This directory is the destination of the RTL generated by the
HLS-based and Chisel-based accelerator design flows in the
accelerators folder. It is the communication point between the ESP
accelerator design flows and the SoC design flow, which can see the
library of available accelerators in the tech folder.
This folder is organized by technology target (FPGA or ASIC):
- Xilinx Virtex 7 (
virtex7) - Virtex Ultrascale (
virtexu) - Ultrascale+ (
virtexup)
The HLS-generated RTL for the accelerators gets installed in the
tech folder corresponding to the selected technology target for the
HLS. The acc subfolder is for the accelerator RTL. The memgen
subfolder is for the accelerator local memory generated with the
PLMGen tool (tools/plmgen) for the SystemC accelerators. The
sccs subfolder is for any non-accelerator component generated with
HLS, like the SystemC implementation of the caches.