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saa7115.c
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/* saa711x - Philips SAA711x video decoder driver
* This driver can work with saa7111, saa7111a, saa7113, saa7114,
* saa7115 and saa7118.
*
* Based on saa7114 driver by Maxim Yevtyushkin, which is based on
* the saa7111 driver by Dave Perks.
*
* Copyright (C) 1998 Dave Perks <[email protected]>
* Copyright (C) 2002 Maxim Yevtyushkin <[email protected]>
*
* Slight changes for video timing and attachment output by
* Wolfgang Scherr <[email protected]>
*
* Moved over to the linux >= 2.4.x i2c protocol (1/1/2003)
* by Ronald Bultje <[email protected]>
*
* Added saa7115 support by Kevin Thayer <nufan_wfk at yahoo.com>
* (2/17/2003)
*
* VBI support (2004) and cleanups (2005) by Hans Verkuil <[email protected]>
*
* Copyright (c) 2005-2006 Mauro Carvalho Chehab <[email protected]>
* SAA7111, SAA7113 and SAA7118 support
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include "saa711x_regs.h"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/videodev2.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>
#include <media/saa7115.h>
#include <asm/div64.h>
#define VRES_60HZ (480+16)
MODULE_DESCRIPTION("Philips SAA7111/SAA7113/SAA7114/SAA7115/SAA7118 video decoder driver");
MODULE_AUTHOR( "Maxim Yevtyushkin, Kevin Thayer, Chris Kennedy, "
"Hans Verkuil, Mauro Carvalho Chehab");
MODULE_LICENSE("GPL");
static bool debug;
module_param(debug, bool, 0644);
MODULE_PARM_DESC(debug, "Debug level (0-1)");
enum saa711x_model {
SAA7111A,
SAA7111,
SAA7113,
GM7113C,
SAA7114,
SAA7115,
SAA7118,
};
struct saa711x_state {
struct v4l2_subdev sd;
struct v4l2_ctrl_handler hdl;
struct {
/* chroma gain control cluster */
struct v4l2_ctrl *agc;
struct v4l2_ctrl *gain;
};
v4l2_std_id std;
int input;
int output;
int enable;
int radio;
int width;
int height;
enum saa711x_model ident;
u32 audclk_freq;
u32 crystal_freq;
bool ucgc;
u8 cgcdiv;
bool apll;
bool double_asclk;
};
static inline struct saa711x_state *to_state(struct v4l2_subdev *sd)
{
return container_of(sd, struct saa711x_state, sd);
}
static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
{
return &container_of(ctrl->handler, struct saa711x_state, hdl)->sd;
}
/* ----------------------------------------------------------------------- */
static inline int saa711x_write(struct v4l2_subdev *sd, u8 reg, u8 value)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
return i2c_smbus_write_byte_data(client, reg, value);
}
/* Sanity routine to check if a register is present */
static int saa711x_has_reg(const int id, const u8 reg)
{
if (id == SAA7111)
return reg < 0x20 && reg != 0x01 && reg != 0x0f &&
(reg < 0x13 || reg > 0x19) && reg != 0x1d && reg != 0x1e;
if (id == SAA7111A)
return reg < 0x20 && reg != 0x01 && reg != 0x0f &&
reg != 0x14 && reg != 0x18 && reg != 0x19 &&
reg != 0x1d && reg != 0x1e;
/* common for saa7113/4/5/8 */
if (unlikely((reg >= 0x3b && reg <= 0x3f) || reg == 0x5c || reg == 0x5f ||
reg == 0xa3 || reg == 0xa7 || reg == 0xab || reg == 0xaf || (reg >= 0xb5 && reg <= 0xb7) ||
reg == 0xd3 || reg == 0xd7 || reg == 0xdb || reg == 0xdf || (reg >= 0xe5 && reg <= 0xe7) ||
reg == 0x82 || (reg >= 0x89 && reg <= 0x8e)))
return 0;
switch (id) {
case GM7113C:
return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && reg < 0x20;
case SAA7113:
return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && (reg < 0x20 || reg > 0x3f) &&
reg != 0x5d && reg < 0x63;
case SAA7114:
return (reg < 0x1a || reg > 0x1e) && (reg < 0x20 || reg > 0x2f) &&
(reg < 0x63 || reg > 0x7f) && reg != 0x33 && reg != 0x37 &&
reg != 0x81 && reg < 0xf0;
case SAA7115:
return (reg < 0x20 || reg > 0x2f) && reg != 0x65 && (reg < 0xfc || reg > 0xfe);
case SAA7118:
return (reg < 0x1a || reg > 0x1d) && (reg < 0x20 || reg > 0x22) &&
(reg < 0x26 || reg > 0x28) && reg != 0x33 && reg != 0x37 &&
(reg < 0x63 || reg > 0x7f) && reg != 0x81 && reg < 0xf0;
}
return 1;
}
static int saa711x_writeregs(struct v4l2_subdev *sd, const unsigned char *regs)
{
struct saa711x_state *state = to_state(sd);
unsigned char reg, data;
while (*regs != 0x00) {
reg = *(regs++);
data = *(regs++);
/* According with datasheets, reserved regs should be
filled with 0 - seems better not to touch on they */
if (saa711x_has_reg(state->ident, reg)) {
if (saa711x_write(sd, reg, data) < 0)
return -1;
} else {
v4l2_dbg(1, debug, sd, "tried to access reserved reg 0x%02x\n", reg);
}
}
return 0;
}
static inline int saa711x_read(struct v4l2_subdev *sd, u8 reg)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
return i2c_smbus_read_byte_data(client, reg);
}
/* ----------------------------------------------------------------------- */
/* SAA7111 initialization table */
static const unsigned char saa7111_init[] = {
R_01_INC_DELAY, 0x00, /* reserved */
/*front end */
R_02_INPUT_CNTL_1, 0xd0, /* FUSE=3, GUDL=2, MODE=0 */
R_03_INPUT_CNTL_2, 0x23, /* HLNRS=0, VBSL=1, WPOFF=0, HOLDG=0,
* GAFIX=0, GAI1=256, GAI2=256 */
R_04_INPUT_CNTL_3, 0x00, /* GAI1=256 */
R_05_INPUT_CNTL_4, 0x00, /* GAI2=256 */
/* decoder */
R_06_H_SYNC_START, 0xf3, /* HSB at 13(50Hz) / 17(60Hz)
* pixels after end of last line */
R_07_H_SYNC_STOP, 0xe8, /* HSS seems to be needed to
* work with NTSC, too */
R_08_SYNC_CNTL, 0xc8, /* AUFD=1, FSEL=1, EXFIL=0,
* VTRC=1, HPLL=0, VNOI=0 */
R_09_LUMA_CNTL, 0x01, /* BYPS=0, PREF=0, BPSS=0,
* VBLB=0, UPTCV=0, APER=1 */
R_0A_LUMA_BRIGHT_CNTL, 0x80,
R_0B_LUMA_CONTRAST_CNTL, 0x47, /* 0b - CONT=1.109 */
R_0C_CHROMA_SAT_CNTL, 0x40,
R_0D_CHROMA_HUE_CNTL, 0x00,
R_0E_CHROMA_CNTL_1, 0x01, /* 0e - CDTO=0, CSTD=0, DCCF=0,
* FCTC=0, CHBW=1 */
R_0F_CHROMA_GAIN_CNTL, 0x00, /* reserved */
R_10_CHROMA_CNTL_2, 0x48, /* 10 - OFTS=1, HDEL=0, VRLN=1, YDEL=0 */
R_11_MODE_DELAY_CNTL, 0x1c, /* 11 - GPSW=0, CM99=0, FECO=0, COMPO=1,
* OEYC=1, OEHV=1, VIPB=0, COLO=0 */
R_12_RT_SIGNAL_CNTL, 0x00, /* 12 - output control 2 */
R_13_RT_X_PORT_OUT_CNTL, 0x00, /* 13 - output control 3 */
R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
R_15_VGATE_START_FID_CHG, 0x00,
R_16_VGATE_STOP, 0x00,
R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
0x00, 0x00
};
/*
* This table has one illegal value, and some values that are not
* correct according to the datasheet initialization table.
*
* If you need a table with legal/default values tell the driver in
* i2c_board_info.platform_data, and you will get the gm7113c_init
* table instead.
*/
/* SAA7113 Init codes */
static const unsigned char saa7113_init[] = {
R_01_INC_DELAY, 0x08,
R_02_INPUT_CNTL_1, 0xc2,
R_03_INPUT_CNTL_2, 0x30,
R_04_INPUT_CNTL_3, 0x00,
R_05_INPUT_CNTL_4, 0x00,
R_06_H_SYNC_START, 0x89, /* Illegal value -119,
* min. value = -108 (0x94) */
R_07_H_SYNC_STOP, 0x0d,
R_08_SYNC_CNTL, 0x88, /* Not datasheet default.
* HTC = VTR mode, should be 0x98 */
R_09_LUMA_CNTL, 0x01,
R_0A_LUMA_BRIGHT_CNTL, 0x80,
R_0B_LUMA_CONTRAST_CNTL, 0x47,
R_0C_CHROMA_SAT_CNTL, 0x40,
R_0D_CHROMA_HUE_CNTL, 0x00,
R_0E_CHROMA_CNTL_1, 0x01,
R_0F_CHROMA_GAIN_CNTL, 0x2a,
R_10_CHROMA_CNTL_2, 0x08, /* Not datsheet default.
* VRLN enabled, should be 0x00 */
R_11_MODE_DELAY_CNTL, 0x0c,
R_12_RT_SIGNAL_CNTL, 0x07, /* Not datasheet default,
* should be 0x01 */
R_13_RT_X_PORT_OUT_CNTL, 0x00,
R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
R_15_VGATE_START_FID_CHG, 0x00,
R_16_VGATE_STOP, 0x00,
R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
0x00, 0x00
};
/*
* GM7113C is a clone of the SAA7113 chip
* This init table is copied out of the saa7113 datasheet.
* In R_08 we enable "Automatic Field Detection" [AUFD],
* this is disabled when saa711x_set_v4lstd is called.
*/
static const unsigned char gm7113c_init[] = {
R_01_INC_DELAY, 0x08,
R_02_INPUT_CNTL_1, 0xc0,
R_03_INPUT_CNTL_2, 0x33,
R_04_INPUT_CNTL_3, 0x00,
R_05_INPUT_CNTL_4, 0x00,
R_06_H_SYNC_START, 0xe9,
R_07_H_SYNC_STOP, 0x0d,
R_08_SYNC_CNTL, 0x98,
R_09_LUMA_CNTL, 0x01,
R_0A_LUMA_BRIGHT_CNTL, 0x80,
R_0B_LUMA_CONTRAST_CNTL, 0x47,
R_0C_CHROMA_SAT_CNTL, 0x40,
R_0D_CHROMA_HUE_CNTL, 0x00,
R_0E_CHROMA_CNTL_1, 0x01,
R_0F_CHROMA_GAIN_CNTL, 0x2a,
R_10_CHROMA_CNTL_2, 0x00,
R_11_MODE_DELAY_CNTL, 0x0c,
R_12_RT_SIGNAL_CNTL, 0x01,
R_13_RT_X_PORT_OUT_CNTL, 0x00,
R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
R_15_VGATE_START_FID_CHG, 0x00,
R_16_VGATE_STOP, 0x00,
R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
0x00, 0x00
};
/* If a value differs from the Hauppauge driver values, then the comment starts with
'was 0xXX' to denote the Hauppauge value. Otherwise the value is identical to what the
Hauppauge driver sets. */
/* SAA7114 and SAA7115 initialization table */
static const unsigned char saa7115_init_auto_input[] = {
/* Front-End Part */
R_01_INC_DELAY, 0x48, /* white peak control disabled */
R_03_INPUT_CNTL_2, 0x20, /* was 0x30. 0x20: long vertical blanking */
R_04_INPUT_CNTL_3, 0x90, /* analog gain set to 0 */
R_05_INPUT_CNTL_4, 0x90, /* analog gain set to 0 */
/* Decoder Part */
R_06_H_SYNC_START, 0xeb, /* horiz sync begin = -21 */
R_07_H_SYNC_STOP, 0xe0, /* horiz sync stop = -17 */
R_09_LUMA_CNTL, 0x53, /* 0x53, was 0x56 for 60hz. luminance control */
R_0A_LUMA_BRIGHT_CNTL, 0x80, /* was 0x88. decoder brightness, 0x80 is itu standard */
R_0B_LUMA_CONTRAST_CNTL, 0x44, /* was 0x48. decoder contrast, 0x44 is itu standard */
R_0C_CHROMA_SAT_CNTL, 0x40, /* was 0x47. decoder saturation, 0x40 is itu standard */
R_0D_CHROMA_HUE_CNTL, 0x00,
R_0F_CHROMA_GAIN_CNTL, 0x00, /* use automatic gain */
R_10_CHROMA_CNTL_2, 0x06, /* chroma: active adaptive combfilter */
R_11_MODE_DELAY_CNTL, 0x00,
R_12_RT_SIGNAL_CNTL, 0x9d, /* RTS0 output control: VGATE */
R_13_RT_X_PORT_OUT_CNTL, 0x80, /* ITU656 standard mode, RTCO output enable RTCE */
R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
R_18_RAW_DATA_GAIN_CNTL, 0x40, /* gain 0x00 = nominal */
R_19_RAW_DATA_OFF_CNTL, 0x80,
R_1A_COLOR_KILL_LVL_CNTL, 0x77, /* recommended value */
R_1B_MISC_TVVCRDET, 0x42, /* recommended value */
R_1C_ENHAN_COMB_CTRL1, 0xa9, /* recommended value */
R_1D_ENHAN_COMB_CTRL2, 0x01, /* recommended value */
R_80_GLOBAL_CNTL_1, 0x0, /* No tasks enabled at init */
/* Power Device Control */
R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset device */
R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* set device programmed, all in operational mode */
0x00, 0x00
};
/* Used to reset saa7113, saa7114 and saa7115 */
static const unsigned char saa7115_cfg_reset_scaler[] = {
R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00, /* disable I-port output */
R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* enable I-port output */
0x00, 0x00
};
/* ============== SAA7715 VIDEO templates ============= */
static const unsigned char saa7115_cfg_60hz_video[] = {
R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
R_15_VGATE_START_FID_CHG, 0x03,
R_16_VGATE_STOP, 0x11,
R_17_MISC_VGATE_CONF_AND_MSB, 0x9c,
R_08_SYNC_CNTL, 0x68, /* 0xBO: auto detection, 0x68 = NTSC */
R_0E_CHROMA_CNTL_1, 0x07, /* video autodetection is on */
R_5A_V_OFF_FOR_SLICER, 0x06, /* standard 60hz value for ITU656 line counting */
/* Task A */
R_90_A_TASK_HANDLING_CNTL, 0x80,
R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
/* hoffset low (input), 0x0002 is minimum */
R_94_A_HORIZ_INPUT_WINDOW_START, 0x01,
R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
/* hsize low (input), 0x02d0 = 720 */
R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
R_98_A_VERT_INPUT_WINDOW_START, 0x05,
R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x0c,
R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,
R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x0c,
R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,
/* Task B */
R_C0_B_TASK_HANDLING_CNTL, 0x00,
R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
/* 0x0002 is minimum */
R_C4_B_HORIZ_INPUT_WINDOW_START, 0x02,
R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
/* 0x02d0 = 720 */
R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
/* vwindow start 0x12 = 18 */
R_C8_B_VERT_INPUT_WINDOW_START, 0x12,
R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
/* vwindow length 0xf8 = 248 */
R_CA_B_VERT_INPUT_WINDOW_LENGTH, VRES_60HZ>>1,
R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, VRES_60HZ>>9,
/* hwindow 0x02d0 = 720 */
R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
R_F0_LFCO_PER_LINE, 0xad, /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */
R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0 */
R_F5_PULSGEN_LINE_LENGTH, 0xad,
R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
0x00, 0x00
};
static const unsigned char saa7115_cfg_50hz_video[] = {
R_80_GLOBAL_CNTL_1, 0x00,
R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
R_15_VGATE_START_FID_CHG, 0x37, /* VGATE start */
R_16_VGATE_STOP, 0x16,
R_17_MISC_VGATE_CONF_AND_MSB, 0x99,
R_08_SYNC_CNTL, 0x28, /* 0x28 = PAL */
R_0E_CHROMA_CNTL_1, 0x07,
R_5A_V_OFF_FOR_SLICER, 0x03, /* standard 50hz value */
/* Task A */
R_90_A_TASK_HANDLING_CNTL, 0x81,
R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
/* This is weird: the datasheet says that you should use 2 as the minimum value, */
/* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
/* hoffset low (input), 0x0002 is minimum */
R_94_A_HORIZ_INPUT_WINDOW_START, 0x00,
R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
/* hsize low (input), 0x02d0 = 720 */
R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
R_98_A_VERT_INPUT_WINDOW_START, 0x03,
R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
/* vsize 0x12 = 18 */
R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x12,
R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
/* hsize 0x05a0 = 1440 */
R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05, /* hsize hi (output) */
R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x12, /* vsize low (output), 0x12 = 18 */
R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00, /* vsize hi (output) */
/* Task B */
R_C0_B_TASK_HANDLING_CNTL, 0x00,
R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
/* This is weird: the datasheet says that you should use 2 as the minimum value, */
/* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
/* hoffset low (input), 0x0002 is minimum. See comment above. */
R_C4_B_HORIZ_INPUT_WINDOW_START, 0x00,
R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
/* hsize 0x02d0 = 720 */
R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
/* voffset 0x16 = 22 */
R_C8_B_VERT_INPUT_WINDOW_START, 0x16,
R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
/* vsize 0x0120 = 288 */
R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0x20,
R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x01,
/* hsize 0x02d0 = 720 */
R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
R_F0_LFCO_PER_LINE, 0xb0, /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */
R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0, (was 0x05) */
R_F5_PULSGEN_LINE_LENGTH, 0xb0,
R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
0x00, 0x00
};
/* ============== SAA7715 VIDEO templates (end) ======= */
static const unsigned char saa7115_cfg_vbi_on[] = {
R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
R_80_GLOBAL_CNTL_1, 0x30, /* Activate both tasks */
R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */
0x00, 0x00
};
static const unsigned char saa7115_cfg_vbi_off[] = {
R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
R_80_GLOBAL_CNTL_1, 0x20, /* Activate only task "B" */
R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */
0x00, 0x00
};
static const unsigned char saa7115_init_misc[] = {
R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F, 0x01,
R_83_X_PORT_I_O_ENA_AND_OUT_CLK, 0x01,
R_84_I_PORT_SIGNAL_DEF, 0x20,
R_85_I_PORT_SIGNAL_POLAR, 0x21,
R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT, 0xc5,
R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,
/* Task A */
R_A0_A_HORIZ_PRESCALING, 0x01,
R_A1_A_ACCUMULATION_LENGTH, 0x00,
R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
/* Configure controls at nominal value*/
R_A4_A_LUMA_BRIGHTNESS_CNTL, 0x80,
R_A5_A_LUMA_CONTRAST_CNTL, 0x40,
R_A6_A_CHROMA_SATURATION_CNTL, 0x40,
/* note: 2 x zoom ensures that VBI lines have same length as video lines. */
R_A8_A_HORIZ_LUMA_SCALING_INC, 0x00,
R_A9_A_HORIZ_LUMA_SCALING_INC_MSB, 0x02,
R_AA_A_HORIZ_LUMA_PHASE_OFF, 0x00,
/* must be horiz lum scaling / 2 */
R_AC_A_HORIZ_CHROMA_SCALING_INC, 0x00,
R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB, 0x01,
/* must be offset luma / 2 */
R_AE_A_HORIZ_CHROMA_PHASE_OFF, 0x00,
R_B0_A_VERT_LUMA_SCALING_INC, 0x00,
R_B1_A_VERT_LUMA_SCALING_INC_MSB, 0x04,
R_B2_A_VERT_CHROMA_SCALING_INC, 0x00,
R_B3_A_VERT_CHROMA_SCALING_INC_MSB, 0x04,
R_B4_A_VERT_SCALING_MODE_CNTL, 0x01,
R_B8_A_VERT_CHROMA_PHASE_OFF_00, 0x00,
R_B9_A_VERT_CHROMA_PHASE_OFF_01, 0x00,
R_BA_A_VERT_CHROMA_PHASE_OFF_10, 0x00,
R_BB_A_VERT_CHROMA_PHASE_OFF_11, 0x00,
R_BC_A_VERT_LUMA_PHASE_OFF_00, 0x00,
R_BD_A_VERT_LUMA_PHASE_OFF_01, 0x00,
R_BE_A_VERT_LUMA_PHASE_OFF_10, 0x00,
R_BF_A_VERT_LUMA_PHASE_OFF_11, 0x00,
/* Task B */
R_D0_B_HORIZ_PRESCALING, 0x01,
R_D1_B_ACCUMULATION_LENGTH, 0x00,
R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
/* Configure controls at nominal value*/
R_D4_B_LUMA_BRIGHTNESS_CNTL, 0x80,
R_D5_B_LUMA_CONTRAST_CNTL, 0x40,
R_D6_B_CHROMA_SATURATION_CNTL, 0x40,
/* hor lum scaling 0x0400 = 1 */
R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00,
R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
R_DA_B_HORIZ_LUMA_PHASE_OFF, 0x00,
/* must be hor lum scaling / 2 */
R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,
/* must be offset luma / 2 */
R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA, 0x00,
R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,
R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
R_E4_B_VERT_SCALING_MODE_CNTL, 0x01,
R_E8_B_VERT_CHROMA_PHASE_OFF_00, 0x00,
R_E9_B_VERT_CHROMA_PHASE_OFF_01, 0x00,
R_EA_B_VERT_CHROMA_PHASE_OFF_10, 0x00,
R_EB_B_VERT_CHROMA_PHASE_OFF_11, 0x00,
R_EC_B_VERT_LUMA_PHASE_OFF_00, 0x00,
R_ED_B_VERT_LUMA_PHASE_OFF_01, 0x00,
R_EE_B_VERT_LUMA_PHASE_OFF_10, 0x00,
R_EF_B_VERT_LUMA_PHASE_OFF_11, 0x00,
R_F2_NOMINAL_PLL2_DTO, 0x50, /* crystal clock = 24.576 MHz, target = 27MHz */
R_F3_PLL_INCREMENT, 0x46,
R_F4_PLL2_STATUS, 0x00,
R_F7_PULSE_A_POS_MSB, 0x4b, /* not the recommended settings! */
R_F8_PULSE_B_POS, 0x00,
R_F9_PULSE_B_POS_MSB, 0x4b,
R_FA_PULSE_C_POS, 0x00,
R_FB_PULSE_C_POS_MSB, 0x4b,
/* PLL2 lock detection settings: 71 lines 50% phase error */
R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES, 0x88,
/* Turn off VBI */
R_40_SLICER_CNTL_1, 0x20, /* No framing code errors allowed. */
R_41_LCR_BASE, 0xff,
R_41_LCR_BASE+1, 0xff,
R_41_LCR_BASE+2, 0xff,
R_41_LCR_BASE+3, 0xff,
R_41_LCR_BASE+4, 0xff,
R_41_LCR_BASE+5, 0xff,
R_41_LCR_BASE+6, 0xff,
R_41_LCR_BASE+7, 0xff,
R_41_LCR_BASE+8, 0xff,
R_41_LCR_BASE+9, 0xff,
R_41_LCR_BASE+10, 0xff,
R_41_LCR_BASE+11, 0xff,
R_41_LCR_BASE+12, 0xff,
R_41_LCR_BASE+13, 0xff,
R_41_LCR_BASE+14, 0xff,
R_41_LCR_BASE+15, 0xff,
R_41_LCR_BASE+16, 0xff,
R_41_LCR_BASE+17, 0xff,
R_41_LCR_BASE+18, 0xff,
R_41_LCR_BASE+19, 0xff,
R_41_LCR_BASE+20, 0xff,
R_41_LCR_BASE+21, 0xff,
R_41_LCR_BASE+22, 0xff,
R_58_PROGRAM_FRAMING_CODE, 0x40,
R_59_H_OFF_FOR_SLICER, 0x47,
R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF, 0x83,
R_5D_DID, 0xbd,
R_5E_SDID, 0x35,
R_02_INPUT_CNTL_1, 0xc4, /* input tuner -> input 4, amplifier active */
R_80_GLOBAL_CNTL_1, 0x20, /* enable task B */
R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,
R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,
0x00, 0x00
};
static int saa711x_odd_parity(u8 c)
{
c ^= (c >> 4);
c ^= (c >> 2);
c ^= (c >> 1);
return c & 1;
}
static int saa711x_decode_vps(u8 *dst, u8 *p)
{
static const u8 biphase_tbl[] = {
0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
0xc3, 0x4b, 0x43, 0xc3, 0x87, 0x0f, 0x07, 0x87,
0x83, 0x0b, 0x03, 0x83, 0xc3, 0x4b, 0x43, 0xc3,
0xc1, 0x49, 0x41, 0xc1, 0x85, 0x0d, 0x05, 0x85,
0x81, 0x09, 0x01, 0x81, 0xc1, 0x49, 0x41, 0xc1,
0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
0xc2, 0x4a, 0x42, 0xc2, 0x86, 0x0e, 0x06, 0x86,
0x82, 0x0a, 0x02, 0x82, 0xc2, 0x4a, 0x42, 0xc2,
0xc0, 0x48, 0x40, 0xc0, 0x84, 0x0c, 0x04, 0x84,
0x80, 0x08, 0x00, 0x80, 0xc0, 0x48, 0x40, 0xc0,
0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
};
int i;
u8 c, err = 0;
for (i = 0; i < 2 * 13; i += 2) {
err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]];
c = (biphase_tbl[p[i + 1]] & 0xf) | ((biphase_tbl[p[i]] & 0xf) << 4);
dst[i / 2] = c;
}
return err & 0xf0;
}
static int saa711x_decode_wss(u8 *p)
{
static const int wss_bits[8] = {
0, 0, 0, 1, 0, 1, 1, 1
};
unsigned char parity;
int wss = 0;
int i;
for (i = 0; i < 16; i++) {
int b1 = wss_bits[p[i] & 7];
int b2 = wss_bits[(p[i] >> 3) & 7];
if (b1 == b2)
return -1;
wss |= b2 << i;
}
parity = wss & 15;
parity ^= parity >> 2;
parity ^= parity >> 1;
if (!(parity & 1))
return -1;
return wss;
}
static int saa711x_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
{
struct saa711x_state *state = to_state(sd);
u32 acpf;
u32 acni;
u32 hz;
u64 f;
u8 acc = 0; /* reg 0x3a, audio clock control */
/* Checks for chips that don't have audio clock (saa7111, saa7113) */
if (!saa711x_has_reg(state->ident, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD))
return 0;
v4l2_dbg(1, debug, sd, "set audio clock freq: %d\n", freq);
/* sanity check */
if (freq < 32000 || freq > 48000)
return -EINVAL;
/* hz is the refresh rate times 100 */
hz = (state->std & V4L2_STD_525_60) ? 5994 : 5000;
/* acpf = (256 * freq) / field_frequency == (256 * 100 * freq) / hz */
acpf = (25600 * freq) / hz;
/* acni = (256 * freq * 2^23) / crystal_frequency =
(freq * 2^(8+23)) / crystal_frequency =
(freq << 31) / crystal_frequency */
f = freq;
f = f << 31;
do_div(f, state->crystal_freq);
acni = f;
if (state->ucgc) {
acpf = acpf * state->cgcdiv / 16;
acni = acni * state->cgcdiv / 16;
acc = 0x80;
if (state->cgcdiv == 3)
acc |= 0x40;
}
if (state->apll)
acc |= 0x08;
if (state->double_asclk) {
acpf <<= 1;
acni <<= 1;
}
saa711x_write(sd, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03);
saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10 << state->double_asclk);
saa711x_write(sd, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc);
saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff);
saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+1,
(acpf >> 8) & 0xff);
saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+2,
(acpf >> 16) & 0x03);
saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC, acni & 0xff);
saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+1, (acni >> 8) & 0xff);
saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+2, (acni >> 16) & 0x3f);
state->audclk_freq = freq;
return 0;
}
static int saa711x_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
{
struct v4l2_subdev *sd = to_sd(ctrl);
struct saa711x_state *state = to_state(sd);
switch (ctrl->id) {
case V4L2_CID_CHROMA_AGC:
/* chroma gain cluster */
if (state->agc->val)
state->gain->val =
saa711x_read(sd, R_0F_CHROMA_GAIN_CNTL) & 0x7f;
break;
}
return 0;
}
static int saa711x_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct v4l2_subdev *sd = to_sd(ctrl);
struct saa711x_state *state = to_state(sd);
switch (ctrl->id) {
case V4L2_CID_BRIGHTNESS:
saa711x_write(sd, R_0A_LUMA_BRIGHT_CNTL, ctrl->val);
break;
case V4L2_CID_CONTRAST:
saa711x_write(sd, R_0B_LUMA_CONTRAST_CNTL, ctrl->val);
break;
case V4L2_CID_SATURATION:
saa711x_write(sd, R_0C_CHROMA_SAT_CNTL, ctrl->val);
break;
case V4L2_CID_HUE:
saa711x_write(sd, R_0D_CHROMA_HUE_CNTL, ctrl->val);
break;
case V4L2_CID_CHROMA_AGC:
/* chroma gain cluster */
if (state->agc->val)
saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val);
else
saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val | 0x80);
break;
default:
return -EINVAL;
}
return 0;
}
static int saa711x_set_size(struct v4l2_subdev *sd, int width, int height)
{
struct saa711x_state *state = to_state(sd);
int HPSC, HFSC;
int VSCY;
int res;
int is_50hz = state->std & V4L2_STD_625_50;
int Vsrc = is_50hz ? 576 : 480;
v4l2_dbg(1, debug, sd, "decoder set size to %ix%i\n", width, height);
/* FIXME need better bounds checking here */
if ((width < 1) || (width > 1440))
return -EINVAL;
if ((height < 1) || (height > Vsrc))
return -EINVAL;
if (!saa711x_has_reg(state->ident, R_D0_B_HORIZ_PRESCALING)) {
/* Decoder only supports 720 columns and 480 or 576 lines */
if (width != 720)
return -EINVAL;
if (height != Vsrc)
return -EINVAL;
}
state->width = width;
state->height = height;
if (!saa711x_has_reg(state->ident, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH))
return 0;
/* probably have a valid size, let's set it */
/* Set output width/height */
/* width */
saa711x_write(sd, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,
(u8) (width & 0xff));
saa711x_write(sd, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB,
(u8) ((width >> 8) & 0xff));
/* Vertical Scaling uses height/2 */
res = height / 2;
/* On 60Hz, it is using a higher Vertical Output Size */
if (!is_50hz)
res += (VRES_60HZ - 480) >> 1;
/* height */
saa711x_write(sd, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,
(u8) (res & 0xff));
saa711x_write(sd, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB,
(u8) ((res >> 8) & 0xff));
/* Scaling settings */
/* Hprescaler is floor(inres/outres) */
HPSC = (int)(720 / width);
/* 0 is not allowed (div. by zero) */
HPSC = HPSC ? HPSC : 1;
HFSC = (int)((1024 * 720) / (HPSC * width));
/* FIXME hardcodes to "Task B"
* write H prescaler integer */
saa711x_write(sd, R_D0_B_HORIZ_PRESCALING,
(u8) (HPSC & 0x3f));
v4l2_dbg(1, debug, sd, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC);
/* write H fine-scaling (luminance) */
saa711x_write(sd, R_D8_B_HORIZ_LUMA_SCALING_INC,
(u8) (HFSC & 0xff));
saa711x_write(sd, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB,
(u8) ((HFSC >> 8) & 0xff));
/* write H fine-scaling (chrominance)
* must be lum/2, so i'll just bitshift :) */
saa711x_write(sd, R_DC_B_HORIZ_CHROMA_SCALING,
(u8) ((HFSC >> 1) & 0xff));
saa711x_write(sd, R_DD_B_HORIZ_CHROMA_SCALING_MSB,
(u8) ((HFSC >> 9) & 0xff));
VSCY = (int)((1024 * Vsrc) / height);
v4l2_dbg(1, debug, sd, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY);
/* Correct Contrast and Luminance */
saa711x_write(sd, R_D5_B_LUMA_CONTRAST_CNTL,
(u8) (64 * 1024 / VSCY));
saa711x_write(sd, R_D6_B_CHROMA_SATURATION_CNTL,
(u8) (64 * 1024 / VSCY));
/* write V fine-scaling (luminance) */
saa711x_write(sd, R_E0_B_VERT_LUMA_SCALING_INC,
(u8) (VSCY & 0xff));
saa711x_write(sd, R_E1_B_VERT_LUMA_SCALING_INC_MSB,
(u8) ((VSCY >> 8) & 0xff));
/* write V fine-scaling (chrominance) */
saa711x_write(sd, R_E2_B_VERT_CHROMA_SCALING_INC,
(u8) (VSCY & 0xff));
saa711x_write(sd, R_E3_B_VERT_CHROMA_SCALING_INC_MSB,
(u8) ((VSCY >> 8) & 0xff));
saa711x_writeregs(sd, saa7115_cfg_reset_scaler);
/* Activates task "B" */
saa711x_write(sd, R_80_GLOBAL_CNTL_1,
saa711x_read(sd, R_80_GLOBAL_CNTL_1) | 0x20);
return 0;
}
static void saa711x_set_v4lstd(struct v4l2_subdev *sd, v4l2_std_id std)
{
struct saa711x_state *state = to_state(sd);
/* Prevent unnecessary standard changes. During a standard
change the I-Port is temporarily disabled. Any devices
reading from that port can get confused.
Note that s_std is also used to switch from
radio to TV mode, so if a s_std is broadcast to
all I2C devices then you do not want to have an unwanted
side-effect here. */
if (std == state->std)
return;
state->std = std;
// This works for NTSC-M, SECAM-L and the 50Hz PAL variants.
if (std & V4L2_STD_525_60) {
v4l2_dbg(1, debug, sd, "decoder set standard 60 Hz\n");
if (state->ident == GM7113C) {
u8 reg = saa711x_read(sd, R_08_SYNC_CNTL);
reg &= ~(SAA7113_R_08_FSEL | SAA7113_R_08_AUFD);
reg |= SAA7113_R_08_FSEL;
saa711x_write(sd, R_08_SYNC_CNTL, reg);
} else {
saa711x_writeregs(sd, saa7115_cfg_60hz_video);
}