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Merge tag 'pci-v3.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas: "The interesting things here are: - Turn on Config Request Retry Status Software Visibility. This caused hangs last time, but we included a fix this time. - Rework PCI device configuration to use _HPP/_HPX more aggressively - Allow PCI devices to be put into D3cold during system suspend - Add arm64 PCI support - Add APM X-Gene host bridge driver - Add TI Keystone host bridge driver - Add Xilinx AXI host bridge driver More detailed summary: Enumeration - Check Vendor ID only for Config Request Retry Status (Rajat Jain) - Enable Config Request Retry Status when supported (Rajat Jain) - Add generic domain handling (Catalin Marinas) - Generate uppercase hex for modalias interface class (Ricardo Ribalda Delgado) Resource management - Add missing MEM_64 mask in pci_assign_unassigned_bridge_resources() (Yinghai Lu) - Increase IBM ipr SAS Crocodile BARs to at least system page size (Douglas Lehr) PCI device hotplug - Prevent NULL dereference during pciehp probe (Andreas Noever) - Move _HPP & _HPX handling into core (Bjorn Helgaas) - Apply _HPP to PCIe devices as well as PCI (Bjorn Helgaas) - Apply _HPP/_HPX to display devices (Bjorn Helgaas) - Preserve SERR & PARITY settings when applying _HPP/_HPX (Bjorn Helgaas) - Preserve MPS and MRRS settings when applying _HPP/_HPX (Bjorn Helgaas) - Apply _HPP/_HPX to all devices, not just hot-added ones (Bjorn Helgaas) - Fix wait time in pciehp timeout message (Yinghai Lu) - Add more pciehp Slot Control debug output (Yinghai Lu) - Stop disabling pciehp notifications during init (Yinghai Lu) MSI - Remove arch_msi_check_device() (Alexander Gordeev) - Rename pci_msi_check_device() to pci_msi_supported() (Alexander Gordeev) - Move D0 check into pci_msi_check_device() (Alexander Gordeev) - Remove unused kobject from struct msi_desc (Yijing Wang) - Remove "pos" from the struct msi_desc msi_attrib (Yijing Wang) - Add "msi_bus" sysfs MSI/MSI-X control for endpoints (Yijing Wang) - Use __get_cached_msi_msg() instead of get_cached_msi_msg() (Yijing Wang) - Use __read_msi_msg() instead of read_msi_msg() (Yijing Wang) - Use __write_msi_msg() instead of write_msi_msg() (Yijing Wang) Power management - Drop unused runtime PM support code for PCIe ports (Rafael J. Wysocki) - Allow PCI devices to be put into D3cold during system suspend (Rafael J. Wysocki) AER - Add additional AER error strings (Gong Chen) - Make <linux/aer.h> standalone includable (Thierry Reding) Virtualization - Add ACS quirk for Solarflare SFC9120 & SFC9140 (Alex Williamson) - Add ACS quirk for Intel 10G NICs (Alex Williamson) - Add ACS quirk for AMD A88X southbridge (Marti Raudsepp) - Remove unused pci_find_upstream_pcie_bridge(), pci_get_dma_source() (Alex Williamson) - Add device flag helpers (Ethan Zhao) - Assume all Mellanox devices have broken INTx masking (Gavin Shan) Generic host bridge driver - Fix ioport_map() for !CONFIG_GENERIC_IOMAP (Liviu Dudau) - Add pci_register_io_range() and pci_pio_to_address() (Liviu Dudau) - Define PCI_IOBASE as the base of virtual PCI IO space (Liviu Dudau) - Fix the conversion of IO ranges into IO resources (Liviu Dudau) - Add pci_get_new_domain_nr() and of_get_pci_domain_nr() (Liviu Dudau) - Add support for parsing PCI host bridge resources from DT (Liviu Dudau) - Add pci_remap_iospace() to map bus I/O resources (Liviu Dudau) - Add arm64 architectural support for PCI (Liviu Dudau) APM X-Gene - Add APM X-Gene PCIe driver (Tanmay Inamdar) - Add arm64 DT APM X-Gene PCIe device tree nodes (Tanmay Inamdar) Freescale i.MX6 - Probe in module_init(), not fs_initcall() (Lucas Stach) - Delay enabling reference clock for SS until it stabilizes (Tim Harvey) Marvell MVEBU - Fix uninitialized variable in mvebu_get_tgt_attr() (Thomas Petazzoni) NVIDIA Tegra - Make sure the PCIe PLL is really reset (Eric Yuen) - Add error path tegra_msi_teardown_irq() cleanup (Jisheng Zhang) - Fix extended configuration space mapping (Peter Daifuku) - Implement resource hierarchy (Thierry Reding) - Clear CLKREQ# enable on port disable (Thierry Reding) - Add Tegra124 support (Thierry Reding) ST Microelectronics SPEAr13xx - Pass config resource through reg property (Pratyush Anand) Synopsys DesignWare - Use NULL instead of false (Fabio Estevam) - Parse bus-range property from devicetree (Lucas Stach) - Use pci_create_root_bus() instead of pci_scan_root_bus() (Lucas Stach) - Remove pci_assign_unassigned_resources() (Lucas Stach) - Check private_data validity in single place (Lucas Stach) - Setup and clear exactly one MSI at a time (Lucas Stach) - Remove open-coded bitmap operations (Lucas Stach) - Fix configuration base address when using 'reg' (Minghuan Lian) - Fix IO resource end address calculation (Minghuan Lian) - Rename get_msi_data() to get_msi_addr() (Minghuan Lian) - Add get_msi_data() to pcie_host_ops (Minghuan Lian) - Add support for v3.65 hardware (Murali Karicheri) - Fold struct pcie_port_info into struct pcie_port (Pratyush Anand) TI Keystone - Add TI Keystone PCIe driver (Murali Karicheri) - Limit MRSS for all downstream devices (Murali Karicheri) - Assume controller is already in RC mode (Murali Karicheri) - Set device ID based on SoC to support multiple ports (Murali Karicheri) Xilinx AXI - Add Xilinx AXI PCIe driver (Srikanth Thokala) - Fix xilinx_pcie_assign_msi() return value test (Dan Carpenter) Miscellaneous - Clean up whitespace (Quentin Lambert) - Remove assignments from "if" conditions (Quentin Lambert) - Move PCI_VENDOR_ID_VMWARE to pci_ids.h (Francesco Ruggeri) - x86: Mark DMI tables as initialization data (Mathias Krause) - x86: Move __init annotation to the correct place (Mathias Krause) - x86: Mark constants of pci_mmcfg_nvidia_mcp55() as __initconst (Mathias Krause) - x86: Constify pci_mmcfg_probes[] array (Mathias Krause) - x86: Mark PCI BIOS initialization code as such (Mathias Krause) - Parenthesize PCI_DEVID and PCI_VPD_LRDT_ID parameters (Megan Kamiya) - Remove unnecessary variable in pci_add_dynid() (Tobias Klauser)" * tag 'pci-v3.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (109 commits) arm64: dts: Add APM X-Gene PCIe device tree nodes PCI: Add ACS quirk for AMD A88X southbridge devices PCI: xgene: Add APM X-Gene PCIe driver PCI: designware: Remove open-coded bitmap operations PCI/MSI: Remove unnecessary temporary variable PCI/MSI: Use __write_msi_msg() instead of write_msi_msg() MSI/powerpc: Use __read_msi_msg() instead of read_msi_msg() PCI/MSI: Use __get_cached_msi_msg() instead of get_cached_msi_msg() PCI/MSI: Add "msi_bus" sysfs MSI/MSI-X control for endpoints PCI/MSI: Remove "pos" from the struct msi_desc msi_attrib PCI/MSI: Remove unused kobject from struct msi_desc PCI/MSI: Rename pci_msi_check_device() to pci_msi_supported() PCI/MSI: Move D0 check into pci_msi_check_device() PCI/MSI: Remove arch_msi_check_device() irqchip: armada-370-xp: Remove arch_msi_check_device() PCI/MSI/PPC: Remove arch_msi_check_device() arm64: Add architectural support for PCI PCI: Add pci_remap_iospace() to map bus I/O resources of/pci: Add support for parsing PCI host bridge resources from DT of/pci: Add pci_get_new_domain_nr() and of_get_pci_domain_nr() ... Conflicts: arch/arm64/boot/dts/apm-storm.dtsi
2 parents ea58459 + f92d9ee commit 80213c0

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‎Documentation/ABI/testing/sysfs-bus-pci

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Original file line numberDiff line numberDiff line change
@@ -65,6 +65,16 @@ Description:
6565
force a rescan of all PCI buses in the system, and
6666
re-discover previously removed devices.
6767

68+
What: /sys/bus/pci/devices/.../msi_bus
69+
Date: September 2014
70+
Contact: Linux PCI developers <[email protected]>
71+
Description:
72+
Writing a zero value to this attribute disallows MSI and
73+
MSI-X for any future drivers of the device. If the device
74+
is a bridge, MSI and MSI-X will be disallowed for future
75+
drivers of all child devices under the bridge. Drivers
76+
must be reloaded for the new setting to take effect.
77+
6878
What: /sys/bus/pci/devices/.../msi_irqs/
6979
Date: September, 2011
7080
Contact: Neil Horman <[email protected]>

‎Documentation/devicetree/bindings/pci/designware-pcie.txt

+3
Original file line numberDiff line numberDiff line change
@@ -23,3 +23,6 @@ Required properties:
2323

2424
Optional properties:
2525
- reset-gpio: gpio pin number of power good signal
26+
- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
27+
specify this property, to keep backwards compatibility a range of 0x00-0xff
28+
is assumed if not present)

‎Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt

+24-1
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,10 @@
11
NVIDIA Tegra PCIe controller
22

33
Required properties:
4-
- compatible: "nvidia,tegra20-pcie" or "nvidia,tegra30-pcie"
4+
- compatible: Must be one of:
5+
- "nvidia,tegra20-pcie"
6+
- "nvidia,tegra30-pcie"
7+
- "nvidia,tegra124-pcie"
58
- device_type: Must be "pci"
69
- reg: A list of physical base address and length for each set of controller
710
registers. Must contain an entry for each entry in the reg-names property.
@@ -57,6 +60,11 @@ Required properties:
5760
- afi
5861
- pcie_x
5962

63+
Required properties on Tegra124 and later:
64+
- phys: Must contain an entry for each entry in phy-names.
65+
- phy-names: Must include the following entries:
66+
- pcie
67+
6068
Power supplies for Tegra20:
6169
- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
6270
- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
@@ -84,6 +92,21 @@ Power supplies for Tegra30:
8492
- avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
8593
- vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
8694

95+
Power supplies for Tegra124:
96+
- Required:
97+
- avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
98+
- dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
99+
- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
100+
supply 1.05 V.
101+
- hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
102+
Must supply 3.3 V.
103+
- hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
104+
Must supply 3.3 V.
105+
- vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
106+
supply 2.8-3.3 V.
107+
- avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must
108+
supply 1.05 V.
109+
87110
Root ports are defined as subnodes of the PCIe controller node.
88111

89112
Required properties:

‎Documentation/devicetree/bindings/pci/pci-keystone.txt

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@@ -0,0 +1,63 @@
1+
TI Keystone PCIe interface
2+
3+
Keystone PCI host Controller is based on Designware PCI h/w version 3.65.
4+
It shares common functions with PCIe Designware core driver and inherit
5+
common properties defined in
6+
Documentation/devicetree/bindings/pci/designware-pci.txt
7+
8+
Please refer to Documentation/devicetree/bindings/pci/designware-pci.txt
9+
for the details of Designware DT bindings. Additional properties are
10+
described here as well as properties that are not applicable.
11+
12+
Required Properties:-
13+
14+
compatibility: "ti,keystone-pcie"
15+
reg: index 1 is the base address and length of DW application registers.
16+
index 2 is the base address and length of PCI device ID register.
17+
18+
pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
19+
interrupt-cells: should be set to 1
20+
interrupt-parent: Parent interrupt controller phandle
21+
interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
22+
23+
Example:
24+
pcie_msi_intc: msi-interrupt-controller {
25+
interrupt-controller;
26+
#interrupt-cells = <1>;
27+
interrupt-parent = <&gic>;
28+
interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
29+
<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
30+
<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
31+
<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
32+
<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
33+
<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
34+
<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
35+
<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
36+
};
37+
38+
pcie_intc: Interrupt controller device node for Legacy IRQ chip
39+
interrupt-cells: should be set to 1
40+
interrupt-parent: Parent interrupt controller phandle
41+
interrupts: GIC interrupt lines connected to PCI Legacy interrupt lines
42+
43+
Example:
44+
pcie_intc: legacy-interrupt-controller {
45+
interrupt-controller;
46+
#interrupt-cells = <1>;
47+
interrupt-parent = <&gic>;
48+
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
49+
<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
50+
<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
51+
<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
52+
};
53+
54+
Optional properties:-
55+
phys: phandle to Generic Keystone SerDes phy for PCI
56+
phy-names: name of the Generic Keystine SerDes phy for PCI
57+
- If boot loader already does PCI link establishment, then phys and
58+
phy-names shouldn't be present.
59+
60+
Designware DT Properties not applicable for Keystone PCI
61+
62+
1. pcie_bus clock-names not used. Instead, a phandle to phys is used.
63+

‎Documentation/devicetree/bindings/pci/xgene-pci.txt

+57
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@@ -0,0 +1,57 @@
1+
* AppliedMicro X-Gene PCIe interface
2+
3+
Required properties:
4+
- device_type: set to "pci"
5+
- compatible: should contain "apm,xgene-pcie" to identify the core.
6+
- reg: A list of physical base address and length for each set of controller
7+
registers. Must contain an entry for each entry in the reg-names
8+
property.
9+
- reg-names: Must include the following entries:
10+
"csr": controller configuration registers.
11+
"cfg": pcie configuration space registers.
12+
- #address-cells: set to <3>
13+
- #size-cells: set to <2>
14+
- ranges: ranges for the outbound memory, I/O regions.
15+
- dma-ranges: ranges for the inbound memory regions.
16+
- #interrupt-cells: set to <1>
17+
- interrupt-map-mask and interrupt-map: standard PCI properties
18+
to define the mapping of the PCIe interface to interrupt
19+
numbers.
20+
- clocks: from common clock binding: handle to pci clock.
21+
22+
Optional properties:
23+
- status: Either "ok" or "disabled".
24+
- dma-coherent: Present if dma operations are coherent
25+
26+
Example:
27+
28+
SoC specific DT Entry:
29+
30+
pcie0: pcie@1f2b0000 {
31+
status = "disabled";
32+
device_type = "pci";
33+
compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
34+
#interrupt-cells = <1>;
35+
#size-cells = <2>;
36+
#address-cells = <3>;
37+
reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
38+
0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
39+
reg-names = "csr", "cfg";
40+
ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
41+
0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
42+
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
43+
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
44+
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
45+
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
46+
0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
47+
0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
48+
0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
49+
dma-coherent;
50+
clocks = <&pcie0clk 0>;
51+
};
52+
53+
54+
Board specific DT Entry:
55+
&pcie0 {
56+
status = "ok";
57+
};

‎Documentation/devicetree/bindings/pci/xilinx-pcie.txt

+62
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@@ -0,0 +1,62 @@
1+
* Xilinx AXI PCIe Root Port Bridge DT description
2+
3+
Required properties:
4+
- #address-cells: Address representation for root ports, set to <3>
5+
- #size-cells: Size representation for root ports, set to <2>
6+
- #interrupt-cells: specifies the number of cells needed to encode an
7+
interrupt source. The value must be 1.
8+
- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
9+
- reg: Should contain AXI PCIe registers location and length
10+
- device_type: must be "pci"
11+
- interrupts: Should contain AXI PCIe interrupt
12+
- interrupt-map-mask,
13+
interrupt-map: standard PCI properties to define the mapping of the
14+
PCI interface to interrupt numbers.
15+
- ranges: ranges for the PCI memory regions (I/O space region is not
16+
supported by hardware)
17+
Please refer to the standard PCI bus binding document for a more
18+
detailed explanation
19+
20+
Optional properties:
21+
- bus-range: PCI bus numbers covered
22+
23+
Interrupt controller child node
24+
+++++++++++++++++++++++++++++++
25+
Required properties:
26+
- interrupt-controller: identifies the node as an interrupt controller
27+
- #address-cells: specifies the number of cells needed to encode an
28+
address. The value must be 0.
29+
- #interrupt-cells: specifies the number of cells needed to encode an
30+
interrupt source. The value must be 1.
31+
32+
NOTE:
33+
The core provides a single interrupt for both INTx/MSI messages. So,
34+
created a interrupt controller node to support 'interrupt-map' DT
35+
functionality. The driver will create an IRQ domain for this map, decode
36+
the four INTx interrupts in ISR and route them to this domain.
37+
38+
39+
Example:
40+
++++++++
41+
42+
pci_express: axi-pcie@50000000 {
43+
#address-cells = <3>;
44+
#size-cells = <2>;
45+
#interrupt-cells = <1>;
46+
compatible = "xlnx,axi-pcie-host-1.00.a";
47+
reg = < 0x50000000 0x10000000 >;
48+
device_type = "pci";
49+
interrupts = < 0 52 4 >;
50+
interrupt-map-mask = <0 0 0 7>;
51+
interrupt-map = <0 0 0 1 &pcie_intc 1>,
52+
<0 0 0 2 &pcie_intc 2>,
53+
<0 0 0 3 &pcie_intc 3>,
54+
<0 0 0 4 &pcie_intc 4>;
55+
ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;
56+
57+
pcie_intc: interrupt-controller {
58+
interrupt-controller;
59+
#address-cells = <0>;
60+
#interrupt-cells = <1>;
61+
}
62+
};

‎Documentation/driver-model/devres.txt

+2
Original file line numberDiff line numberDiff line change
@@ -264,8 +264,10 @@ IIO
264264
IO region
265265
devm_release_mem_region()
266266
devm_release_region()
267+
devm_release_resource()
267268
devm_request_mem_region()
268269
devm_request_region()
270+
devm_request_resource()
269271

270272
IOMAP
271273
devm_ioport_map()

‎MAINTAINERS

+15
Original file line numberDiff line numberDiff line change
@@ -6939,6 +6939,14 @@ F: include/linux/pci*
69396939
F: arch/x86/pci/
69406940
F: arch/x86/kernel/quirks.c
69416941

6942+
PCI DRIVER FOR APPLIEDMICRO XGENE
6943+
M: Tanmay Inamdar <[email protected]>
6944+
L: [email protected]
6945+
L: [email protected]
6946+
S: Maintained
6947+
F: Documentation/devicetree/bindings/pci/xgene-pci.txt
6948+
F: drivers/pci/host/pci-xgene.c
6949+
69426950
PCI DRIVER FOR IMX6
69436951
M: Richard Zhu <[email protected]>
69446952
M: Lucas Stach <[email protected]>
@@ -6947,6 +6955,13 @@ L: [email protected] (moderated for non-subscribers)
69476955
S: Maintained
69486956
F: drivers/pci/host/*imx6*
69496957

6958+
PCI DRIVER FOR TI KEYSTONE
6959+
M: Murali Karicheri <[email protected]>
6960+
L: [email protected]
6961+
L: [email protected] (moderated for non-subscribers)
6962+
S: Maintained
6963+
F: drivers/pci/host/*keystone*
6964+
69506965
PCI DRIVER FOR MVEBU (Marvell Armada 370 and Armada XP SOC support)
69516966
M: Thomas Petazzoni <[email protected]>
69526967
M: Jason Cooper <[email protected]>

‎arch/arm/boot/dts/spear1310.dtsi

+9-9
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,8 @@
8585

8686
pcie0: pcie@b1000000 {
8787
compatible = "st,spear1340-pcie", "snps,dw-pcie";
88-
reg = <0xb1000000 0x4000>;
88+
reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
89+
reg-names = "dbi", "config";
8990
interrupts = <0 68 0x4>;
9091
interrupt-map-mask = <0 0 0 0>;
9192
interrupt-map = <0x0 0 &gic 0 68 0x4>;
@@ -95,15 +96,15 @@
9596
#address-cells = <3>;
9697
#size-cells = <2>;
9798
device_type = "pci";
98-
ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
99-
0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
99+
ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
100100
0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
101101
status = "disabled";
102102
};
103103

104104
pcie1: pcie@b1800000 {
105105
compatible = "st,spear1340-pcie", "snps,dw-pcie";
106-
reg = <0xb1800000 0x4000>;
106+
reg = <0xb1800000 0x4000>, <0x90000000 0x20000>;
107+
reg-names = "dbi", "config";
107108
interrupts = <0 69 0x4>;
108109
interrupt-map-mask = <0 0 0 0>;
109110
interrupt-map = <0x0 0 &gic 0 69 0x4>;
@@ -113,15 +114,15 @@
113114
#address-cells = <3>;
114115
#size-cells = <2>;
115116
device_type = "pci";
116-
ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000 /* configuration space */
117-
0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
117+
ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
118118
0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
119119
status = "disabled";
120120
};
121121

122122
pcie2: pcie@b4000000 {
123123
compatible = "st,spear1340-pcie", "snps,dw-pcie";
124-
reg = <0xb4000000 0x4000>;
124+
reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>;
125+
reg-names = "dbi", "config";
125126
interrupts = <0 70 0x4>;
126127
interrupt-map-mask = <0 0 0 0>;
127128
interrupt-map = <0x0 0 &gic 0 70 0x4>;
@@ -131,8 +132,7 @@
131132
#address-cells = <3>;
132133
#size-cells = <2>;
133134
device_type = "pci";
134-
ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000 /* configuration space */
135-
0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
135+
ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
136136
0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
137137
status = "disabled";
138138
};

‎arch/arm/boot/dts/spear1340.dtsi

+3-3
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,8 @@
5050

5151
pcie0: pcie@b1000000 {
5252
compatible = "st,spear1340-pcie", "snps,dw-pcie";
53-
reg = <0xb1000000 0x4000>;
53+
reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
54+
reg-names = "dbi", "config";
5455
interrupts = <0 68 0x4>;
5556
interrupt-map-mask = <0 0 0 0>;
5657
interrupt-map = <0x0 0 &gic 0 68 0x4>;
@@ -60,8 +61,7 @@
6061
#address-cells = <3>;
6162
#size-cells = <2>;
6263
device_type = "pci";
63-
ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
64-
0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
64+
ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
6565
0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
6666
status = "disabled";
6767
};

‎arch/arm/include/asm/io.h

+1
Original file line numberDiff line numberDiff line change
@@ -178,6 +178,7 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
178178

179179
/* PCI fixed i/o mapping */
180180
#define PCI_IO_VIRT_BASE 0xfee00000
181+
#define PCI_IOBASE ((void __iomem *)PCI_IO_VIRT_BASE)
181182

182183
#if defined(CONFIG_PCI)
183184
void pci_ioremap_set_mem_type(int mem_type);

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