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Merge branch 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma
Pull dmaengine updates from Vinod Koul: "This update brings: - the big cleanup up by Maxime for device control and slave capabilities. This makes the API much cleaner. - new IMG MDC driver by Andrew - new Renesas R-Car Gen2 DMA Controller driver by Laurent along with bunch of fixes on rcar drivers - odd fixes and updates spread over driver" * 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (130 commits) dmaengine: pl330: add DMA_PAUSE feature dmaengine: pl330: improve pl330_tx_status() function dmaengine: rcar-dmac: Disable channel 0 when using IOMMU dmaengine: rcar-dmac: Work around descriptor mode IOMMU errata dmaengine: rcar-dmac: Allocate hardware descriptors with DMAC device dmaengine: rcar-dmac: Fix oops due to unintialized list in error ISR dmaengine: rcar-dmac: Fix spinlock issues in interrupt dmaenegine: edma: fix sparse warnings dmaengine: rcar-dmac: Fix uninitialized variable usage dmaengine: shdmac: extend PM methods dmaengine: shdmac: use SET_RUNTIME_PM_OPS() dmaengine: pl330: fix bug that cause start the same descs in cyclic dmaengine: at_xdmac: allow muliple dwidths when doing slave transfers dmaengine: at_xdmac: simplify channel configuration stuff dmaengine: at_xdmac: introduce save_cc field dmaengine: at_xdmac: wait for in-progress transaction to complete after pausing a channel ioat: fail self-test if wait_for_completion times out dmaengine: dw: define DW_DMA_MAX_NR_MASTERS dmaengine: dw: amend description of dma_dev field dmatest: move src_off, dst_off, len inside loop ...
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‎Documentation/devicetree/bindings/dma/img-mdc-dma.txt

+57
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,57 @@
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* IMG Multi-threaded DMA Controller (MDC)
2+
3+
Required properties:
4+
- compatible: Must be "img,pistachio-mdc-dma".
5+
- reg: Must contain the base address and length of the MDC registers.
6+
- interrupts: Must contain all the per-channel DMA interrupts.
7+
- clocks: Must contain an entry for each entry in clock-names.
8+
See ../clock/clock-bindings.txt for details.
9+
- clock-names: Must include the following entries:
10+
- sys: MDC system interface clock.
11+
- img,cr-periph: Must contain a phandle to the peripheral control syscon
12+
node which contains the DMA request to channel mapping registers.
13+
- img,max-burst-multiplier: Must be the maximum supported burst size multiplier.
14+
The maximum burst size is this value multiplied by the hardware-reported bus
15+
width.
16+
- #dma-cells: Must be 3:
17+
- The first cell is the peripheral's DMA request line.
18+
- The second cell is a bitmap specifying to which channels the DMA request
19+
line may be mapped (i.e. bit N set indicates channel N is usable).
20+
- The third cell is the thread ID to be used by the channel.
21+
22+
Optional properties:
23+
- dma-channels: Number of supported DMA channels, up to 32. If not specified
24+
the number reported by the hardware is used.
25+
26+
Example:
27+
28+
mdc: dma-controller@18143000 {
29+
compatible = "img,pistachio-mdc-dma";
30+
reg = <0x18143000 0x1000>;
31+
interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>,
32+
<GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 31 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 35 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>,
42+
<GIC_SHARED 38 IRQ_TYPE_LEVEL_HIGH>;
43+
clocks = <&system_clk>;
44+
clock-names = "sys";
45+
46+
img,max-burst-multiplier = <16>;
47+
img,cr-periph = <&cr_periph>;
48+
49+
#dma-cells = <3>;
50+
};
51+
52+
spi@18100f00 {
53+
...
54+
dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
55+
dma-names = "tx", "rx";
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...
57+
};

‎Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt

-3
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,6 @@ controller instances named DMAC capable of serving multiple clients. Channels
55
can be dedicated to specific clients or shared between a large number of
66
clients.
77

8-
DMA clients are connected to the DMAC ports referenced by an 8-bit identifier
9-
called MID/RID.
10-
118
Each DMA client is connected to one dedicated port of the DMAC, identified by
129
an 8-bit port number called the MID/RID. A DMA controller can thus serve up to
1310
256 clients in total. When the number of hardware channels is lower than the

‎Documentation/devicetree/bindings/dma/snps-dma.txt

+1-1
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ Example:
3838
chan_allocation_order = <1>;
3939
chan_priority = <1>;
4040
block_size = <0xfff>;
41-
data_width = <3 3 0 0>;
41+
data_width = <3 3>;
4242
};
4343

4444
DMA clients connected to the Designware DMA controller must use the format

‎Documentation/dmaengine/provider.txt

+55-42
Original file line numberDiff line numberDiff line change
@@ -113,6 +113,31 @@ need to initialize a few fields in there:
113113
* channels: should be initialized as a list using the
114114
INIT_LIST_HEAD macro for example
115115

116+
* src_addr_widths:
117+
- should contain a bitmask of the supported source transfer width
118+
119+
* dst_addr_widths:
120+
- should contain a bitmask of the supported destination transfer
121+
width
122+
123+
* directions:
124+
- should contain a bitmask of the supported slave directions
125+
(i.e. excluding mem2mem transfers)
126+
127+
* residue_granularity:
128+
- Granularity of the transfer residue reported to dma_set_residue.
129+
- This can be either:
130+
+ Descriptor
131+
-> Your device doesn't support any kind of residue
132+
reporting. The framework will only know that a particular
133+
transaction descriptor is done.
134+
+ Segment
135+
-> Your device is able to report which chunks have been
136+
transferred
137+
+ Burst
138+
-> Your device is able to report which burst have been
139+
transferred
140+
116141
* dev: should hold the pointer to the struct device associated
117142
to your current driver instance.
118143

@@ -274,48 +299,36 @@ supported.
274299
account the current period.
275300
- This function can be called in an interrupt context.
276301

277-
* device_control
278-
- Used by client drivers to control and configure the channel it
279-
has a handle on.
280-
- Called with a command and an argument
281-
+ The command is one of the values listed by the enum
282-
dma_ctrl_cmd. The valid commands are:
283-
+ DMA_PAUSE
284-
+ Pauses a transfer on the channel
285-
+ This command should operate synchronously on the channel,
286-
pausing right away the work of the given channel
287-
+ DMA_RESUME
288-
+ Restarts a transfer on the channel
289-
+ This command should operate synchronously on the channel,
290-
resuming right away the work of the given channel
291-
+ DMA_TERMINATE_ALL
292-
+ Aborts all the pending and ongoing transfers on the
293-
channel
294-
+ This command should operate synchronously on the channel,
295-
terminating right away all the channels
296-
+ DMA_SLAVE_CONFIG
297-
+ Reconfigures the channel with passed configuration
298-
+ This command should NOT perform synchronously, or on any
299-
currently queued transfers, but only on subsequent ones
300-
+ In this case, the function will receive a
301-
dma_slave_config structure pointer as an argument, that
302-
will detail which configuration to use.
303-
+ Even though that structure contains a direction field,
304-
this field is deprecated in favor of the direction
305-
argument given to the prep_* functions
306-
+ FSLDMA_EXTERNAL_START
307-
+ TODO: Why does that even exist?
308-
+ The argument is an opaque unsigned long. This actually is a
309-
pointer to a struct dma_slave_config that should be used only
310-
in the DMA_SLAVE_CONFIG.
311-
312-
* device_slave_caps
313-
- Called through the framework by client drivers in order to have
314-
an idea of what are the properties of the channel allocated to
315-
them.
316-
- Such properties are the buswidth, available directions, etc.
317-
- Required for every generic layer doing DMA transfers, such as
318-
ASoC.
302+
* device_config
303+
- Reconfigures the channel with the configuration given as
304+
argument
305+
- This command should NOT perform synchronously, or on any
306+
currently queued transfers, but only on subsequent ones
307+
- In this case, the function will receive a dma_slave_config
308+
structure pointer as an argument, that will detail which
309+
configuration to use.
310+
- Even though that structure contains a direction field, this
311+
field is deprecated in favor of the direction argument given to
312+
the prep_* functions
313+
- This call is mandatory for slave operations only. This should NOT be
314+
set or expected to be set for memcpy operations.
315+
If a driver support both, it should use this call for slave
316+
operations only and not for memcpy ones.
317+
318+
* device_pause
319+
- Pauses a transfer on the channel
320+
- This command should operate synchronously on the channel,
321+
pausing right away the work of the given channel
322+
323+
* device_resume
324+
- Resumes a transfer on the channel
325+
- This command should operate synchronously on the channel,
326+
pausing right away the work of the given channel
327+
328+
* device_terminate_all
329+
- Aborts all the pending and ongoing transfers on the channel
330+
- This command should operate synchronously on the channel,
331+
terminating right away all the channels
319332

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Misc notes (stuff that should be documented, but don't really know
321334
where to put them)

‎MAINTAINERS

+1
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@@ -8503,6 +8503,7 @@ SYNOPSYS DESIGNWARE DMAC DRIVER
85038503
M: Viresh Kumar <[email protected]>
85048504
M: Andy Shevchenko <[email protected]>
85058505
S: Maintained
8506+
F: include/linux/dma/dw.h
85068507
F: include/linux/platform_data/dma-dw.h
85078508
F: drivers/dma/dw/
85088509

‎arch/arc/boot/dts/abilis_tb10x.dtsi

+1-1
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@@ -112,7 +112,7 @@
112112
chan_allocation_order = <0>;
113113
chan_priority = <1>;
114114
block_size = <0x7ff>;
115-
data_width = <2 0 0 0>;
115+
data_width = <2>;
116116
clocks = <&ahb_clk>;
117117
clock-names = "hclk";
118118
};

‎arch/arm/boot/dts/spear13xx.dtsi

+2-2
Original file line numberDiff line numberDiff line change
@@ -117,7 +117,7 @@
117117
chan_priority = <1>;
118118
block_size = <0xfff>;
119119
dma-masters = <2>;
120-
data_width = <3 3 0 0>;
120+
data_width = <3 3>;
121121
};
122122

123123
dma@eb000000 {
@@ -133,7 +133,7 @@
133133
chan_allocation_order = <1>;
134134
chan_priority = <1>;
135135
block_size = <0xfff>;
136-
data_width = <3 3 0 0>;
136+
data_width = <3 3>;
137137
};
138138

139139
fsmc: flash@b0000000 {

‎arch/avr32/mach-at32ap/at32ap700x.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -607,7 +607,7 @@ static struct dw_dma_platform_data dw_dmac0_data = {
607607
.nr_channels = 3,
608608
.block_size = 4095U,
609609
.nr_masters = 2,
610-
.data_width = { 2, 2, 0, 0 },
610+
.data_width = { 2, 2 },
611611
};
612612

613613
static struct resource dw_dmac0_resource[] = {

‎drivers/crypto/ux500/cryp/cryp_core.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -606,12 +606,12 @@ static void cryp_dma_done(struct cryp_ctx *ctx)
606606
dev_dbg(ctx->device->dev, "[%s]: ", __func__);
607607

608608
chan = ctx->device->dma.chan_mem2cryp;
609-
dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
609+
dmaengine_terminate_all(chan);
610610
dma_unmap_sg(chan->device->dev, ctx->device->dma.sg_src,
611611
ctx->device->dma.sg_src_len, DMA_TO_DEVICE);
612612

613613
chan = ctx->device->dma.chan_cryp2mem;
614-
dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
614+
dmaengine_terminate_all(chan);
615615
dma_unmap_sg(chan->device->dev, ctx->device->dma.sg_dst,
616616
ctx->device->dma.sg_dst_len, DMA_FROM_DEVICE);
617617
}

‎drivers/crypto/ux500/hash/hash_core.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -202,7 +202,7 @@ static void hash_dma_done(struct hash_ctx *ctx)
202202
struct dma_chan *chan;
203203

204204
chan = ctx->device->dma.chan_mem2hash;
205-
dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
205+
dmaengine_terminate_all(chan);
206206
dma_unmap_sg(chan->device->dev, ctx->device->dma.sg,
207207
ctx->device->dma.sg_len, DMA_TO_DEVICE);
208208
}

‎drivers/dma/Kconfig

+9
Original file line numberDiff line numberDiff line change
@@ -416,6 +416,15 @@ config NBPFAXI_DMA
416416
help
417417
Support for "Type-AXI" NBPF DMA IPs from Renesas
418418

419+
config IMG_MDC_DMA
420+
tristate "IMG MDC support"
421+
depends on MIPS || COMPILE_TEST
422+
depends on MFD_SYSCON
423+
select DMA_ENGINE
424+
select DMA_VIRTUAL_CHANNELS
425+
help
426+
Enable support for the IMG multi-threaded DMA controller (MDC).
427+
419428
config DMA_ENGINE
420429
bool
421430

‎drivers/dma/Makefile

+2-1
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
1919
obj-$(CONFIG_AT_XDMAC) += at_xdmac.o
2020
obj-$(CONFIG_MX3_IPU) += ipu/
2121
obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
22-
obj-$(CONFIG_SH_DMAE_BASE) += sh/
22+
obj-$(CONFIG_RENESAS_DMA) += sh/
2323
obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
2424
obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/
2525
obj-$(CONFIG_IMX_SDMA) += imx-sdma.o
@@ -50,3 +50,4 @@ obj-y += xilinx/
5050
obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o
5151
obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o
5252
obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o
53+
obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o

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