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Starred repositories

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Verilog 39 12 Updated Jun 19, 2021

AXI4 and AXI4-Lite interface definitions

SystemVerilog 92 27 Updated Sep 20, 2020

Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor

SystemVerilog 48 40 Updated Jan 4, 2025

DDR2 memory controller written in Verilog

Verilog 73 32 Updated Feb 28, 2012

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip …

Verilog 623 118 Updated Nov 13, 2024

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversi…

Verilog 105 17 Updated Jan 29, 2024