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vcpu.c
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/*
* kvm_vcpu.c: handling all virtual cpu related thing.
* Copyright (c) 2005, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
* Place - Suite 330, Boston, MA 02111-1307 USA.
*
* Shaofan Li (Susue Li) <[email protected]>
* Yaozu Dong (Eddie Dong) ([email protected])
* Xuefei Xu (Anthony Xu) ([email protected])
* Xiantao Zhang <[email protected]>
*/
#include <linux/kvm_host.h>
#include <linux/types.h>
#include <asm/processor.h>
#include <asm/ia64regs.h>
#include <asm/gcc_intrin.h>
#include <asm/kregs.h>
#include <asm/pgtable.h>
#include <asm/tlb.h>
#include "asm-offsets.h"
#include "vcpu.h"
/*
* Special notes:
* - Index by it/dt/rt sequence
* - Only existing mode transitions are allowed in this table
* - RSE is placed at lazy mode when emulating guest partial mode
* - If gva happens to be rr0 and rr4, only allowed case is identity
* mapping (gva=gpa), or panic! (How?)
*/
int mm_switch_table[8][8] = {
/* 2004/09/12(Kevin): Allow switch to self */
/*
* (it,dt,rt): (0,0,0) -> (1,1,1)
* This kind of transition usually occurs in the very early
* stage of Linux boot up procedure. Another case is in efi
* and pal calls. (see "arch/ia64/kernel/head.S")
*
* (it,dt,rt): (0,0,0) -> (0,1,1)
* This kind of transition is found when OSYa exits efi boot
* service. Due to gva = gpa in this case (Same region),
* data access can be satisfied though itlb entry for physical
* emulation is hit.
*/
{SW_SELF, 0, 0, SW_NOP, 0, 0, 0, SW_P2V},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
/*
* (it,dt,rt): (0,1,1) -> (1,1,1)
* This kind of transition is found in OSYa.
*
* (it,dt,rt): (0,1,1) -> (0,0,0)
* This kind of transition is found in OSYa
*/
{SW_NOP, 0, 0, SW_SELF, 0, 0, 0, SW_P2V},
/* (1,0,0)->(1,1,1) */
{0, 0, 0, 0, 0, 0, 0, SW_P2V},
/*
* (it,dt,rt): (1,0,1) -> (1,1,1)
* This kind of transition usually occurs when Linux returns
* from the low level TLB miss handlers.
* (see "arch/ia64/kernel/ivt.S")
*/
{0, 0, 0, 0, 0, SW_SELF, 0, SW_P2V},
{0, 0, 0, 0, 0, 0, 0, 0},
/*
* (it,dt,rt): (1,1,1) -> (1,0,1)
* This kind of transition usually occurs in Linux low level
* TLB miss handler. (see "arch/ia64/kernel/ivt.S")
*
* (it,dt,rt): (1,1,1) -> (0,0,0)
* This kind of transition usually occurs in pal and efi calls,
* which requires running in physical mode.
* (see "arch/ia64/kernel/head.S")
* (1,1,1)->(1,0,0)
*/
{SW_V2P, 0, 0, 0, SW_V2P, SW_V2P, 0, SW_SELF},
};
void physical_mode_init(struct kvm_vcpu *vcpu)
{
vcpu->arch.mode_flags = GUEST_IN_PHY;
}
void switch_to_physical_rid(struct kvm_vcpu *vcpu)
{
unsigned long psr;
/* Save original virtual mode rr[0] and rr[4] */
psr = ia64_clear_ic();
ia64_set_rr(VRN0<<VRN_SHIFT, vcpu->arch.metaphysical_rr0);
ia64_srlz_d();
ia64_set_rr(VRN4<<VRN_SHIFT, vcpu->arch.metaphysical_rr4);
ia64_srlz_d();
ia64_set_psr(psr);
return;
}
void switch_to_virtual_rid(struct kvm_vcpu *vcpu)
{
unsigned long psr;
psr = ia64_clear_ic();
ia64_set_rr(VRN0 << VRN_SHIFT, vcpu->arch.metaphysical_saved_rr0);
ia64_srlz_d();
ia64_set_rr(VRN4 << VRN_SHIFT, vcpu->arch.metaphysical_saved_rr4);
ia64_srlz_d();
ia64_set_psr(psr);
return;
}
static int mm_switch_action(struct ia64_psr opsr, struct ia64_psr npsr)
{
return mm_switch_table[MODE_IND(opsr)][MODE_IND(npsr)];
}
void switch_mm_mode(struct kvm_vcpu *vcpu, struct ia64_psr old_psr,
struct ia64_psr new_psr)
{
int act;
act = mm_switch_action(old_psr, new_psr);
switch (act) {
case SW_V2P:
/*printk("V -> P mode transition: (0x%lx -> 0x%lx)\n",
old_psr.val, new_psr.val);*/
switch_to_physical_rid(vcpu);
/*
* Set rse to enforced lazy, to prevent active rse
*save/restor when guest physical mode.
*/
vcpu->arch.mode_flags |= GUEST_IN_PHY;
break;
case SW_P2V:
switch_to_virtual_rid(vcpu);
/*
* recover old mode which is saved when entering
* guest physical mode
*/
vcpu->arch.mode_flags &= ~GUEST_IN_PHY;
break;
case SW_SELF:
break;
case SW_NOP:
break;
default:
/* Sanity check */
break;
}
return;
}
/*
* In physical mode, insert tc/tr for region 0 and 4 uses
* RID[0] and RID[4] which is for physical mode emulation.
* However what those inserted tc/tr wants is rid for
* virtual mode. So original virtual rid needs to be restored
* before insert.
*
* Operations which required such switch include:
* - insertions (itc.*, itr.*)
* - purges (ptc.* and ptr.*)
* - tpa
* - tak
* - thash?, ttag?
* All above needs actual virtual rid for destination entry.
*/
void check_mm_mode_switch(struct kvm_vcpu *vcpu, struct ia64_psr old_psr,
struct ia64_psr new_psr)
{
if ((old_psr.dt != new_psr.dt)
|| (old_psr.it != new_psr.it)
|| (old_psr.rt != new_psr.rt))
switch_mm_mode(vcpu, old_psr, new_psr);
return;
}
/*
* In physical mode, insert tc/tr for region 0 and 4 uses
* RID[0] and RID[4] which is for physical mode emulation.
* However what those inserted tc/tr wants is rid for
* virtual mode. So original virtual rid needs to be restored
* before insert.
*
* Operations which required such switch include:
* - insertions (itc.*, itr.*)
* - purges (ptc.* and ptr.*)
* - tpa
* - tak
* - thash?, ttag?
* All above needs actual virtual rid for destination entry.
*/
void prepare_if_physical_mode(struct kvm_vcpu *vcpu)
{
if (is_physical_mode(vcpu)) {
vcpu->arch.mode_flags |= GUEST_PHY_EMUL;
switch_to_virtual_rid(vcpu);
}
return;
}
/* Recover always follows prepare */
void recover_if_physical_mode(struct kvm_vcpu *vcpu)
{
if (is_physical_mode(vcpu))
switch_to_physical_rid(vcpu);
vcpu->arch.mode_flags &= ~GUEST_PHY_EMUL;
return;
}
#define RPT(x) ((u16) &((struct kvm_pt_regs *)0)->x)
static u16 gr_info[32] = {
0, /* r0 is read-only : WE SHOULD NEVER GET THIS */
RPT(r1), RPT(r2), RPT(r3),
RPT(r4), RPT(r5), RPT(r6), RPT(r7),
RPT(r8), RPT(r9), RPT(r10), RPT(r11),
RPT(r12), RPT(r13), RPT(r14), RPT(r15),
RPT(r16), RPT(r17), RPT(r18), RPT(r19),
RPT(r20), RPT(r21), RPT(r22), RPT(r23),
RPT(r24), RPT(r25), RPT(r26), RPT(r27),
RPT(r28), RPT(r29), RPT(r30), RPT(r31)
};
#define IA64_FIRST_STACKED_GR 32
#define IA64_FIRST_ROTATING_FR 32
static inline unsigned long
rotate_reg(unsigned long sor, unsigned long rrb, unsigned long reg)
{
reg += rrb;
if (reg >= sor)
reg -= sor;
return reg;
}
/*
* Return the (rotated) index for floating point register
* be in the REGNUM (REGNUM must range from 32-127,
* result is in the range from 0-95.
*/
static inline unsigned long fph_index(struct kvm_pt_regs *regs,
long regnum)
{
unsigned long rrb_fr = (regs->cr_ifs >> 25) & 0x7f;
return rotate_reg(96, rrb_fr, (regnum - IA64_FIRST_ROTATING_FR));
}
/*
* The inverse of the above: given bspstore and the number of
* registers, calculate ar.bsp.
*/
static inline unsigned long *kvm_rse_skip_regs(unsigned long *addr,
long num_regs)
{
long delta = ia64_rse_slot_num(addr) + num_regs;
int i = 0;
if (num_regs < 0)
delta -= 0x3e;
if (delta < 0) {
while (delta <= -0x3f) {
i--;
delta += 0x3f;
}
} else {
while (delta >= 0x3f) {
i++;
delta -= 0x3f;
}
}
return addr + num_regs + i;
}
static void get_rse_reg(struct kvm_pt_regs *regs, unsigned long r1,
unsigned long *val, int *nat)
{
unsigned long *bsp, *addr, *rnat_addr, *bspstore;
unsigned long *kbs = (void *) current_vcpu + VMM_RBS_OFFSET;
unsigned long nat_mask;
unsigned long old_rsc, new_rsc;
long sof = (regs->cr_ifs) & 0x7f;
long sor = (((regs->cr_ifs >> 14) & 0xf) << 3);
long rrb_gr = (regs->cr_ifs >> 18) & 0x7f;
long ridx = r1 - 32;
if (ridx < sor)
ridx = rotate_reg(sor, rrb_gr, ridx);
old_rsc = ia64_getreg(_IA64_REG_AR_RSC);
new_rsc = old_rsc&(~(0x3));
ia64_setreg(_IA64_REG_AR_RSC, new_rsc);
bspstore = (unsigned long *)ia64_getreg(_IA64_REG_AR_BSPSTORE);
bsp = kbs + (regs->loadrs >> 19);
addr = kvm_rse_skip_regs(bsp, -sof + ridx);
nat_mask = 1UL << ia64_rse_slot_num(addr);
rnat_addr = ia64_rse_rnat_addr(addr);
if (addr >= bspstore) {
ia64_flushrs();
ia64_mf();
bspstore = (unsigned long *)ia64_getreg(_IA64_REG_AR_BSPSTORE);
}
*val = *addr;
if (nat) {
if (bspstore < rnat_addr)
*nat = (int)!!(ia64_getreg(_IA64_REG_AR_RNAT)
& nat_mask);
else
*nat = (int)!!((*rnat_addr) & nat_mask);
ia64_setreg(_IA64_REG_AR_RSC, old_rsc);
}
}
void set_rse_reg(struct kvm_pt_regs *regs, unsigned long r1,
unsigned long val, unsigned long nat)
{
unsigned long *bsp, *bspstore, *addr, *rnat_addr;
unsigned long *kbs = (void *) current_vcpu + VMM_RBS_OFFSET;
unsigned long nat_mask;
unsigned long old_rsc, new_rsc, psr;
unsigned long rnat;
long sof = (regs->cr_ifs) & 0x7f;
long sor = (((regs->cr_ifs >> 14) & 0xf) << 3);
long rrb_gr = (regs->cr_ifs >> 18) & 0x7f;
long ridx = r1 - 32;
if (ridx < sor)
ridx = rotate_reg(sor, rrb_gr, ridx);
old_rsc = ia64_getreg(_IA64_REG_AR_RSC);
/* put RSC to lazy mode, and set loadrs 0 */
new_rsc = old_rsc & (~0x3fff0003);
ia64_setreg(_IA64_REG_AR_RSC, new_rsc);
bsp = kbs + (regs->loadrs >> 19); /* 16 + 3 */
addr = kvm_rse_skip_regs(bsp, -sof + ridx);
nat_mask = 1UL << ia64_rse_slot_num(addr);
rnat_addr = ia64_rse_rnat_addr(addr);
local_irq_save(psr);
bspstore = (unsigned long *)ia64_getreg(_IA64_REG_AR_BSPSTORE);
if (addr >= bspstore) {
ia64_flushrs();
ia64_mf();
*addr = val;
bspstore = (unsigned long *)ia64_getreg(_IA64_REG_AR_BSPSTORE);
rnat = ia64_getreg(_IA64_REG_AR_RNAT);
if (bspstore < rnat_addr)
rnat = rnat & (~nat_mask);
else
*rnat_addr = (*rnat_addr)&(~nat_mask);
ia64_mf();
ia64_loadrs();
ia64_setreg(_IA64_REG_AR_RNAT, rnat);
} else {
rnat = ia64_getreg(_IA64_REG_AR_RNAT);
*addr = val;
if (bspstore < rnat_addr)
rnat = rnat&(~nat_mask);
else
*rnat_addr = (*rnat_addr) & (~nat_mask);
ia64_setreg(_IA64_REG_AR_BSPSTORE, (unsigned long)bspstore);
ia64_setreg(_IA64_REG_AR_RNAT, rnat);
}
local_irq_restore(psr);
ia64_setreg(_IA64_REG_AR_RSC, old_rsc);
}
void getreg(unsigned long regnum, unsigned long *val,
int *nat, struct kvm_pt_regs *regs)
{
unsigned long addr, *unat;
if (regnum >= IA64_FIRST_STACKED_GR) {
get_rse_reg(regs, regnum, val, nat);
return;
}
/*
* Now look at registers in [0-31] range and init correct UNAT
*/
addr = (unsigned long)regs;
unat = ®s->eml_unat;
addr += gr_info[regnum];
*val = *(unsigned long *)addr;
/*
* do it only when requested
*/
if (nat)
*nat = (*unat >> ((addr >> 3) & 0x3f)) & 0x1UL;
}
void setreg(unsigned long regnum, unsigned long val,
int nat, struct kvm_pt_regs *regs)
{
unsigned long addr;
unsigned long bitmask;
unsigned long *unat;
/*
* First takes care of stacked registers
*/
if (regnum >= IA64_FIRST_STACKED_GR) {
set_rse_reg(regs, regnum, val, nat);
return;
}
/*
* Now look at registers in [0-31] range and init correct UNAT
*/
addr = (unsigned long)regs;
unat = ®s->eml_unat;
/*
* add offset from base of struct
* and do it !
*/
addr += gr_info[regnum];
*(unsigned long *)addr = val;
/*
* We need to clear the corresponding UNAT bit to fully emulate the load
* UNAT bit_pos = GR[r3]{8:3} form EAS-2.4
*/
bitmask = 1UL << ((addr >> 3) & 0x3f);
if (nat)
*unat |= bitmask;
else
*unat &= ~bitmask;
}
u64 vcpu_get_gr(struct kvm_vcpu *vcpu, unsigned long reg)
{
struct kvm_pt_regs *regs = vcpu_regs(vcpu);
unsigned long val;
if (!reg)
return 0;
getreg(reg, &val, 0, regs);
return val;
}
void vcpu_set_gr(struct kvm_vcpu *vcpu, unsigned long reg, u64 value, int nat)
{
struct kvm_pt_regs *regs = vcpu_regs(vcpu);
long sof = (regs->cr_ifs) & 0x7f;
if (!reg)
return;
if (reg >= sof + 32)
return;
setreg(reg, value, nat, regs); /* FIXME: handle NATs later*/
}
void getfpreg(unsigned long regnum, struct ia64_fpreg *fpval,
struct kvm_pt_regs *regs)
{
/* Take floating register rotation into consideration*/
if (regnum >= IA64_FIRST_ROTATING_FR)
regnum = IA64_FIRST_ROTATING_FR + fph_index(regs, regnum);
#define CASE_FIXED_FP(reg) \
case (reg) : \
ia64_stf_spill(fpval, reg); \
break
switch (regnum) {
CASE_FIXED_FP(0);
CASE_FIXED_FP(1);
CASE_FIXED_FP(2);
CASE_FIXED_FP(3);
CASE_FIXED_FP(4);
CASE_FIXED_FP(5);
CASE_FIXED_FP(6);
CASE_FIXED_FP(7);
CASE_FIXED_FP(8);
CASE_FIXED_FP(9);
CASE_FIXED_FP(10);
CASE_FIXED_FP(11);
CASE_FIXED_FP(12);
CASE_FIXED_FP(13);
CASE_FIXED_FP(14);
CASE_FIXED_FP(15);
CASE_FIXED_FP(16);
CASE_FIXED_FP(17);
CASE_FIXED_FP(18);
CASE_FIXED_FP(19);
CASE_FIXED_FP(20);
CASE_FIXED_FP(21);
CASE_FIXED_FP(22);
CASE_FIXED_FP(23);
CASE_FIXED_FP(24);
CASE_FIXED_FP(25);
CASE_FIXED_FP(26);
CASE_FIXED_FP(27);
CASE_FIXED_FP(28);
CASE_FIXED_FP(29);
CASE_FIXED_FP(30);
CASE_FIXED_FP(31);
CASE_FIXED_FP(32);
CASE_FIXED_FP(33);
CASE_FIXED_FP(34);
CASE_FIXED_FP(35);
CASE_FIXED_FP(36);
CASE_FIXED_FP(37);
CASE_FIXED_FP(38);
CASE_FIXED_FP(39);
CASE_FIXED_FP(40);
CASE_FIXED_FP(41);
CASE_FIXED_FP(42);
CASE_FIXED_FP(43);
CASE_FIXED_FP(44);
CASE_FIXED_FP(45);
CASE_FIXED_FP(46);
CASE_FIXED_FP(47);
CASE_FIXED_FP(48);
CASE_FIXED_FP(49);
CASE_FIXED_FP(50);
CASE_FIXED_FP(51);
CASE_FIXED_FP(52);
CASE_FIXED_FP(53);
CASE_FIXED_FP(54);
CASE_FIXED_FP(55);
CASE_FIXED_FP(56);
CASE_FIXED_FP(57);
CASE_FIXED_FP(58);
CASE_FIXED_FP(59);
CASE_FIXED_FP(60);
CASE_FIXED_FP(61);
CASE_FIXED_FP(62);
CASE_FIXED_FP(63);
CASE_FIXED_FP(64);
CASE_FIXED_FP(65);
CASE_FIXED_FP(66);
CASE_FIXED_FP(67);
CASE_FIXED_FP(68);
CASE_FIXED_FP(69);
CASE_FIXED_FP(70);
CASE_FIXED_FP(71);
CASE_FIXED_FP(72);
CASE_FIXED_FP(73);
CASE_FIXED_FP(74);
CASE_FIXED_FP(75);
CASE_FIXED_FP(76);
CASE_FIXED_FP(77);
CASE_FIXED_FP(78);
CASE_FIXED_FP(79);
CASE_FIXED_FP(80);
CASE_FIXED_FP(81);
CASE_FIXED_FP(82);
CASE_FIXED_FP(83);
CASE_FIXED_FP(84);
CASE_FIXED_FP(85);
CASE_FIXED_FP(86);
CASE_FIXED_FP(87);
CASE_FIXED_FP(88);
CASE_FIXED_FP(89);
CASE_FIXED_FP(90);
CASE_FIXED_FP(91);
CASE_FIXED_FP(92);
CASE_FIXED_FP(93);
CASE_FIXED_FP(94);
CASE_FIXED_FP(95);
CASE_FIXED_FP(96);
CASE_FIXED_FP(97);
CASE_FIXED_FP(98);
CASE_FIXED_FP(99);
CASE_FIXED_FP(100);
CASE_FIXED_FP(101);
CASE_FIXED_FP(102);
CASE_FIXED_FP(103);
CASE_FIXED_FP(104);
CASE_FIXED_FP(105);
CASE_FIXED_FP(106);
CASE_FIXED_FP(107);
CASE_FIXED_FP(108);
CASE_FIXED_FP(109);
CASE_FIXED_FP(110);
CASE_FIXED_FP(111);
CASE_FIXED_FP(112);
CASE_FIXED_FP(113);
CASE_FIXED_FP(114);
CASE_FIXED_FP(115);
CASE_FIXED_FP(116);
CASE_FIXED_FP(117);
CASE_FIXED_FP(118);
CASE_FIXED_FP(119);
CASE_FIXED_FP(120);
CASE_FIXED_FP(121);
CASE_FIXED_FP(122);
CASE_FIXED_FP(123);
CASE_FIXED_FP(124);
CASE_FIXED_FP(125);
CASE_FIXED_FP(126);
CASE_FIXED_FP(127);
}
#undef CASE_FIXED_FP
}
void setfpreg(unsigned long regnum, struct ia64_fpreg *fpval,
struct kvm_pt_regs *regs)
{
/* Take floating register rotation into consideration*/
if (regnum >= IA64_FIRST_ROTATING_FR)
regnum = IA64_FIRST_ROTATING_FR + fph_index(regs, regnum);
#define CASE_FIXED_FP(reg) \
case (reg) : \
ia64_ldf_fill(reg, fpval); \
break
switch (regnum) {
CASE_FIXED_FP(2);
CASE_FIXED_FP(3);
CASE_FIXED_FP(4);
CASE_FIXED_FP(5);
CASE_FIXED_FP(6);
CASE_FIXED_FP(7);
CASE_FIXED_FP(8);
CASE_FIXED_FP(9);
CASE_FIXED_FP(10);
CASE_FIXED_FP(11);
CASE_FIXED_FP(12);
CASE_FIXED_FP(13);
CASE_FIXED_FP(14);
CASE_FIXED_FP(15);
CASE_FIXED_FP(16);
CASE_FIXED_FP(17);
CASE_FIXED_FP(18);
CASE_FIXED_FP(19);
CASE_FIXED_FP(20);
CASE_FIXED_FP(21);
CASE_FIXED_FP(22);
CASE_FIXED_FP(23);
CASE_FIXED_FP(24);
CASE_FIXED_FP(25);
CASE_FIXED_FP(26);
CASE_FIXED_FP(27);
CASE_FIXED_FP(28);
CASE_FIXED_FP(29);
CASE_FIXED_FP(30);
CASE_FIXED_FP(31);
CASE_FIXED_FP(32);
CASE_FIXED_FP(33);
CASE_FIXED_FP(34);
CASE_FIXED_FP(35);
CASE_FIXED_FP(36);
CASE_FIXED_FP(37);
CASE_FIXED_FP(38);
CASE_FIXED_FP(39);
CASE_FIXED_FP(40);
CASE_FIXED_FP(41);
CASE_FIXED_FP(42);
CASE_FIXED_FP(43);
CASE_FIXED_FP(44);
CASE_FIXED_FP(45);
CASE_FIXED_FP(46);
CASE_FIXED_FP(47);
CASE_FIXED_FP(48);
CASE_FIXED_FP(49);
CASE_FIXED_FP(50);
CASE_FIXED_FP(51);
CASE_FIXED_FP(52);
CASE_FIXED_FP(53);
CASE_FIXED_FP(54);
CASE_FIXED_FP(55);
CASE_FIXED_FP(56);
CASE_FIXED_FP(57);
CASE_FIXED_FP(58);
CASE_FIXED_FP(59);
CASE_FIXED_FP(60);
CASE_FIXED_FP(61);
CASE_FIXED_FP(62);
CASE_FIXED_FP(63);
CASE_FIXED_FP(64);
CASE_FIXED_FP(65);
CASE_FIXED_FP(66);
CASE_FIXED_FP(67);
CASE_FIXED_FP(68);
CASE_FIXED_FP(69);
CASE_FIXED_FP(70);
CASE_FIXED_FP(71);
CASE_FIXED_FP(72);
CASE_FIXED_FP(73);
CASE_FIXED_FP(74);
CASE_FIXED_FP(75);
CASE_FIXED_FP(76);
CASE_FIXED_FP(77);
CASE_FIXED_FP(78);
CASE_FIXED_FP(79);
CASE_FIXED_FP(80);
CASE_FIXED_FP(81);
CASE_FIXED_FP(82);
CASE_FIXED_FP(83);
CASE_FIXED_FP(84);
CASE_FIXED_FP(85);
CASE_FIXED_FP(86);
CASE_FIXED_FP(87);
CASE_FIXED_FP(88);
CASE_FIXED_FP(89);
CASE_FIXED_FP(90);
CASE_FIXED_FP(91);
CASE_FIXED_FP(92);
CASE_FIXED_FP(93);
CASE_FIXED_FP(94);
CASE_FIXED_FP(95);
CASE_FIXED_FP(96);
CASE_FIXED_FP(97);
CASE_FIXED_FP(98);
CASE_FIXED_FP(99);
CASE_FIXED_FP(100);
CASE_FIXED_FP(101);
CASE_FIXED_FP(102);
CASE_FIXED_FP(103);
CASE_FIXED_FP(104);
CASE_FIXED_FP(105);
CASE_FIXED_FP(106);
CASE_FIXED_FP(107);
CASE_FIXED_FP(108);
CASE_FIXED_FP(109);
CASE_FIXED_FP(110);
CASE_FIXED_FP(111);
CASE_FIXED_FP(112);
CASE_FIXED_FP(113);
CASE_FIXED_FP(114);
CASE_FIXED_FP(115);
CASE_FIXED_FP(116);
CASE_FIXED_FP(117);
CASE_FIXED_FP(118);
CASE_FIXED_FP(119);
CASE_FIXED_FP(120);
CASE_FIXED_FP(121);
CASE_FIXED_FP(122);
CASE_FIXED_FP(123);
CASE_FIXED_FP(124);
CASE_FIXED_FP(125);
CASE_FIXED_FP(126);
CASE_FIXED_FP(127);
}
}
void vcpu_get_fpreg(struct kvm_vcpu *vcpu, unsigned long reg,
struct ia64_fpreg *val)
{
struct kvm_pt_regs *regs = vcpu_regs(vcpu);
getfpreg(reg, val, regs); /* FIXME: handle NATs later*/
}
void vcpu_set_fpreg(struct kvm_vcpu *vcpu, unsigned long reg,
struct ia64_fpreg *val)
{
struct kvm_pt_regs *regs = vcpu_regs(vcpu);
if (reg > 1)
setfpreg(reg, val, regs); /* FIXME: handle NATs later*/
}
/*
* The Altix RTC is mapped specially here for the vmm module
*/
#define SN_RTC_BASE (u64 *)(KVM_VMM_BASE+(1UL<<KVM_VMM_SHIFT))
static long kvm_get_itc(struct kvm_vcpu *vcpu)
{
#if defined(CONFIG_IA64_SGI_SN2) || defined(CONFIG_IA64_GENERIC)
struct kvm *kvm = (struct kvm *)KVM_VM_BASE;
if (kvm->arch.is_sn2)
return (*SN_RTC_BASE);
else
#endif
return ia64_getreg(_IA64_REG_AR_ITC);
}
/************************************************************************
* lsapic timer
***********************************************************************/
u64 vcpu_get_itc(struct kvm_vcpu *vcpu)
{
unsigned long guest_itc;
guest_itc = VMX(vcpu, itc_offset) + kvm_get_itc(vcpu);
if (guest_itc >= VMX(vcpu, last_itc)) {
VMX(vcpu, last_itc) = guest_itc;
return guest_itc;
} else
return VMX(vcpu, last_itc);
}
static inline void vcpu_set_itm(struct kvm_vcpu *vcpu, u64 val);
static void vcpu_set_itc(struct kvm_vcpu *vcpu, u64 val)
{
struct kvm_vcpu *v;
struct kvm *kvm;
int i;
long itc_offset = val - kvm_get_itc(vcpu);
unsigned long vitv = VCPU(vcpu, itv);
kvm = (struct kvm *)KVM_VM_BASE;
if (kvm_vcpu_is_bsp(vcpu)) {
for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) {
v = (struct kvm_vcpu *)((char *)vcpu +
sizeof(struct kvm_vcpu_data) * i);
VMX(v, itc_offset) = itc_offset;
VMX(v, last_itc) = 0;
}
}
VMX(vcpu, last_itc) = 0;
if (VCPU(vcpu, itm) <= val) {
VMX(vcpu, itc_check) = 0;
vcpu_unpend_interrupt(vcpu, vitv);
} else {
VMX(vcpu, itc_check) = 1;
vcpu_set_itm(vcpu, VCPU(vcpu, itm));
}
}
static inline u64 vcpu_get_itm(struct kvm_vcpu *vcpu)
{
return ((u64)VCPU(vcpu, itm));
}
static inline void vcpu_set_itm(struct kvm_vcpu *vcpu, u64 val)
{
unsigned long vitv = VCPU(vcpu, itv);
VCPU(vcpu, itm) = val;
if (val > vcpu_get_itc(vcpu)) {
VMX(vcpu, itc_check) = 1;
vcpu_unpend_interrupt(vcpu, vitv);
VMX(vcpu, timer_pending) = 0;
} else
VMX(vcpu, itc_check) = 0;
}
#define ITV_VECTOR(itv) (itv&0xff)
#define ITV_IRQ_MASK(itv) (itv&(1<<16))
static inline void vcpu_set_itv(struct kvm_vcpu *vcpu, u64 val)
{
VCPU(vcpu, itv) = val;
if (!ITV_IRQ_MASK(val) && vcpu->arch.timer_pending) {
vcpu_pend_interrupt(vcpu, ITV_VECTOR(val));
vcpu->arch.timer_pending = 0;
}
}
static inline void vcpu_set_eoi(struct kvm_vcpu *vcpu, u64 val)
{
int vec;
vec = highest_inservice_irq(vcpu);
if (vec == NULL_VECTOR)
return;
VMX(vcpu, insvc[vec >> 6]) &= ~(1UL << (vec & 63));
VCPU(vcpu, eoi) = 0;
vcpu->arch.irq_new_pending = 1;
}
/* See Table 5-8 in SDM vol2 for the definition */
int irq_masked(struct kvm_vcpu *vcpu, int h_pending, int h_inservice)
{
union ia64_tpr vtpr;
vtpr.val = VCPU(vcpu, tpr);
if (h_inservice == NMI_VECTOR)
return IRQ_MASKED_BY_INSVC;
if (h_pending == NMI_VECTOR) {
/* Non Maskable Interrupt */
return IRQ_NO_MASKED;
}
if (h_inservice == ExtINT_VECTOR)
return IRQ_MASKED_BY_INSVC;
if (h_pending == ExtINT_VECTOR) {
if (vtpr.mmi) {
/* mask all external IRQ */
return IRQ_MASKED_BY_VTPR;
} else
return IRQ_NO_MASKED;
}
if (is_higher_irq(h_pending, h_inservice)) {
if (is_higher_class(h_pending, vtpr.mic + (vtpr.mmi << 4)))
return IRQ_NO_MASKED;
else
return IRQ_MASKED_BY_VTPR;
} else {
return IRQ_MASKED_BY_INSVC;
}
}
void vcpu_pend_interrupt(struct kvm_vcpu *vcpu, u8 vec)
{
long spsr;
int ret;
local_irq_save(spsr);
ret = test_and_set_bit(vec, &VCPU(vcpu, irr[0]));
local_irq_restore(spsr);
vcpu->arch.irq_new_pending = 1;
}
void vcpu_unpend_interrupt(struct kvm_vcpu *vcpu, u8 vec)
{
long spsr;
int ret;
local_irq_save(spsr);
ret = test_and_clear_bit(vec, &VCPU(vcpu, irr[0]));
local_irq_restore(spsr);
if (ret) {
vcpu->arch.irq_new_pending = 1;
wmb();
}
}
void update_vhpi(struct kvm_vcpu *vcpu, int vec)
{
u64 vhpi;
if (vec == NULL_VECTOR)
vhpi = 0;
else if (vec == NMI_VECTOR)
vhpi = 32;
else if (vec == ExtINT_VECTOR)
vhpi = 16;
else
vhpi = vec >> 4;
VCPU(vcpu, vhpi) = vhpi;
if (VCPU(vcpu, vac).a_int)
ia64_call_vsa(PAL_VPS_SET_PENDING_INTERRUPT,
(u64)vcpu->arch.vpd, 0, 0, 0, 0, 0, 0);
}
u64 vcpu_get_ivr(struct kvm_vcpu *vcpu)
{
int vec, h_inservice, mask;
vec = highest_pending_irq(vcpu);
h_inservice = highest_inservice_irq(vcpu);
mask = irq_masked(vcpu, vec, h_inservice);
if (vec == NULL_VECTOR || mask == IRQ_MASKED_BY_INSVC) {
if (VCPU(vcpu, vhpi))
update_vhpi(vcpu, NULL_VECTOR);
return IA64_SPURIOUS_INT_VECTOR;
}
if (mask == IRQ_MASKED_BY_VTPR) {
update_vhpi(vcpu, vec);
return IA64_SPURIOUS_INT_VECTOR;
}
VMX(vcpu, insvc[vec >> 6]) |= (1UL << (vec & 63));
vcpu_unpend_interrupt(vcpu, vec);
return (u64)vec;
}
/**************************************************************************
Privileged operation emulation routines
**************************************************************************/
u64 vcpu_thash(struct kvm_vcpu *vcpu, u64 vadr)