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Can't compile FPGA for tn_vdp_v2_v9918 with latest version GoWin V1.9.9.03 Education (64-Bit) build (73833) #22

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wiesl opened this issue Jul 5, 2024 · 1 comment
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Can't compile FPGA for tn_vdp_v2_v9918 with latest version GoWin V1.9.9.03 Education (64-Bit) build (73833) #22

wiesl opened this issue Jul 5, 2024 · 1 comment

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@wiesl
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wiesl commented Jul 5, 2024 •
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Hello,

I'm getting the following error:
Parsing netlist file "C:\Users\username\Desktop\tn_vdp\fpga\tn_vdp_v2_v9918\impl\gwsynthesis\tn_vdp.vg" completed
ERROR (PA2122) : Not support 'mem_r_mem_r_0_0_s'(DPB) WRITE_MODE0 = 2'b10, please change write mode WRITE_MODE0 = 2'b00 or 2'b01.
ERROR (PA2122) : Not support 'mem_r_mem_r_0_1_s'(DPB) WRITE_MODE0 = 2'b10, please change write mode WRITE_MODE0 = 2'b00 or 2'b01.
ERROR (PA2122) : Not support 'mem_r_mem_r_0_2_s'(DPB) WRITE_MODE0 = 2'b10, please change write mode WRITE_MODE0 = 2'b00 or 2'b01.
ERROR (PA2122) : Not support 'mem_r_mem_r_0_3_s'(DPB) WRITE_MODE0 = 2'b10, please change write mode WRITE_MODE0 = 2'b00 or 2'b01.
ERROR (PA2122) : Not support 'mem_r_mem_r_0_4_s'(DPB) WRITE_MODE0 = 2'b10, please change write mode WRITE_MODE0 = 2'b00 or 2'b01.
ERROR (PA2122) : Not support 'mem_r_mem_r_0_5_s'(DPB) WRITE_MODE0 = 2'b10, please change write mode WRITE_MODE0 = 2'b00 or 2'b01.
ERROR (PA2122) : Not support 'mem_r_mem_r_0_6_s'(DPB) WRITE_MODE0 = 2'b10, please change write mode WRITE_MODE0 = 2'b00 or 2'b01.
ERROR (PA2122) : Not support 'mem_r_mem_r_0_7_s'(DPB) WRITE_MODE0 = 2'b10, please change write mode WRITE_MODE0 = 2'b00 or 2'b01.
ERROR (PA2122) : Not support 'linebuf1_linebuf1_0_0_s'(DPX9B) WRITE_MODE0 = 2'b10, please change write mode WRITE_MODE0 = 2'b00 or 2'b01.
ERROR (PA2122) : Not support 'linebuf2_linebuf2_0_0_s'(DPX9B) WRITE_MODE0 = 2'b10, please change write mode WRITE_MODE0 = 2'b00 or 2'b01.
ERROR (PA2122) : Not support 'colram_colram_0_0_s'(DPB) WRITE_MODE1 = 2'b10, please change write mode WRITE_MODE1 = 2'b00 or 2'b01.
NOTE (PA0005) : Processing netlist completed with errors

Looks like this is a problem, with a read before write of the dual ported RAM part in newer versions of GoWin. That has been removed according to the release notes. Any way to fix it?

Do you have an older version of GoWin to download?

Didn't try other versions but guess same problem with 9k version.

Some research I already made after using search engines:
Picotiny example fails during Place & Route #19
sipeed/TangNano-9K-example#19
Found it: Tools -> IP Core Generator -> Hard Module -> Memory -> Block Memory -> DPB

MiSTery on Tang Nano
https://www.atari-forum.com/viewtopic.php?t=43080&start=200
The manifestation of this seems to have changed over the various GoWin versions. The current MiSTeryNano synthesizes successful with the latest GoWin 1.9.9 (no beta).
Form Gowin BSRAM & SSRAM User Guide
https://cdn.gowinsemi.com.cn/UG285E.pdf
Read before write in dual port mode was removed.

Bug in Gowin while using Tang Nano 9k?
https://www.reddit.com/r/GowinFPGA/comments/1d1t2to/bug_in_gowin_while_using_tang_nano_9k/
In manual "Gowin BSRAM & SSRAM User Guide" page 6:
GW1N-9/GW1N-1S/GW1NR-9/GW1NS-4 series does not support dual port mode.
but Gowin EDA synthesizes and does place and routes DPB (dual port block ram) + it is available as an IP (without the "byte addressable" in UI but generated in Verilog)
p.s. I solved my problem by using a combination of BSRAM pROM and SP instead of dual port RAM. Not a resourceful use of block RAM but meets the specs and I couldn't use 100% of it anyway.
That the blocking assignment "fixes" the issue makes sense since the device does not support "Read-Before-Write". Making a blocking assignment points out that write is before read so it does make sense.

Still an issue that Gowin IDE generates a netlist that is not supported. Better would be a message at synthesize and indication of how to fix it.

Picotiny example fails during Place & Route #19
sipeed/TangNano-9K-example#19
sipeed/TangNano-9K-example@c3b7957

https://cdn.gowinsemi.com.cn/SUG550E.pdf chapter 4.2 is what you want to work from.
Changing from asynchronous assign to synchronous solves the problem.

Thnx.

Ciao

This fixes it but I guess it doesn't work anymore:

diff --git a/fpga/tn_vdp_v2_v9918/src/ram16k.v b/fpga/tn_vdp_v2_v9918/src/ram16k.v
index d5aae63..b9b9aa8 100644
--- a/fpga/tn_vdp_v2_v9918/src/ram16k.v
+++ b/fpga/tn_vdp_v2_v9918/src/ram16k.v
@@ -18,8 +18,8 @@ end
 
     always @(posedge clk) begin
     
-        dout_r <= mem_r[addr];
-        dout2_r <= mem_r[addr2];
+        //dout_r = mem_r[addr];
+        //dout2_r = mem_r[addr2];
         if (we == 1) begin
             mem_r[addr] <= din;
         end

diff --git a/fpga/tn_vdp_v2_v9918/src/f18a/f18a_color.vhd b/fpga/tn_vdp_v2_v9918/src/f18a/f18a_color.vhd
index ccf3789..f3fe08c 100644
--- a/fpga/tn_vdp_v2_v9918/src/f18a/f18a_color.vhd
+++ b/fpga/tn_vdp_v2_v9918/src/f18a/f18a_color.vhd
@@ -167,7 +167,7 @@ begin
    begin
       if rising_edge(clk) then
          if we1 = '1' then
-            colram(to_integer(unsigned(addr1))) <= din;
+            -- colram(to_integer(unsigned(addr1))) <= din;
          end if;
 
          -- to the GPU! :-)

diff --git a/fpga/tn_vdp_v2_v9918/src/f18a/f18a_sprites.vhd b/fpga/tn_vdp_v2_v9918/src/f18a/f18a_sprites.vhd
index 275a2af..42d196e 100644
--- a/fpga/tn_vdp_v2_v9918/src/f18a/f18a_sprites.vhd
+++ b/fpga/tn_vdp_v2_v9918/src/f18a/f18a_sprites.vhd
@@ -214,8 +214,8 @@ begin
    process (clk)
    begin
       if rising_edge(clk) then
-         dout1a <= linebuf1(to_integer(unsigned(addr1a)));
-         dout1b <= linebuf1(to_integer(unsigned(addr1b)));
+         --dout1a <= linebuf1(to_integer(unsigned(addr1a)));
+         --dout1b <= linebuf1(to_integer(unsigned(addr1b)));
          if we1 = '1' then
             linebuf1(to_integer(unsigned(addr1a))) <= din;
          end if;
@@ -227,8 +227,8 @@ begin
    process (clk)
    begin
       if rising_edge(clk) then
-         dout2a <= linebuf2(to_integer(unsigned(addr2a)));
-         dout2b <= linebuf2(to_integer(unsigned(addr2b)));
+         --dout2a <= linebuf2(to_integer(unsigned(addr2a)));
+         --dout2b <= linebuf2(to_integer(unsigned(addr2b)));
          if we2 = '1' then
             linebuf2(to_integer(unsigned(addr2a))) <= din;
          end if;
@lfantoniosi
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lfantoniosi commented Jul 5, 2024 via email

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