From 153fa865c6eabe3c73a44672a77f63be21253eeb Mon Sep 17 00:00:00 2001 From: Dylan McKay Date: Fri, 9 Dec 2016 07:49:04 +0000 Subject: [PATCH] [AVR] Add tests for a large number of pseudo instructions This adds MIR tests for 24 pseudo instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289191 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AVR/AVRExpandPseudoInsts.cpp | 12 ++++++++++++ test/CodeGen/AVR/progmem-extended.ll | 3 +++ test/CodeGen/AVR/pseudo/ASRWRd.mir | 22 ++++++++++++++++++++++ test/CodeGen/AVR/pseudo/CPCWRdRr.mir | 6 ++++-- test/CodeGen/AVR/pseudo/CPWRdRr.mir | 6 ++++-- test/CodeGen/AVR/pseudo/FRMIDX.mir | 25 +++++++++++++++++++++++++ test/CodeGen/AVR/pseudo/INWRdA.mir | 22 ++++++++++++++++++++++ test/CodeGen/AVR/pseudo/LDIWRdK.mir | 24 ++++++++++++++++++++++++ test/CodeGen/AVR/pseudo/LDSWRdK.mir | 24 ++++++++++++++++++++++++ test/CodeGen/AVR/pseudo/LDWRdPtr.mir | 24 ++++++++++++++++++++++++ test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir | 24 ++++++++++++++++++++++++ test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir | 24 ++++++++++++++++++++++++ test/CodeGen/AVR/pseudo/LPMWRdZ.mir | 22 ++++++++++++++++++++++ test/CodeGen/AVR/pseudo/LPMWRdZPi.mir | 22 ++++++++++++++++++++++ test/CodeGen/AVR/pseudo/LSLWRd.mir | 22 ++++++++++++++++++++++ test/CodeGen/AVR/pseudo/LSRWRd.mir | 22 ++++++++++++++++++++++ test/CodeGen/AVR/pseudo/OUTWARr.mir | 22 ++++++++++++++++++++++ test/CodeGen/AVR/pseudo/POPWRd.mir | 22 ++++++++++++++++++++++ test/CodeGen/AVR/pseudo/PUSHWRr.mir | 22 ++++++++++++++++++++++ test/CodeGen/AVR/pseudo/ROLWRd.mir | 22 ++++++++++++++++++++++ test/CodeGen/AVR/pseudo/RORWRd.mir | 22 ++++++++++++++++++++++ test/CodeGen/AVR/pseudo/SEXT.mir | 24 ++++++++++++++++++++++++ test/CodeGen/AVR/pseudo/STDWPtrQRr.mir | 22 ++++++++++++++++++++++ test/CodeGen/AVR/pseudo/STSWKRr.mir | 24 ++++++++++++++++++++++++ test/CodeGen/AVR/pseudo/STWPtrPdRr.mir | 22 ++++++++++++++++++++++ test/CodeGen/AVR/pseudo/STWPtrPiRr.mir | 22 ++++++++++++++++++++++ test/CodeGen/AVR/pseudo/STWPtrRr.mir | 24 ++++++++++++++++++++++++ test/CodeGen/AVR/pseudo/ZEXT.mir | 24 ++++++++++++++++++++++++ 28 files changed, 572 insertions(+), 4 deletions(-) create mode 100644 test/CodeGen/AVR/pseudo/ASRWRd.mir create mode 100644 test/CodeGen/AVR/pseudo/FRMIDX.mir create mode 100644 test/CodeGen/AVR/pseudo/INWRdA.mir create mode 100644 test/CodeGen/AVR/pseudo/LDIWRdK.mir create mode 100644 test/CodeGen/AVR/pseudo/LDSWRdK.mir create mode 100644 test/CodeGen/AVR/pseudo/LDWRdPtr.mir create mode 100644 test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir create mode 100644 test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir create mode 100644 test/CodeGen/AVR/pseudo/LPMWRdZ.mir create mode 100644 test/CodeGen/AVR/pseudo/LPMWRdZPi.mir create mode 100644 test/CodeGen/AVR/pseudo/LSLWRd.mir create mode 100644 test/CodeGen/AVR/pseudo/LSRWRd.mir create mode 100644 test/CodeGen/AVR/pseudo/OUTWARr.mir create mode 100644 test/CodeGen/AVR/pseudo/POPWRd.mir create mode 100644 test/CodeGen/AVR/pseudo/PUSHWRr.mir create mode 100644 test/CodeGen/AVR/pseudo/ROLWRd.mir create mode 100644 test/CodeGen/AVR/pseudo/RORWRd.mir create mode 100644 test/CodeGen/AVR/pseudo/SEXT.mir create mode 100644 test/CodeGen/AVR/pseudo/STDWPtrQRr.mir create mode 100644 test/CodeGen/AVR/pseudo/STSWKRr.mir create mode 100644 test/CodeGen/AVR/pseudo/STWPtrPdRr.mir create mode 100644 test/CodeGen/AVR/pseudo/STWPtrPiRr.mir create mode 100644 test/CodeGen/AVR/pseudo/STWPtrRr.mir create mode 100644 test/CodeGen/AVR/pseudo/ZEXT.mir diff --git a/lib/Target/AVR/AVRExpandPseudoInsts.cpp b/lib/Target/AVR/AVRExpandPseudoInsts.cpp index 3dc32576014cd..ea4a179c00a96 100644 --- a/lib/Target/AVR/AVRExpandPseudoInsts.cpp +++ b/lib/Target/AVR/AVRExpandPseudoInsts.cpp @@ -703,6 +703,16 @@ bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { return true; } +template <> +bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { + llvm_unreachable("wide LPM is unimplemented"); +} + +template <> +bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { + llvm_unreachable("wide LPMPi is unimplemented"); +} + template bool AVRExpandPseudo::expandAtomic(Block &MBB, BlockIt MBBI, Func f) { // Remove the pseudo instruction. @@ -1415,6 +1425,8 @@ bool AVRExpandPseudo::expandMI(Block &MBB, BlockIt MBBI) { EXPAND(AVR::LDWRdPtrPd); case AVR::LDDWRdYQ: //:FIXME: remove this once PR13375 gets fixed EXPAND(AVR::LDDWRdPtrQ); + EXPAND(AVR::LPMWRdZ); + EXPAND(AVR::LPMWRdZPi); EXPAND(AVR::AtomicLoad8); EXPAND(AVR::AtomicLoad16); EXPAND(AVR::AtomicStore8); diff --git a/test/CodeGen/AVR/progmem-extended.ll b/test/CodeGen/AVR/progmem-extended.ll index 4dec871f10994..c4c474e366c7d 100644 --- a/test/CodeGen/AVR/progmem-extended.ll +++ b/test/CodeGen/AVR/progmem-extended.ll @@ -1,4 +1,7 @@ ; RUN: llc < %s -march=avr -mattr=movw,lpmx | FileCheck %s +; XFAIL: * + +# Wide LPM is currently unimplemented in the pseudo expansion pass. ; Tests the extended LPM instructions (LPMW, LPM Rd, Z+). diff --git a/test/CodeGen/AVR/pseudo/ASRWRd.mir b/test/CodeGen/AVR/pseudo/ASRWRd.mir new file mode 100644 index 0000000000000..3e809564ca1c0 --- /dev/null +++ b/test/CodeGen/AVR/pseudo/ASRWRd.mir @@ -0,0 +1,22 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s + +--- | + target triple = "avr--" + define void @test() { + entry: + ret void + } +... + +--- +name: test +body: | + bb.0.entry: + + ; CHECK-LABEL: test + + ; CHECK: %r15 = ASRRd %r15, implicit-def %sreg + ; CHECK-NEXT: %r14 = RORRd %r14, implicit-def %sreg, implicit killed %sreg + + %r15r14 = ASRWRd %r15r14, implicit-def %sreg +... diff --git a/test/CodeGen/AVR/pseudo/CPCWRdRr.mir b/test/CodeGen/AVR/pseudo/CPCWRdRr.mir index cbc742964c18b..2081aa0b5ee47 100644 --- a/test/CodeGen/AVR/pseudo/CPCWRdRr.mir +++ b/test/CodeGen/AVR/pseudo/CPCWRdRr.mir @@ -1,5 +1,4 @@ # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s -# XFAIL: * # This test checks the expansion of the 16-bit CPCW pseudo instruction. @@ -18,5 +17,8 @@ body: | ; CHECK-LABEL: test_cpcwrdrr - %r15r14 = CPCWRdRr %r15r14, %r21r20, implicit-def %sreg, implicit %sreg + ; CHECK: CPCRdRr %r20, %r22, implicit-def %sreg, implicit killed %sreg + ; CHECK-NEXT: CPCRdRr %r21, %r23, implicit-def %sreg, implicit killed %sreg + + CPCWRdRr %r21r20, %r23r22, implicit-def %sreg, implicit %sreg ... diff --git a/test/CodeGen/AVR/pseudo/CPWRdRr.mir b/test/CodeGen/AVR/pseudo/CPWRdRr.mir index 37630148bd835..7e25e7fe22726 100644 --- a/test/CodeGen/AVR/pseudo/CPWRdRr.mir +++ b/test/CodeGen/AVR/pseudo/CPWRdRr.mir @@ -1,5 +1,4 @@ # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s -# XFAIL: * # This test checks the expansion of the 16-bit CPW pseudo instruction. @@ -18,5 +17,8 @@ body: | ; CHECK-LABEL: test_cpwrdrr - %r15r14 = CPWRdRr %r15r14, %r21r20, implicit-def %sreg + ; CHECK: CPRdRr %r14, %r20, implicit-def %sreg + ; CHECK-NEXT: CPCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg + + CPWRdRr %r15r14, %r21r20, implicit-def %sreg ... diff --git a/test/CodeGen/AVR/pseudo/FRMIDX.mir b/test/CodeGen/AVR/pseudo/FRMIDX.mir new file mode 100644 index 0000000000000..47a9397fa6b0e --- /dev/null +++ b/test/CodeGen/AVR/pseudo/FRMIDX.mir @@ -0,0 +1,25 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s + +# TODO: Write this test. +# This instruction isn't expanded by the pseudo expansion passs, but +# rather AVRRegisterInfo::eliminateFrameIndex. + +--- | + target triple = "avr--" + define void @test() { + entry: + ret void + } +... + +--- +name: test +registers: + - { id: 0, class: _ } +body: | + bb.0.entry: + + ; CHECK-LABEL: test + + %r29r28 = FRMIDX %r31r30, 0, implicit-def %sreg +... diff --git a/test/CodeGen/AVR/pseudo/INWRdA.mir b/test/CodeGen/AVR/pseudo/INWRdA.mir new file mode 100644 index 0000000000000..a801598faddd1 --- /dev/null +++ b/test/CodeGen/AVR/pseudo/INWRdA.mir @@ -0,0 +1,22 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s + +--- | + target triple = "avr--" + define void @test() { + entry: + ret void + } +... + +--- +name: test +body: | + bb.0.entry: + + ; CHECK-LABEL: test + + ; CHECK: %r14 = INRdA 31 + ; CHECK-NEXT: %r15 = INRdA 32 + + %r15r14 = INWRdA 31 +... diff --git a/test/CodeGen/AVR/pseudo/LDIWRdK.mir b/test/CodeGen/AVR/pseudo/LDIWRdK.mir new file mode 100644 index 0000000000000..23d16d9c5692b --- /dev/null +++ b/test/CodeGen/AVR/pseudo/LDIWRdK.mir @@ -0,0 +1,24 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s + +# This test checks the expansion of the 16-bit LDIWRdK pseudo instruction. + +--- | + target triple = "avr--" + define void @test_ldiwrdrr() { + entry: + ret void + } +... + +--- +name: test_ldiwrdrr +body: | + bb.0.entry: + + ; CHECK-LABEL: test_ldiwrdrr + + ; CHECK: %r30 = LDIRdK 255 + ; CHECK-NEXT: %r31 = LDIRdK 9 + + %r31r30 = LDIWRdK 2559 +... diff --git a/test/CodeGen/AVR/pseudo/LDSWRdK.mir b/test/CodeGen/AVR/pseudo/LDSWRdK.mir new file mode 100644 index 0000000000000..aa4883634d748 --- /dev/null +++ b/test/CodeGen/AVR/pseudo/LDSWRdK.mir @@ -0,0 +1,24 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s + +# This test checks the expansion of the 16-bit LDSWRdK pseudo instruction. + +--- | + target triple = "avr--" + define void @test_ldswrdrr() { + entry: + ret void + } +... + +--- +name: test_ldswrdrr +body: | + bb.0.entry: + + ; CHECK-LABEL: test_ldswrdrr + + ; CHECK: %r30 = LDSRdK 2559 + ; CHECK-NEXT: %r31 = LDSRdK 2560 + + %r31r30 = LDSWRdK 2559 +... diff --git a/test/CodeGen/AVR/pseudo/LDWRdPtr.mir b/test/CodeGen/AVR/pseudo/LDWRdPtr.mir new file mode 100644 index 0000000000000..aaf9f182f2be5 --- /dev/null +++ b/test/CodeGen/AVR/pseudo/LDWRdPtr.mir @@ -0,0 +1,24 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s + +# This test checks the expansion of the 16-bit LDWRdPtr pseudo instruction. + +--- | + target triple = "avr--" + define void @test_ldwrdptr() { + entry: + ret void + } +... + +--- +name: test_ldwrdptr +body: | + bb.0.entry: + + ; CHECK-LABEL: test_ldwrdptr + + ; CHECK: %r0 = LDRdPtr %r31r30 + ; CHECK-NEXT: early-clobber %r1 = LDDRdPtrQ %r31r30, 1 + + %r1r0 = LDWRdPtr %r31r30 +... diff --git a/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir b/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir new file mode 100644 index 0000000000000..f304cc220cbc9 --- /dev/null +++ b/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir @@ -0,0 +1,24 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s + +# This test checks the expansion of the 16-bit LDWRdPtrPd pseudo instruction. + +--- | + target triple = "avr--" + define void @test_ldwrdptrpd() { + entry: + ret void + } +... + +--- +name: test_ldwrdptrpd +body: | + bb.0.entry: + + ; CHECK-LABEL: test_ldwrdptrpd + + ; CHECK: early-clobber %r1, early-clobber %r31r30 = LDRdPtrPd killed %r31r30 + ; CHECK-NEXT: early-clobber %r0, early-clobber %r31r30 = LDRdPtrPd killed %r31r30 + + %r1r0, %r31r30 = LDWRdPtrPd %r31r30 +... diff --git a/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir b/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir new file mode 100644 index 0000000000000..9153be0bf1c96 --- /dev/null +++ b/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir @@ -0,0 +1,24 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s + +# This test checks the expansion of the 16-bit LDWRdPtrPi pseudo instruction. + +--- | + target triple = "avr--" + define void @test_ldwrdptrpi() { + entry: + ret void + } +... + +--- +name: test_ldwrdptrpi +body: | + bb.0.entry: + + ; CHECK-LABEL: test_ldwrdptrpi + + ; CHECK: early-clobber %r0, early-clobber %r31r30 = LDRdPtrPi killed %r31r30 + ; CHECK-NEXT: early-clobber %r1, early-clobber %r31r30 = LDRdPtrPi killed %r31r30 + + %r1r0, %r31r30 = LDWRdPtrPi %r31r30 +... diff --git a/test/CodeGen/AVR/pseudo/LPMWRdZ.mir b/test/CodeGen/AVR/pseudo/LPMWRdZ.mir new file mode 100644 index 0000000000000..49469845ba8ca --- /dev/null +++ b/test/CodeGen/AVR/pseudo/LPMWRdZ.mir @@ -0,0 +1,22 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# XFAIL: * + +# This instruction is currently unimplemented. + +--- | + target triple = "avr--" + define void @test() { + entry: + ret void + } +... + +--- +name: test +body: | + bb.0.entry: + + ; CHECK-LABEL: test + + %r5r4 = LPMWRdZ %r31r30 +... diff --git a/test/CodeGen/AVR/pseudo/LPMWRdZPi.mir b/test/CodeGen/AVR/pseudo/LPMWRdZPi.mir new file mode 100644 index 0000000000000..2530f28f18690 --- /dev/null +++ b/test/CodeGen/AVR/pseudo/LPMWRdZPi.mir @@ -0,0 +1,22 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# XFAIL: * + +# This instruction is currently unimplemented. + +--- | + target triple = "avr--" + define void @test() { + entry: + ret void + } +... + +--- +name: test +body: | + bb.0.entry: + + ; CHECK-LABEL: test + + %r5r4 = LPMWRdZPi %r31r30, implicit-def %r31r30 +... diff --git a/test/CodeGen/AVR/pseudo/LSLWRd.mir b/test/CodeGen/AVR/pseudo/LSLWRd.mir new file mode 100644 index 0000000000000..441939856aef9 --- /dev/null +++ b/test/CodeGen/AVR/pseudo/LSLWRd.mir @@ -0,0 +1,22 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s + +--- | + target triple = "avr--" + define void @test() { + entry: + ret void + } +... + +--- +name: test +body: | + bb.0.entry: + + ; CHECK-LABEL: test + + ; CHECK: %r14 = LSLRd %r14, implicit-def %sreg + ; CHECK-NEXT: %r15 = ROLRd %r15, implicit-def %sreg, implicit killed %sreg + + %r15r14 = LSLWRd %r15r14, implicit-def %sreg +... diff --git a/test/CodeGen/AVR/pseudo/LSRWRd.mir b/test/CodeGen/AVR/pseudo/LSRWRd.mir new file mode 100644 index 0000000000000..f5ffb93f4035a --- /dev/null +++ b/test/CodeGen/AVR/pseudo/LSRWRd.mir @@ -0,0 +1,22 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s + +--- | + target triple = "avr--" + define void @test() { + entry: + ret void + } +... + +--- +name: test +body: | + bb.0.entry: + + ; CHECK-LABEL: test + + ; CHECK: %r15 = LSRRd %r15, implicit-def %sreg + ; CHECK-NEXT: %r14 = RORRd %r14, implicit-def %sreg, implicit killed %sreg + + %r15r14 = LSRWRd %r15r14, implicit-def %sreg +... diff --git a/test/CodeGen/AVR/pseudo/OUTWARr.mir b/test/CodeGen/AVR/pseudo/OUTWARr.mir new file mode 100644 index 0000000000000..85e9f5259a871 --- /dev/null +++ b/test/CodeGen/AVR/pseudo/OUTWARr.mir @@ -0,0 +1,22 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s + +--- | + target triple = "avr--" + define void @test() { + entry: + ret void + } +... + +--- +name: test +body: | + bb.0.entry: + + ; CHECK-LABEL: test + + ; CHECK: OUTARr 32, %r15 + ; CHECK-NEXT: OUTARr 31, %r14 + + OUTWARr 31, %r15r14 +... diff --git a/test/CodeGen/AVR/pseudo/POPWRd.mir b/test/CodeGen/AVR/pseudo/POPWRd.mir new file mode 100644 index 0000000000000..6794742bf54ab --- /dev/null +++ b/test/CodeGen/AVR/pseudo/POPWRd.mir @@ -0,0 +1,22 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s + +--- | + target triple = "avr--" + define void @test() { + entry: + ret void + } +... + +--- +name: test +body: | + bb.0.entry: + + ; CHECK-LABEL: test + + ; CHECK: %r29 = POPRd implicit-def %sp, implicit %sp + ; CHECK-LABEL: %r28 = POPRd implicit-def %sp, implicit %sp + + %r29r28 = POPWRd implicit-def %sp, implicit %sp +... diff --git a/test/CodeGen/AVR/pseudo/PUSHWRr.mir b/test/CodeGen/AVR/pseudo/PUSHWRr.mir new file mode 100644 index 0000000000000..93920867030f7 --- /dev/null +++ b/test/CodeGen/AVR/pseudo/PUSHWRr.mir @@ -0,0 +1,22 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s + +--- | + target triple = "avr--" + define void @test() { + entry: + ret void + } +... + +--- +name: test +body: | + bb.0.entry: + + ; CHECK-LABEL: test + + ; CHECK: PUSHRr %r28, implicit-def %sp, implicit %sp + ; CHECK-NEXT: PUSHRr %r29, implicit-def %sp, implicit %sp + + PUSHWRr %r29r28, implicit-def %sp, implicit %sp +... diff --git a/test/CodeGen/AVR/pseudo/ROLWRd.mir b/test/CodeGen/AVR/pseudo/ROLWRd.mir new file mode 100644 index 0000000000000..242ab09e55f42 --- /dev/null +++ b/test/CodeGen/AVR/pseudo/ROLWRd.mir @@ -0,0 +1,22 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# XFAIL: * + +# This instruction is unimplemented. + +--- | + target triple = "avr--" + define void @test() { + entry: + ret void + } +... + +--- +name: test +body: | + bb.0.entry: + + ; CHECK-LABEL: test + + %r15r14 = ROLWRd %r15r14, implicit-def %sreg, implicit %sreg +... diff --git a/test/CodeGen/AVR/pseudo/RORWRd.mir b/test/CodeGen/AVR/pseudo/RORWRd.mir new file mode 100644 index 0000000000000..77362cacea70d --- /dev/null +++ b/test/CodeGen/AVR/pseudo/RORWRd.mir @@ -0,0 +1,22 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# XFAIL: * + +# This instruction is unimplemented. + +--- | + target triple = "avr--" + define void @test() { + entry: + ret void + } +... + +--- +name: test +body: | + bb.0.entry: + + ; CHECK-LABEL: test + + %r15r14 = RORWRd %r15r14, implicit-def %sreg, implicit %sreg +... diff --git a/test/CodeGen/AVR/pseudo/SEXT.mir b/test/CodeGen/AVR/pseudo/SEXT.mir new file mode 100644 index 0000000000000..069eb883dcc1b --- /dev/null +++ b/test/CodeGen/AVR/pseudo/SEXT.mir @@ -0,0 +1,24 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s + +--- | + target triple = "avr--" + define void @test() { + entry: + ret void + } +... + +--- +name: test +body: | + bb.0.entry: + + ; CHECK-LABEL: test + + ; CHECK: %r14 = MOVRdRr %r31 + ; CHECK-NEXT: %r15 = MOVRdRr %r31 + ; CHECK-NEXT: %r15 = LSLRd killed %r15, implicit-def %sreg + ; CHECK-NEXT: %r15 = SBCRdRr killed %r15, killed %r15, implicit-def %sreg, implicit killed %sreg + + %r15r14 = SEXT %r31, implicit-def %sreg +... diff --git a/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir b/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir new file mode 100644 index 0000000000000..ff2fdb9155e1b --- /dev/null +++ b/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir @@ -0,0 +1,22 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s + +--- | + target triple = "avr--" + define void @test() { + entry: + ret void + } +... + +--- +name: test +body: | + bb.0.entry: + + ; CHECK-LABEL: test + + ; CHECK: STDPtrQRr %r29r28, 10, %r0 + ; CHECK-NEXT: STDPtrQRr %r29r28, 11, %r1 + + STDWPtrQRr %r29r28, 10, %r1r0 +... diff --git a/test/CodeGen/AVR/pseudo/STSWKRr.mir b/test/CodeGen/AVR/pseudo/STSWKRr.mir new file mode 100644 index 0000000000000..ccf852271ae98 --- /dev/null +++ b/test/CodeGen/AVR/pseudo/STSWKRr.mir @@ -0,0 +1,24 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s + +# This test checks the expansion of the 16-bit STSWRdK pseudo instruction. + +--- | + target triple = "avr--" + define void @test_stswkrr() { + entry: + ret void + } +... + +--- +name: test_stswkrr +body: | + bb.0.entry: + + ; CHECK-LABEL: test_stswkrr + + ; CHECK: STSKRr 2560, %r31 + ; CHECK-NEXT: STSKRr 2559, %r30 + + STSWKRr 2559, %r31r30 +... diff --git a/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir b/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir new file mode 100644 index 0000000000000..0d0d9e909e4af --- /dev/null +++ b/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir @@ -0,0 +1,22 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s + +--- | + target triple = "avr--" + define void @test() { + entry: + ret void + } +... + +--- +name: test +body: | + bb.0.entry: + + ; CHECK-LABEL: test + + ; CHECK: early-clobber %r31r30 = STPtrPdRr killed %r31r30, %r29, 52 + ; CHECK-NEXT: early-clobber %r31r30 = STPtrPdRr killed %r31r30, %r28, 52 + + %r31r30 = STWPtrPdRr %r31r30, %r29r28, 52 +... diff --git a/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir b/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir new file mode 100644 index 0000000000000..a436d9b109bbc --- /dev/null +++ b/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir @@ -0,0 +1,22 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s + +--- | + target triple = "avr--" + define void @test() { + entry: + ret void + } +... + +--- +name: test +body: | + bb.0.entry: + + ; CHECK-LABEL: test + + ; CHECK: early-clobber %r31r30 = STPtrPiRr killed %r31r30, %r28, 52 + ; CHECK-NEXT: early-clobber %r31r30 = STPtrPiRr killed %r31r30, %r29, 52 + + %r31r30 = STWPtrPiRr %r31r30, %r29r28, 52 +... diff --git a/test/CodeGen/AVR/pseudo/STWPtrRr.mir b/test/CodeGen/AVR/pseudo/STWPtrRr.mir new file mode 100644 index 0000000000000..f85f4f8a0452a --- /dev/null +++ b/test/CodeGen/AVR/pseudo/STWPtrRr.mir @@ -0,0 +1,24 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s + +# This test checks the expansion of the 16-bit STSWRdK pseudo instruction. + +--- | + target triple = "avr--" + define void @test_stwptrrr() { + entry: + ret void + } +... + +--- +name: test_stwptrrr +body: | + bb.0.entry: + + ; CHECK-LABEL: test_stwptrrr + + ; CHECK: STPtrRr %r31r30, %r16 + ; CHECK-NEXT: STDPtrQRr %r31r30, 1, %r17 + + STWPtrRr %r31r30, %r17r16 +... diff --git a/test/CodeGen/AVR/pseudo/ZEXT.mir b/test/CodeGen/AVR/pseudo/ZEXT.mir new file mode 100644 index 0000000000000..069eb883dcc1b --- /dev/null +++ b/test/CodeGen/AVR/pseudo/ZEXT.mir @@ -0,0 +1,24 @@ +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s + +--- | + target triple = "avr--" + define void @test() { + entry: + ret void + } +... + +--- +name: test +body: | + bb.0.entry: + + ; CHECK-LABEL: test + + ; CHECK: %r14 = MOVRdRr %r31 + ; CHECK-NEXT: %r15 = MOVRdRr %r31 + ; CHECK-NEXT: %r15 = LSLRd killed %r15, implicit-def %sreg + ; CHECK-NEXT: %r15 = SBCRdRr killed %r15, killed %r15, implicit-def %sreg, implicit killed %sreg + + %r15r14 = SEXT %r31, implicit-def %sreg +...