Skip to content

Commit e0d7dbe

Browse files
Zlatko BuljanZlatko Buljan
Zlatko Buljan
authored and
Zlatko Buljan
committed
[mips][microMIPS] Implement PRECEQ.W.PHL, PRECEQ.W.PHR, PRECEQU.PH.QBL, PRECEQU.PH.QBLA, PRECEQU.PH.QBR, PRECEQU.PH.QBRA, PRECEU.PH.QBL, PRECEU.PH.QBLA, PRECEU.PH.QBR and PRECEU.PH.QBRA instructions
Differential Revision: http://reviews.llvm.org/D14279 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253326 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent 6c42346 commit e0d7dbe

File tree

6 files changed

+92
-10
lines changed

6 files changed

+92
-10
lines changed

‎lib/Target/Mips/MicroMipsDSPInstrInfo.td

+42
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,16 @@ class SHRL_PH_MMR2_ENC : POOL32A_2RSA4OP6_FMT<"shrl.ph", 0b001111>;
6767
class SHRL_QB_MM_ENC : POOL32A_2RSA3_FMT<"shrl.qb", 0b1100001>;
6868
class SHRLV_PH_MMR2_ENC : POOL32A_3RB0_FMT<"shrlv.ph", 0b1100010101>;
6969
class SHRLV_QB_MM_ENC : POOL32A_3RB0_FMT<"shrlv.qb", 0b1101010101>;
70+
class PRECEQ_W_PHL_MM_ENC : POOL32A_2R_FMT<"preceq.w.phl", 0b0101000100>;
71+
class PRECEQ_W_PHR_MM_ENC : POOL32A_2R_FMT<"preceq.w.phr", 0b0110000100>;
72+
class PRECEQU_PH_QBL_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbl", 0b0111000100>;
73+
class PRECEQU_PH_QBLA_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbla", 0b0111001100>;
74+
class PRECEQU_PH_QBR_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbr", 0b1001000100>;
75+
class PRECEQU_PH_QBRA_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbra", 0b1001001100>;
76+
class PRECEU_PH_QBL_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbl", 0b1011000100>;
77+
class PRECEU_PH_QBLA_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbla", 0b1011001100>;
78+
class PRECEU_PH_QBR_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbr", 0b1101000100>;
79+
class PRECEU_PH_QBRA_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbra", 0b1101001100>;
7080

7181
// Instruction desc.
7282
class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
@@ -84,6 +94,26 @@ class ABSQ_S_W_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
8494
"absq_s.w", int_mips_absq_s_w, NoItinerary, GPR32Opnd>, Defs<[DSPOutFlag20]>;
8595
class ABSQ_S_QB_MMR2_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
8696
"absq_s.qb", int_mips_absq_s_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
97+
class PRECEQ_W_PHL_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
98+
"preceq.w.phl", int_mips_preceq_w_phl, NoItinerary, GPR32Opnd, DSPROpnd>;
99+
class PRECEQ_W_PHR_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
100+
"preceq.w.phr", int_mips_preceq_w_phr, NoItinerary, GPR32Opnd, DSPROpnd>;
101+
class PRECEQU_PH_QBL_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
102+
"precequ.ph.qbl", int_mips_precequ_ph_qbl, NoItinerary, DSPROpnd>;
103+
class PRECEQU_PH_QBLA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
104+
"precequ.ph.qbla", int_mips_precequ_ph_qbla, NoItinerary, DSPROpnd>;
105+
class PRECEQU_PH_QBR_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
106+
"precequ.ph.qbr", int_mips_precequ_ph_qbr, NoItinerary, DSPROpnd>;
107+
class PRECEQU_PH_QBRA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
108+
"precequ.ph.qbra", int_mips_precequ_ph_qbra, NoItinerary, DSPROpnd>;
109+
class PRECEU_PH_QBL_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
110+
"preceu.ph.qbl", int_mips_preceu_ph_qbl, NoItinerary, DSPROpnd>;
111+
class PRECEU_PH_QBLA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
112+
"preceu.ph.qbla", int_mips_preceu_ph_qbla, NoItinerary, DSPROpnd>;
113+
class PRECEU_PH_QBR_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
114+
"preceu.ph.qbr", int_mips_preceu_ph_qbr, NoItinerary, DSPROpnd>;
115+
class PRECEU_PH_QBRA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
116+
"preceu.ph.qbra", int_mips_preceu_ph_qbra, NoItinerary, DSPROpnd>;
87117

88118
class SHLL_R2_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
89119
SDPatternOperator ImmPat, InstrItinClass itin,
@@ -192,6 +222,18 @@ def SHRAV_R_W_MM : DspMMRel, SHRAV_R_W_MM_ENC, SHRAV_R_W_MM_DESC;
192222
def SHRA_R_W_MM : DspMMRel, SHRA_R_W_MM_ENC, SHRA_R_W_MM_DESC;
193223
def SHRL_QB_MM : DspMMRel, SHRL_QB_MM_ENC, SHRL_QB_MM_DESC;
194224
def SHRLV_QB_MM : DspMMRel, SHRLV_QB_MM_ENC, SHRLV_QB_MM_DESC;
225+
def PRECEQ_W_PHL_MM : DspMMRel, PRECEQ_W_PHL_MM_ENC, PRECEQ_W_PHL_MM_DESC;
226+
def PRECEQ_W_PHR_MM : DspMMRel, PRECEQ_W_PHR_MM_ENC, PRECEQ_W_PHR_MM_DESC;
227+
def PRECEQU_PH_QBL_MM : DspMMRel, PRECEQU_PH_QBL_MM_ENC, PRECEQU_PH_QBL_MM_DESC;
228+
def PRECEQU_PH_QBLA_MM : DspMMRel, PRECEQU_PH_QBLA_MM_ENC,
229+
PRECEQU_PH_QBLA_MM_DESC;
230+
def PRECEQU_PH_QBR_MM : DspMMRel, PRECEQU_PH_QBR_MM_ENC, PRECEQU_PH_QBR_MM_DESC;
231+
def PRECEQU_PH_QBRA_MM : DspMMRel, PRECEQU_PH_QBRA_MM_ENC,
232+
PRECEQU_PH_QBRA_MM_DESC;
233+
def PRECEU_PH_QBL_MM : DspMMRel, PRECEU_PH_QBL_MM_ENC, PRECEU_PH_QBL_MM_DESC;
234+
def PRECEU_PH_QBLA_MM : DspMMRel, PRECEU_PH_QBLA_MM_ENC, PRECEU_PH_QBLA_MM_DESC;
235+
def PRECEU_PH_QBR_MM : DspMMRel, PRECEU_PH_QBR_MM_ENC, PRECEU_PH_QBR_MM_DESC;
236+
def PRECEU_PH_QBRA_MM : DspMMRel, PRECEU_PH_QBRA_MM_ENC, PRECEU_PH_QBRA_MM_DESC;
195237
// microMIPS DSP Rev 2
196238
def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
197239
ISA_DSPR2;

‎lib/Target/Mips/MipsDSPInstrInfo.td

+10-10
Original file line numberDiff line numberDiff line change
@@ -1107,16 +1107,16 @@ def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
11071107
def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
11081108
def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
11091109
def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
1110-
def PRECEQ_W_PHL : PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1111-
def PRECEQ_W_PHR : PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1112-
def PRECEQU_PH_QBL : PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1113-
def PRECEQU_PH_QBR : PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1114-
def PRECEQU_PH_QBLA : PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1115-
def PRECEQU_PH_QBRA : PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1116-
def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1117-
def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1118-
def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1119-
def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1110+
def PRECEQ_W_PHL : DspMMRel, PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1111+
def PRECEQ_W_PHR : DspMMRel, PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1112+
def PRECEQU_PH_QBL : DspMMRel, PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1113+
def PRECEQU_PH_QBR : DspMMRel, PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1114+
def PRECEQU_PH_QBLA : DspMMRel, PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1115+
def PRECEQU_PH_QBRA : DspMMRel, PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1116+
def PRECEU_PH_QBL : DspMMRel, PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1117+
def PRECEU_PH_QBR : DspMMRel, PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1118+
def PRECEU_PH_QBLA : DspMMRel, PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1119+
def PRECEU_PH_QBRA : DspMMRel, PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
11201120
def SHLL_QB : DspMMRel, SHLL_QB_ENC, SHLL_QB_DESC;
11211121
def SHLLV_QB : DspMMRel, SHLLV_QB_ENC, SHLLV_QB_DESC;
11221122
def SHRL_QB : DspMMRel, SHRL_QB_ENC, SHRL_QB_DESC;

‎test/MC/Disassembler/Mips/micromips-dsp/valid.txt

+10
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,16 @@
2020
0x01 0xac 0xba 0xbc # CHECK: msubu $ac2, $12, $13
2121
0x00 0x62 0xcc 0xbc # CHECK: mult $ac3, $2, $3
2222
0x00 0xa4 0x9c 0xbc # CHECK: multu $ac2, $4, $5
23+
0x00 0x22 0x51 0x3c # CHECK: preceq.w.phl $1, $2
24+
0x00 0x64 0x61 0x3c # CHECK: preceq.w.phr $3, $4
25+
0x00 0xa6 0x71 0x3c # CHECK: precequ.ph.qbl $5, $6
26+
0x00 0xe8 0x73 0x3c # CHECK: precequ.ph.qbla $7, $8
27+
0x01 0x2a 0x91 0x3c # CHECK: precequ.ph.qbr $9, $10
28+
0x01 0x6c 0x93 0x3c # CHECK: precequ.ph.qbra $11, $12
29+
0x01 0xae 0xb1 0x3c # CHECK: preceu.ph.qbl $13, $14
30+
0x01 0xf0 0xb3 0x3c # CHECK: preceu.ph.qbla $15, $16
31+
0x02 0x32 0xd1 0x3c # CHECK: preceu.ph.qbr $17, $18
32+
0x02 0x74 0xd3 0x3c # CHECK: preceu.ph.qbra $19, $20
2333
0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5
2434
0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5
2535
0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5

‎test/MC/Disassembler/Mips/micromips-dspr2/valid.txt

+10
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,16 @@
3333
0x01 0xac 0xba 0xbc # CHECK: msubu $ac2, $12, $13
3434
0x00 0x62 0xcc 0xbc # CHECK: mult $ac3, $2, $3
3535
0x00 0xa4 0x9c 0xbc # CHECK: multu $ac2, $4, $5
36+
0x00 0x22 0x51 0x3c # CHECK: preceq.w.phl $1, $2
37+
0x00 0x64 0x61 0x3c # CHECK: preceq.w.phr $3, $4
38+
0x00 0xa6 0x71 0x3c # CHECK: precequ.ph.qbl $5, $6
39+
0x00 0xe8 0x73 0x3c # CHECK: precequ.ph.qbla $7, $8
40+
0x01 0x2a 0x91 0x3c # CHECK: precequ.ph.qbr $9, $10
41+
0x01 0x6c 0x93 0x3c # CHECK: precequ.ph.qbra $11, $12
42+
0x01 0xae 0xb1 0x3c # CHECK: preceu.ph.qbl $13, $14
43+
0x01 0xf0 0xb3 0x3c # CHECK: preceu.ph.qbla $15, $16
44+
0x02 0x32 0xd1 0x3c # CHECK: preceu.ph.qbr $17, $18
45+
0x02 0x74 0xd3 0x3c # CHECK: preceu.ph.qbra $19, $20
3646
0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5
3747
0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5
3848
0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5

‎test/MC/Mips/micromips-dsp/valid.s

+10
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,16 @@
2121
msubu $ac2, $12, $13 # CHECK: msubu $ac2, $12, $13 # encoding: [0x01,0xac,0xba,0xbc]
2222
mult $ac3, $2, $3 # CHECK: mult $ac3, $2, $3 # encoding: [0x00,0x62,0xcc,0xbc]
2323
multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0xa4,0x9c,0xbc]
24+
preceq.w.phl $1, $2 # CHECK: preceq.w.phl $1, $2 # encoding: [0x00,0x22,0x51,0x3c]
25+
preceq.w.phr $3, $4 # CHECK: preceq.w.phr $3, $4 # encoding: [0x00,0x64,0x61,0x3c]
26+
precequ.ph.qbl $5, $6 # CHECK: precequ.ph.qbl $5, $6 # encoding: [0x00,0xa6,0x71,0x3c]
27+
precequ.ph.qbla $7, $8 # CHECK: precequ.ph.qbla $7, $8 # encoding: [0x00,0xe8,0x73,0x3c]
28+
precequ.ph.qbr $9, $10 # CHECK: precequ.ph.qbr $9, $10 # encoding: [0x01,0x2a,0x91,0x3c]
29+
precequ.ph.qbra $11, $12 # CHECK: precequ.ph.qbra $11, $12 # encoding: [0x01,0x6c,0x93,0x3c]
30+
preceu.ph.qbl $13, $14 # CHECK: preceu.ph.qbl $13, $14 # encoding: [0x01,0xae,0xb1,0x3c]
31+
preceu.ph.qbla $15, $16 # CHECK: preceu.ph.qbla $15, $16 # encoding: [0x01,0xf0,0xb3,0x3c]
32+
preceu.ph.qbr $17, $18 # CHECK: preceu.ph.qbr $17, $18 # encoding: [0x02,0x32,0xd1,0x3c]
33+
preceu.ph.qbra $19, $20 # CHECK: preceu.ph.qbra $19, $20 # encoding: [0x02,0x74,0xd3,0x3c]
2434
shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5]
2535
shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5]
2636
shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c]

‎test/MC/Mips/micromips-dspr2/valid.s

+10
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,16 @@
3434
msubu $ac2, $12, $13 # CHECK: msubu $ac2, $12, $13 # encoding: [0x01,0xac,0xba,0xbc]
3535
mult $ac3, $2, $3 # CHECK: mult $ac3, $2, $3 # encoding: [0x00,0x62,0xcc,0xbc]
3636
multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0xa4,0x9c,0xbc]
37+
preceq.w.phl $1, $2 # CHECK: preceq.w.phl $1, $2 # encoding: [0x00,0x22,0x51,0x3c]
38+
preceq.w.phr $3, $4 # CHECK: preceq.w.phr $3, $4 # encoding: [0x00,0x64,0x61,0x3c]
39+
precequ.ph.qbl $5, $6 # CHECK: precequ.ph.qbl $5, $6 # encoding: [0x00,0xa6,0x71,0x3c]
40+
precequ.ph.qbla $7, $8 # CHECK: precequ.ph.qbla $7, $8 # encoding: [0x00,0xe8,0x73,0x3c]
41+
precequ.ph.qbr $9, $10 # CHECK: precequ.ph.qbr $9, $10 # encoding: [0x01,0x2a,0x91,0x3c]
42+
precequ.ph.qbra $11, $12 # CHECK: precequ.ph.qbra $11, $12 # encoding: [0x01,0x6c,0x93,0x3c]
43+
preceu.ph.qbl $13, $14 # CHECK: preceu.ph.qbl $13, $14 # encoding: [0x01,0xae,0xb1,0x3c]
44+
preceu.ph.qbla $15, $16 # CHECK: preceu.ph.qbla $15, $16 # encoding: [0x01,0xf0,0xb3,0x3c]
45+
preceu.ph.qbr $17, $18 # CHECK: preceu.ph.qbr $17, $18 # encoding: [0x02,0x32,0xd1,0x3c]
46+
preceu.ph.qbra $19, $20 # CHECK: preceu.ph.qbra $19, $20 # encoding: [0x02,0x74,0xd3,0x3c]
3747
shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5]
3848
shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5]
3949
shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c]

0 commit comments

Comments
 (0)