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Starred repositories
Examples for compiling code using the RISC-V gnu toolchain
rarsm / rars
Forked from TheThirdOne/rarsRARS -- RISC-V Assembler and Runtime Simulator
61c-teach / venus
Forked from ThaumicMekanism/venusRISC-V instruction set simulator built for education
ThaumicMekanism / venus
Forked from kvakil/venusRISC-V instruction set simulator built for education
Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
A Fully functional RISC-V Proccessor written in SystemVerilog and tested using Verilator.
RISCV model for Verilator/FPGA targets
Verilog implementation of multi-stage 32-bit RISC-V processor
Linux capable RISC-V SoC designed to be readable and useful.
This library provides a way to move cursor to specified coordinates on screen reliably, while being randomly arced to look like real hand moved it there by using a mouse. The default settings shoul…
OpenOCD compatible, FT4232H based jtag programmer and debug probe
Customizable Bootloader for STM32 microcontrollers. This example demonstrates how to perform in-application-programming of a firmware located on an external SD card with FAT32 file system.
Coding for classic 68k Amigas in C99 and assembler.
Cross-assembler (68000 to x86 or to C), and disassembler (Atari .prg to devpac .s)
SHC - ShortHand C is a project aimed at simplifying the usage of C by using predefined snippets and a drag and drop graphics code generatoe, along with the ability to debug and version control your…
A quick and easy to use drag and drop retro game creator for your favourite handheld video game system