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0052-RISCV-Codegen-support-for-floating-point-comparison-.patch
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <[email protected]>
Subject: [RISCV] Codegen support for floating point comparison operations
This patch also includes extensive tests targeted at select and br+fcmp IR
inputs.
---
lib/Target/RISCV/RISCVISelLowering.cpp | 17 +-
lib/Target/RISCV/RISCVInstrInfo.cpp | 19 +-
lib/Target/RISCV/RISCVInstrInfo.td | 13 +-
lib/Target/RISCV/RISCVInstrInfoF.td | 16 ++
test/CodeGen/RISCV/bare-select.ll | 14 +
test/CodeGen/RISCV/float-br-fcmp.ll | 474 ++++++++++++++++++++++++++++++++
test/CodeGen/RISCV/float-fcmp.ll | 215 +++++++++++++++
test/CodeGen/RISCV/float-select-fcmp.ll | 304 ++++++++++++++++++++
8 files changed, 1060 insertions(+), 12 deletions(-)
create mode 100644 test/CodeGen/RISCV/float-br-fcmp.ll
create mode 100644 test/CodeGen/RISCV/float-fcmp.ll
create mode 100644 test/CodeGen/RISCV/float-select-fcmp.ll
diff --git a/lib/Target/RISCV/RISCVISelLowering.cpp b/lib/Target/RISCV/RISCVISelLowering.cpp
index f75a883c757..572dafaf66d 100644
--- a/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -109,6 +109,14 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
if (Subtarget.hasStdExtF()) {
setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
+ for (auto CC :
+ {ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETO, ISD::SETUEQ,
+ ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE,
+ ISD::SETGT, ISD::SETGE, ISD::SETNE})
+ setCondCodeAction(CC, MVT::f32, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
+ setOperationAction(ISD::SELECT, MVT::f32, Custom);
+ setOperationAction(ISD::BR_CC, MVT::f32, Expand);
}
setOperationAction(ISD::GlobalAddress, XLenVT, Custom);
@@ -383,8 +391,13 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
DebugLoc DL = MI.getDebugLoc();
- assert(MI.getOpcode() == RISCV::Select_GPR_Using_CC_GPR &&
- "Unexpected instr type to insert");
+ switch (MI.getOpcode()) {
+ default:
+ llvm_unreachable("Unexpected instr type to insert");
+ case RISCV::Select_GPR_Using_CC_GPR:
+ case RISCV::Select_FPR32_Using_CC_GPR:
+ break;
+ }
// To "insert" a SELECT instruction, we actually have to insert the triangle
// control-flow pattern. The incoming instruction knows the destination vreg
diff --git a/lib/Target/RISCV/RISCVInstrInfo.cpp b/lib/Target/RISCV/RISCVInstrInfo.cpp
index b630fb87286..a9424a6b077 100644
--- a/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -37,12 +37,21 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, unsigned DstReg,
unsigned SrcReg, bool KillSrc) const {
- assert(RISCV::GPRRegClass.contains(DstReg, SrcReg) &&
- "Impossible reg-to-reg copy");
+ if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
+ BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
+ .addReg(SrcReg, getKillRegState(KillSrc))
+ .addImm(0);
+ return;
+ }
- BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
- .addReg(SrcReg, getKillRegState(KillSrc))
- .addImm(0);
+ if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) {
+ BuildMI(MBB, MBBI, DL, get(RISCV::FSGNJ_S), DstReg)
+ .addReg(SrcReg, getKillRegState(KillSrc))
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ return;
+ }
+
+ llvm_unreachable("Impossible reg-to-reg copy");
}
void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
diff --git a/lib/Target/RISCV/RISCVInstrInfo.td b/lib/Target/RISCV/RISCVInstrInfo.td
index 8eb2cdaff1f..6a3f596b663 100644
--- a/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/lib/Target/RISCV/RISCVInstrInfo.td
@@ -425,11 +425,14 @@ def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>;
def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>;
let usesCustomInserter = 1 in
-def Select_GPR_Using_CC_GPR
- : Pseudo<(outs GPR:$dst),
- (ins GPR:$lhs, GPR:$rhs, ixlenimm:$imm, GPR:$src, GPR:$src2),
- [(set XLenVT:$dst, (SelectCC GPR:$lhs, GPR:$rhs,
- (XLenVT imm:$imm), GPR:$src, GPR:$src2))]>;
+class SelectCC_rrirr<RegisterClass valty, RegisterClass cmpty>
+ : Pseudo<(outs valty:$dst),
+ (ins cmpty:$lhs, cmpty:$rhs, ixlenimm:$imm,
+ valty:$truev, valty:$falsev),
+ [(set valty:$dst, (SelectCC cmpty:$lhs, cmpty:$rhs,
+ (XLenVT imm:$imm), valty:$truev, valty:$falsev))]>;
+
+def Select_GPR_Using_CC_GPR : SelectCC_rrirr<GPR, GPR>;
/// Branches and jumps
diff --git a/lib/Target/RISCV/RISCVInstrInfoF.td b/lib/Target/RISCV/RISCVInstrInfoF.td
index 0ec46766c69..fa64775af00 100644
--- a/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -239,10 +239,26 @@ def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>;
def : PatFpr32Fpr32<fminnum, FMIN_S>;
def : PatFpr32Fpr32<fmaxnum, FMAX_S>;
+/// Setcc
+
+def : PatFpr32Fpr32<seteq, FEQ_S>;
def : PatFpr32Fpr32<setoeq, FEQ_S>;
+def : PatFpr32Fpr32<setlt, FLT_S>;
def : PatFpr32Fpr32<setolt, FLT_S>;
+def : PatFpr32Fpr32<setle, FLE_S>;
def : PatFpr32Fpr32<setole, FLE_S>;
+// Define pattern expansions for setcc operations which aren't directly
+// handled by a RISC-V instruction and aren't expanded in the SelectionDAG
+// Legalizer.
+
+def : Pat<(setuo FPR32:$rs1, FPR32:$rs2),
+ (SLTIU (AND (FEQ_S FPR32:$rs1, FPR32:$rs1),
+ (FEQ_S FPR32:$rs2, FPR32:$rs2)),
+ 1)>;
+
+def Select_FPR32_Using_CC_GPR : SelectCC_rrirr<FPR32, GPR>;
+
/// Loads
defm : LdPat<load, FLW>;
diff --git a/test/CodeGen/RISCV/bare-select.ll b/test/CodeGen/RISCV/bare-select.ll
index a46afe27143..d77728c3f34 100644
--- a/test/CodeGen/RISCV/bare-select.ll
+++ b/test/CodeGen/RISCV/bare-select.ll
@@ -15,3 +15,17 @@ define i32 @bare_select(i1 %a, i32 %b, i32 %c) {
%1 = select i1 %a, i32 %b, i32 %c
ret i32 %1
}
+
+define float @bare_select_float(i1 %a, float %b, float %c) {
+; RV32I-LABEL: bare_select_float:
+; RV32I: # %bb.0:
+; RV32I-NEXT: andi a0, a0, 1
+; RV32I-NEXT: bne a0, zero, .LBB1_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: addi a1, a2, 0
+; RV32I-NEXT: .LBB1_2:
+; RV32I-NEXT: addi a0, a1, 0
+; RV32I-NEXT: jalr zero, ra, 0
+ %1 = select i1 %a, float %b, float %c
+ ret float %1
+}
diff --git a/test/CodeGen/RISCV/float-br-fcmp.ll b/test/CodeGen/RISCV/float-br-fcmp.ll
new file mode 100644
index 00000000000..17c3741e7a3
--- /dev/null
+++ b/test/CodeGen/RISCV/float-br-fcmp.ll
@@ -0,0 +1,474 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32IF %s
+
+declare void @abort()
+declare void @exit(i32)
+
+define void @br_fcmp_false(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_false:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: addi a0, zero, 1
+; RV32IF-NEXT: bne a0, zero, .LBB0_2
+; RV32IF-NEXT: # %bb.1: # %if.then
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: jalr zero, ra, 0
+; RV32IF-NEXT: .LBB0_2: # %if.else
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr ra, a0, 0
+ %1 = fcmp false float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.then:
+ ret void
+if.else:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_oeq(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_oeq:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: feq.s a0, ft1, ft0
+; RV32IF-NEXT: bne a0, zero, .LBB1_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: jalr zero, ra, 0
+; RV32IF-NEXT: .LBB1_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr ra, a0, 0
+ %1 = fcmp oeq float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+; TODO: generated code quality for this is very poor due to
+; DAGCombiner::visitXOR converting the legal setoeq to setune, which requires
+; expansion.
+define void @br_fcmp_oeq_alt(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_oeq_alt:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: feq.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: beq a0, zero, .LBB2_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: jalr zero, ra, 0
+; RV32IF-NEXT: .LBB2_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr ra, a0, 0
+ %1 = fcmp oeq float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.then:
+ tail call void @abort()
+ unreachable
+if.else:
+ ret void
+}
+
+define void @br_fcmp_ogt(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ogt:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: flt.s a0, ft1, ft0
+; RV32IF-NEXT: bne a0, zero, .LBB3_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: jalr zero, ra, 0
+; RV32IF-NEXT: .LBB3_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr ra, a0, 0
+ %1 = fcmp ogt float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_oge(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_oge:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: fle.s a0, ft1, ft0
+; RV32IF-NEXT: bne a0, zero, .LBB4_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: jalr zero, ra, 0
+; RV32IF-NEXT: .LBB4_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr ra, a0, 0
+ %1 = fcmp oge float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_olt(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_olt:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: flt.s a0, ft1, ft0
+; RV32IF-NEXT: bne a0, zero, .LBB5_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: jalr zero, ra, 0
+; RV32IF-NEXT: .LBB5_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr ra, a0, 0
+ %1 = fcmp olt float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_ole(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ole:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: fle.s a0, ft1, ft0
+; RV32IF-NEXT: bne a0, zero, .LBB6_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: jalr zero, ra, 0
+; RV32IF-NEXT: .LBB6_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr ra, a0, 0
+ %1 = fcmp ole float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+; TODO: feq.s+sltiu+bne -> feq.s+beq
+define void @br_fcmp_one(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_one:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: feq.s a0, ft1, ft1
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: and a0, a1, a0
+; RV32IF-NEXT: feq.s a1, ft0, ft1
+; RV32IF-NEXT: xori a1, a1, -1
+; RV32IF-NEXT: sltiu a0, a0, 1
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: and a0, a1, a0
+; RV32IF-NEXT: bne a0, zero, .LBB7_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: jalr zero, ra, 0
+; RV32IF-NEXT: .LBB7_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr ra, a0, 0
+ %1 = fcmp one float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_ord(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ord:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: feq.s a0, ft0, ft0
+; RV32IF-NEXT: and a0, a0, a1
+; RV32IF-NEXT: sltiu a0, a0, 1
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: bne a0, zero, .LBB8_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: jalr zero, ra, 0
+; RV32IF-NEXT: .LBB8_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr ra, a0, 0
+ %1 = fcmp ord float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_ueq(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ueq:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: feq.s a0, ft1, ft0
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: feq.s a2, ft1, ft1
+; RV32IF-NEXT: and a1, a2, a1
+; RV32IF-NEXT: sltiu a1, a1, 1
+; RV32IF-NEXT: or a0, a0, a1
+; RV32IF-NEXT: bne a0, zero, .LBB9_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: jalr zero, ra, 0
+; RV32IF-NEXT: .LBB9_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr ra, a0, 0
+ %1 = fcmp ueq float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_ugt(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ugt:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: fle.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: bne a0, zero, .LBB10_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: jalr zero, ra, 0
+; RV32IF-NEXT: .LBB10_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr ra, a0, 0
+ %1 = fcmp ugt float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_uge(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_uge:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: flt.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: bne a0, zero, .LBB11_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: jalr zero, ra, 0
+; RV32IF-NEXT: .LBB11_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr ra, a0, 0
+ %1 = fcmp uge float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_ult(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ult:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: fle.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: bne a0, zero, .LBB12_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: jalr zero, ra, 0
+; RV32IF-NEXT: .LBB12_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr ra, a0, 0
+ %1 = fcmp ult float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_ule(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ule:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: flt.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: bne a0, zero, .LBB13_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: jalr zero, ra, 0
+; RV32IF-NEXT: .LBB13_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr ra, a0, 0
+ %1 = fcmp ule float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_une(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_une:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: feq.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: bne a0, zero, .LBB14_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: jalr zero, ra, 0
+; RV32IF-NEXT: .LBB14_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr ra, a0, 0
+ %1 = fcmp une float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_uno(float %a, float %b) nounwind {
+; TODO: sltiu+bne -> beq
+; RV32IF-LABEL: br_fcmp_uno:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: feq.s a0, ft0, ft0
+; RV32IF-NEXT: and a0, a0, a1
+; RV32IF-NEXT: sltiu a0, a0, 1
+; RV32IF-NEXT: bne a0, zero, .LBB15_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: jalr zero, ra, 0
+; RV32IF-NEXT: .LBB15_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr ra, a0, 0
+ %1 = fcmp uno float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_true(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_true:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: addi a0, zero, 1
+; RV32IF-NEXT: bne a0, zero, .LBB16_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: jalr zero, ra, 0
+; RV32IF-NEXT: .LBB16_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr ra, a0, 0
+ %1 = fcmp true float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
diff --git a/test/CodeGen/RISCV/float-fcmp.ll b/test/CodeGen/RISCV/float-fcmp.ll
new file mode 100644
index 00000000000..9c8f1c2d313
--- /dev/null
+++ b/test/CodeGen/RISCV/float-fcmp.ll
@@ -0,0 +1,215 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32IF %s
+
+define i32 @fcmp_false(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_false:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi a0, zero, 0
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp false float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_oeq(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_oeq:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: feq.s a0, ft1, ft0
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp oeq float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ogt(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ogt:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: flt.s a0, ft1, ft0
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp ogt float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_oge(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_oge:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: fle.s a0, ft1, ft0
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp oge float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_olt(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_olt:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: flt.s a0, ft1, ft0
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp olt float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ole(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ole:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: fle.s a0, ft1, ft0
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp ole float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_one(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_one:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: feq.s a0, ft1, ft1
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: and a0, a1, a0
+; RV32IF-NEXT: feq.s a1, ft0, ft1
+; RV32IF-NEXT: xori a1, a1, -1
+; RV32IF-NEXT: sltiu a0, a0, 1
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: and a0, a1, a0
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp one float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ord(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ord:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: feq.s a0, ft0, ft0
+; RV32IF-NEXT: and a0, a0, a1
+; RV32IF-NEXT: sltiu a0, a0, 1
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp ord float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ueq(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ueq:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: feq.s a0, ft1, ft0
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: feq.s a2, ft1, ft1
+; RV32IF-NEXT: and a1, a2, a1
+; RV32IF-NEXT: sltiu a1, a1, 1
+; RV32IF-NEXT: or a0, a0, a1
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp ueq float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ugt(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ugt:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: fle.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp ugt float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_uge(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_uge:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: flt.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp uge float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ult(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ult:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: fle.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp ult float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ule(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ule:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: flt.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp ule float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_une(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_une:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: feq.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp une float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_uno(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_uno:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: feq.s a0, ft0, ft0
+; RV32IF-NEXT: and a0, a0, a1
+; RV32IF-NEXT: sltiu a0, a0, 1
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp uno float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_true(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_true:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi a0, zero, 1
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp true float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
diff --git a/test/CodeGen/RISCV/float-select-fcmp.ll b/test/CodeGen/RISCV/float-select-fcmp.ll
new file mode 100644
index 00000000000..6f979ea8337
--- /dev/null
+++ b/test/CodeGen/RISCV/float-select-fcmp.ll
@@ -0,0 +1,304 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32IF %s
+
+define float @select_fcmp_false(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_false:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi a0, a1, 0
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp false float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_oeq(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_oeq:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: feq.s a0, ft0, ft1
+; RV32IF-NEXT: bne a0, zero, .LBB1_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: fsgnj.s ft0, ft1, ft1
+; RV32IF-NEXT: .LBB1_2:
+; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp oeq float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_ogt(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_ogt:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: flt.s a0, ft1, ft0
+; RV32IF-NEXT: bne a0, zero, .LBB2_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: fsgnj.s ft0, ft1, ft1
+; RV32IF-NEXT: .LBB2_2:
+; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp ogt float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_oge(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_oge:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: fle.s a0, ft1, ft0
+; RV32IF-NEXT: bne a0, zero, .LBB3_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: fsgnj.s ft0, ft1, ft1
+; RV32IF-NEXT: .LBB3_2:
+; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp oge float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_olt(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_olt:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: flt.s a0, ft0, ft1
+; RV32IF-NEXT: bne a0, zero, .LBB4_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: fsgnj.s ft0, ft1, ft1
+; RV32IF-NEXT: .LBB4_2:
+; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp olt float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_ole(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_ole:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fle.s a0, ft0, ft1
+; RV32IF-NEXT: bne a0, zero, .LBB5_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: fsgnj.s ft0, ft1, ft1
+; RV32IF-NEXT: .LBB5_2:
+; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp ole float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_one(float %a, float %b) nounwind {
+; TODO: feq.s+sltiu+bne sequence could be optimised
+; RV32IF-LABEL: select_fcmp_one:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: feq.s a0, ft1, ft1
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: and a0, a1, a0
+; RV32IF-NEXT: feq.s a1, ft0, ft1
+; RV32IF-NEXT: xori a1, a1, -1
+; RV32IF-NEXT: sltiu a0, a0, 1
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: and a0, a1, a0
+; RV32IF-NEXT: bne a0, zero, .LBB6_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: fsgnj.s ft0, ft1, ft1
+; RV32IF-NEXT: .LBB6_2:
+; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: jalr zero, ra, 0
+ %1 = fcmp one float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_ord(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_ord:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: feq.s a0, ft1, ft1