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Commits on Sep 18, 2021

• v1.0.1:

  Show description for 7ae6f80
  ultraembedded

  committed
  7ae6f80

Commits on May 3, 2020

• top_cache_axi: Rebuild for updated core;

  Show description for c17cfba
  ultraembedded

  committed
  c17cfba

Commits on Apr 25, 2020

• core: Add missing file include (stops relying on verilog file ordering).

  ultraembedded

  committed
  480d6d9

Commits on Apr 19, 2020

• Update links in README

  ultraembedded

  committed
  a508bc5

• v1.0

  Show description for fedc9dc
  ultraembedded

  committed
  fedc9dc

Commits on Mar 14, 2020

• Add CSR_SIM_CTRL alias for CSR_SCRATCH. Minor change to allow core to run same SW as biRISC-V

  ultraembedded

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  c3ce172

• Merge branch 'master' of https://github.com/ultraembedded/riscv

  ultraembedded

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  2a8cd88

• Remove RV32IMSU variant as it can no longer boot recent versions of Linux (due to privilege spec). Add link to my newer Linux capable CPU.

  ultraembedded

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  3a296fe

Commits on Feb 10, 2020

• Update README.md

  ultraembedded

  authored
  5af85aa

Commits on Sep 28, 2019

• Revert "Remove use of bfd_check_format_matches() which may not always be available depending on bfd version"

  Show description for 7a469f4
  ultraembedded

  committed
  7a469f4

Commits on Sep 21, 2019

• Add core instance with I & D caches

  ultraembedded

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  fd5abe7

• V0.9.8: Add cache writeback control. Add top level params for cacheable addresses.

  ultraembedded

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  f544799

• Remove use of bfd_check_format_matches() which may not always be available depending on bfd version

  ultraembedded

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  9a4ff4a

Commits on Sep 19, 2019

• Add detection of newer verilator versions

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  980900d

Commits on Aug 11, 2019

• Add another wrapper level for the RISC-V core

  ultraembedded

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  6d5dda3

• Minor fixes to wrapper logic.

  ultraembedded

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  24c0826

• Fix whitespace issues with README

  ultraembedded

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  d75019e

• Updated description of core.

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  05c4c30

Commits on Mar 31, 2019

• Fix rdtime - map to 32-bit cycle counter.

  ultraembedded

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  5ce4718

Commits on Mar 10, 2019

• V0.9.7: Minor cleanup for MMU exceptions

  ultraembedded

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  264e1ae

• V0.9.7: Remaining bug fixes in V0.9.7 for exception handling

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  1bc31c1

• V0.9.7: Bug fix misaligned load/store fault handling

  ultraembedded

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  ea88d6b

Commits on Feb 23, 2019

• Add a few more diagrams

  ultraembedded

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  616a571

• Add overview diagram. Add copy of specs used during implementation

  ultraembedded

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  9a1074c

• Minor interface tweak. Improve verilator based tb.

  ultraembedded

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  743c683

Commits on Feb 19, 2019

• Update readme

  ultraembedded

  committed
  8ece4a2

• Version 0.9.5: Extend exception handling. Add RV32IMSU variant (with very basic MMU).

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  a767060

Commits on Dec 31, 2018

• Version 0.9: Various fixes to CSR support. Improve fetch fault handling.

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  3721ebf

Commits on Dec 9, 2018

• Add prebuilt linux test image. Fix missing lib dep on verilog bench

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  3b00a3a

Commits on Dec 8, 2018

• ISA_SIM: Updated to include working MMU, support for dumping memory post run

  ultraembedded

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  dcccb42

Commits on Dec 5, 2018

• Version 0.8: Rework interrupt support. More bug fixes for exception handling

  ultraembedded

  committed
  ab6984b

Commits on Oct 30, 2018

• Update to v0.7. Interrupt bug fixes. Add multiple versions of the core (RV32I, RV32IM).

  ultraembedded

  committed
  de6868f

Commits on Oct 24, 2018

• Update to next revision of core. Extend from RV32I to RV32IM.

  ultraembedded

  committed
  242e4fd

• Update to next revision of core. Extend from RV32I to RV32IM.

  ultraembedded

  committed
  5947ae0

Commits on Dec 28, 2017

• Add link back

  ultraembedded

  committed
  b259a60

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