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phydm_antdiv.c
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <[email protected]>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <[email protected]>
*
*****************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
/* ******************************************************
* when antenna test utility is on or some testing need to disable antenna diversity
* call this function to disable all ODM related mechanisms which will switch antenna.
* ****************************************************** */
void
odm_stop_antenna_switch_dm(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
/* disable ODM antenna diversity */
dm->support_ability &= ~ODM_BB_ANT_DIV;
odm_ant_div_on_off(dm, ANTDIV_OFF);
odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
PHYDM_DBG(dm, DBG_ANT_DIV, "STOP Antenna Diversity\n");
}
void
phydm_enable_antenna_diversity(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
dm->support_ability |= ODM_BB_ANT_DIV;
dm->antdiv_select = 0;
PHYDM_DBG(dm, DBG_ANT_DIV, "AntDiv is enabled & Re-Init AntDiv\n");
odm_antenna_diversity_init(dm);
}
void
odm_set_ant_config(
void *dm_void,
u8 ant_setting /* 0=A, 1=B, 2=C, .... */
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type == ODM_RTL8723B) {
if (ant_setting == 0) /* ant A*/
odm_set_bb_reg(dm, 0x948, MASKDWORD, 0x00000000);
else if (ant_setting == 1)
odm_set_bb_reg(dm, 0x948, MASKDWORD, 0x00000280);
} else if (dm->support_ic_type == ODM_RTL8723D) {
if (ant_setting == 0) /* ant A*/
odm_set_bb_reg(dm, 0x948, MASKLWORD, 0x0000);
else if (ant_setting == 1)
odm_set_bb_reg(dm, 0x948, MASKLWORD, 0x0280);
}
}
/* ****************************************************** */
void
odm_sw_ant_div_rest_after_link(
void *dm_void
)
{
#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
u32 i;
if (dm->ant_div_type == S0S1_SW_ANTDIV) {
dm_swat_table->try_flag = SWAW_STEP_INIT;
dm_swat_table->rssi_trying = 0;
dm_swat_table->double_chk_flag = 0;
fat_tab->rx_idle_ant = MAIN_ANT;
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
phydm_antdiv_reset_statistic(dm, i);
}
#endif
}
void
odm_ant_div_on_off(
void *dm_void,
u8 swch
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
if (fat_tab->ant_div_on_off != swch) {
if (dm->ant_div_type == S0S1_SW_ANTDIV)
return;
if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
PHYDM_DBG(dm, DBG_ANT_DIV, "(( Turn %s )) N-Series HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF");
odm_set_bb_reg(dm, 0xc50, BIT(7), swch);
odm_set_bb_reg(dm, 0xa00, BIT(15), swch);
#if (RTL8723D_SUPPORT == 1)
/*Mingzhi 2017-05-08*/
if (dm->support_ic_type == ODM_RTL8723D) {
if (swch == ANTDIV_ON) {
odm_set_bb_reg(dm, 0xce0, BIT(1), 1);
odm_set_bb_reg(dm, 0x948, BIT(6), 1); /*1:HW ctrl 0:SW ctrl*/
}
else{
odm_set_bb_reg(dm, 0xce0, BIT(1), 0);
odm_set_bb_reg(dm, 0x948, BIT(6), 0); /*1:HW ctrl 0:SW ctrl*/
}
}
#endif
} else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
PHYDM_DBG(dm, DBG_ANT_DIV, "(( Turn %s )) AC-Series HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF");
if (dm->support_ic_type & ODM_RTL8812) {
odm_set_bb_reg(dm, 0xc50, BIT(7), swch); /* OFDM AntDiv function block enable */
odm_set_bb_reg(dm, 0xa00, BIT(15), swch); /* CCK AntDiv function block enable */
} else {
odm_set_bb_reg(dm, 0x8D4, BIT(24), swch); /* OFDM AntDiv function block enable */
if ((dm->cut_version >= ODM_CUT_C) && (dm->support_ic_type == ODM_RTL8821) && (dm->ant_div_type != S0S1_SW_ANTDIV)) {
PHYDM_DBG(dm, DBG_ANT_DIV, "(( Turn %s )) CCK HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF");
odm_set_bb_reg(dm, 0x800, BIT(25), swch);
odm_set_bb_reg(dm, 0xA00, BIT(15), swch); /* CCK AntDiv function block enable */
} else if (dm->support_ic_type == ODM_RTL8821C) {
PHYDM_DBG(dm, DBG_ANT_DIV, "(( Turn %s )) CCK HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF");
odm_set_bb_reg(dm, 0x800, BIT(25), swch);
odm_set_bb_reg(dm, 0xA00, BIT(15), swch); /* CCK AntDiv function block enable */
}
}
}
}
fat_tab->ant_div_on_off = swch;
}
void
odm_tx_by_tx_desc_or_reg(
void *dm_void,
u8 swch
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
u8 enable;
if (fat_tab->b_fix_tx_ant == NO_FIX_TX_ANT)
enable = (swch == TX_BY_DESC) ? 1 : 0;
else
enable = 0;/*Force TX by Reg*/
if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
odm_set_bb_reg(dm, 0x80c, BIT(21), enable);
else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT)
odm_set_bb_reg(dm, 0x900, BIT(18), enable);
PHYDM_DBG(dm, DBG_ANT_DIV, "[AntDiv] TX_Ant_BY (( %s ))\n", (enable == TX_BY_DESC) ? "DESC" : "REG");
}
}
#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
void
phydm_antdiv_reset_statistic(
void *dm_void,
u32 macid
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
fat_tab->main_ant_sum[macid] = 0;
fat_tab->aux_ant_sum[macid] = 0;
fat_tab->main_ant_cnt[macid] = 0;
fat_tab->aux_ant_cnt[macid] = 0;
fat_tab->main_ant_sum_cck[macid] = 0;
fat_tab->aux_ant_sum_cck[macid] = 0;
fat_tab->main_ant_cnt_cck[macid] = 0;
fat_tab->aux_ant_cnt_cck[macid] = 0;
}
void
phydm_fast_training_enable(
void *dm_void,
u8 swch
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 enable;
if (swch == FAT_ON)
enable = 1;
else
enable = 0;
PHYDM_DBG(dm, DBG_ANT_DIV, "Fast ant Training_en = ((%d))\n", enable);
if (dm->support_ic_type == ODM_RTL8188E) {
odm_set_bb_reg(dm, 0xe08, BIT(16), enable); /*enable fast training*/
/**/
} else if (dm->support_ic_type == ODM_RTL8192E) {
odm_set_bb_reg(dm, 0xB34, BIT(28), enable); /*enable fast training (path-A)*/
/*odm_set_bb_reg(dm, 0xB34, BIT(29), enable);*/ /*enable fast training (path-B)*/
} else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8822B)) {
odm_set_bb_reg(dm, 0x900, BIT(19), enable); /*enable fast training */
/**/
}
}
void
phydm_keep_rx_ack_ant_by_tx_ant_time(
void *dm_void,
u32 time
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
/* Timming issue: keep Rx ant after tx for ACK ( time x 3.2 mu sec)*/
if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
odm_set_bb_reg(dm, 0xE20, BIT(23) | BIT(22) | BIT(21) | BIT(20), time);
/**/
} else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
odm_set_bb_reg(dm, 0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), time);
/**/
}
}
void
odm_update_rx_idle_ant(
void *dm_void,
u8 ant
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
u32 default_ant, optional_ant, value32, default_tx_ant;
if (fat_tab->rx_idle_ant != ant) {
PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] rx_idle_ant =%s\n", (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
if (!(dm->support_ic_type & ODM_RTL8723B))
fat_tab->rx_idle_ant = ant;
if (ant == MAIN_ANT) {
default_ant = ANT1_2G;
optional_ant = ANT2_2G;
} else {
default_ant = ANT2_2G;
optional_ant = ANT1_2G;
}
if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
default_tx_ant = (fat_tab->b_fix_tx_ant == FIX_TX_AT_MAIN) ? 0 : 1;
else
default_tx_ant = default_ant;
if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
if (dm->support_ic_type == ODM_RTL8192E) {
odm_set_bb_reg(dm, 0xB38, BIT(5) | BIT(4) | BIT(3), default_ant); /* Default RX */
odm_set_bb_reg(dm, 0xB38, BIT(8) | BIT(7) | BIT(6), optional_ant); /* Optional RX */
odm_set_bb_reg(dm, 0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /* Default TX */
}
#if (RTL8723B_SUPPORT == 1)
else if (dm->support_ic_type == ODM_RTL8723B) {
value32 = odm_get_bb_reg(dm, 0x948, 0xFFF);
if (value32 != 0x280)
odm_update_rx_idle_ant_8723b(dm, ant, default_ant, optional_ant);
else
PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n");
}
#endif
#if (RTL8723D_SUPPORT == 1) /*Mingzhi 2017-05-08*/
else if (dm->support_ic_type == ODM_RTL8723D) {
phydm_set_tx_ant_pwr_8723d(dm, ant);
odm_update_rx_idle_ant_8723d(dm, ant, default_ant, optional_ant);
}
#endif
else { /*8188E & 8188F*/
/*
if (dm->support_ic_type == ODM_RTL8723D) {
#if (RTL8723D_SUPPORT == 1)
phydm_set_tx_ant_pwr_8723d(dm, ant);
#endif
}
*/
#if (RTL8188F_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8188F) {
phydm_update_rx_idle_antenna_8188F(dm, default_ant);
/**/
}
#endif
odm_set_bb_reg(dm, 0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*Default RX*/
odm_set_bb_reg(dm, 0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/
odm_set_bb_reg(dm, 0x860, BIT(14) | BIT(13) | BIT(12), default_tx_ant); /*Default TX*/
}
} else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
u16 value16 = odm_read_2byte(dm, ODM_REG_TRMUX_11AC + 2);
/* */
/* 2014/01/14 MH/Luke.Lee Add direct write for register 0xc0a to prevnt */
/* incorrect 0xc08 bit0-15 .We still not know why it is changed. */
/* */
value16 &= ~(BIT(11) | BIT(10) | BIT(9) | BIT(8) | BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3));
value16 |= ((u16)default_ant << 3);
value16 |= ((u16)optional_ant << 6);
value16 |= ((u16)default_ant << 9);
odm_write_2byte(dm, ODM_REG_TRMUX_11AC + 2, value16);
#if 0
odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(21) | BIT20 | BIT19, default_ant); /* Default RX */
odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(24) | BIT23 | BIT22, optional_ant); /* Optional RX */
odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(27) | BIT26 | BIT25, default_ant); /* Default TX */
#endif
}
if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A)) {
odm_set_mac_reg(dm, 0x6D8, 0x7, default_tx_ant); /*PathA Resp Tx*/
/**/
} else if (dm->support_ic_type == ODM_RTL8188E) {
odm_set_mac_reg(dm, 0x6D8, BIT(7) | BIT(6), default_tx_ant); /*PathA Resp Tx*/
/**/
} else {
odm_set_mac_reg(dm, 0x6D8, BIT(10) | BIT(9) | BIT(8), default_tx_ant); /*PathA Resp Tx*/
/**/
}
} else { /* fat_tab->rx_idle_ant == ant */
PHYDM_DBG(dm, DBG_ANT_DIV, "[ Stay in Ori-ant ] rx_idle_ant =%s\n", (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
fat_tab->rx_idle_ant = ant;
}
}
void
phydm_set_antdiv_val(
void *dm_void,
u32 *val_buf,
u8 val_len
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (val_len != 1) {
PHYDM_DBG(dm, ODM_COMP_API, "[Error][antdiv]Need val_len=1\n");
return;
}
odm_update_rx_idle_ant(dm, (u8)(*val_buf));
}
void
odm_update_tx_ant(
void *dm_void,
u8 ant,
u32 mac_id
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
u8 tx_ant;
if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
ant = (fat_tab->b_fix_tx_ant == FIX_TX_AT_MAIN) ? MAIN_ANT : AUX_ANT;
if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
tx_ant = ant;
else {
if (ant == MAIN_ANT)
tx_ant = ANT1_2G;
else
tx_ant = ANT2_2G;
}
fat_tab->antsel_a[mac_id] = tx_ant & BIT(0);
fat_tab->antsel_b[mac_id] = (tx_ant & BIT(1)) >> 1;
fat_tab->antsel_c[mac_id] = (tx_ant & BIT(2)) >> 2;
PHYDM_DBG(dm, DBG_ANT_DIV, "[Set TX-DESC value]: mac_id:(( %d )), tx_ant = (( %s ))\n", mac_id, (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
/* PHYDM_DBG(dm,DBG_ANT_DIV,"antsel_tr_mux=(( 3'b%d%d%d ))\n",fat_tab->antsel_c[mac_id] , fat_tab->antsel_b[mac_id] , fat_tab->antsel_a[mac_id] ); */
}
#ifdef BEAMFORMING_SUPPORT
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
void
odm_bdc_init(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
PHYDM_DBG(dm, DBG_ANT_DIV, "\n[ BDC Initialization......]\n");
dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
dm_bdc_table->bdc_mode = BDC_MODE_NULL;
dm_bdc_table->bdc_try_flag = 0;
dm_bdc_table->bd_ccoex_type_wbfer = 0;
dm->bdc_holdstate = 0xff;
if (dm->support_ic_type == ODM_RTL8192E) {
odm_set_bb_reg(dm, 0xd7c, 0x0FFFFFFF, 0x1081008);
odm_set_bb_reg(dm, 0xd80, 0x0FFFFFFF, 0);
} else if (dm->support_ic_type == ODM_RTL8812) {
odm_set_bb_reg(dm, 0x9b0, 0x0FFFFFFF, 0x1081008); /* 0x9b0[30:0] = 01081008 */
odm_set_bb_reg(dm, 0x9b4, 0x0FFFFFFF, 0); /* 0x9b4[31:0] = 00000000 */
}
}
void
odm_CSI_on_off(
void *dm_void,
u8 CSI_en
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (CSI_en == CSI_ON) {
if (dm->support_ic_type == ODM_RTL8192E)
odm_set_mac_reg(dm, 0xd84, BIT(11), 1); /* 0xd84[11]=1 */
else if (dm->support_ic_type == ODM_RTL8812)
odm_set_mac_reg(dm, 0x9b0, BIT(31), 1); /* 0x9b0[31]=1 */
} else if (CSI_en == CSI_OFF) {
if (dm->support_ic_type == ODM_RTL8192E)
odm_set_mac_reg(dm, 0xd84, BIT(11), 0); /* 0xd84[11]=0 */
else if (dm->support_ic_type == ODM_RTL8812)
odm_set_mac_reg(dm, 0x9b0, BIT(31), 0); /* 0x9b0[31]=0 */
}
}
void
odm_bd_ccoex_type_with_bfer_client(
void *dm_void,
u8 swch
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
u8 bd_ccoex_type_wbfer;
if (swch == DIVON_CSIOFF) {
PHYDM_DBG(dm, DBG_ANT_DIV, "[BDCcoexType: 1] {DIV,CSI} ={1,0}\n");
bd_ccoex_type_wbfer = 1;
if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) {
odm_ant_div_on_off(dm, ANTDIV_ON);
odm_CSI_on_off(dm, CSI_OFF);
dm_bdc_table->bd_ccoex_type_wbfer = 1;
}
} else if (swch == DIVOFF_CSION) {
PHYDM_DBG(dm, DBG_ANT_DIV, "[BDCcoexType: 2] {DIV,CSI} ={0,1}\n");
bd_ccoex_type_wbfer = 2;
if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) {
odm_ant_div_on_off(dm, ANTDIV_OFF);
odm_CSI_on_off(dm, CSI_ON);
dm_bdc_table->bd_ccoex_type_wbfer = 2;
}
}
}
void
odm_bf_ant_div_mode_arbitration(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
u8 current_bdc_mode;
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
PHYDM_DBG(dm, DBG_ANT_DIV, "\n");
/* 2 mode 1 */
if ((dm_bdc_table->num_txbfee_client != 0) && (dm_bdc_table->num_txbfer_client == 0)) {
current_bdc_mode = BDC_MODE_1;
if (current_bdc_mode != dm_bdc_table->bdc_mode) {
dm_bdc_table->bdc_mode = BDC_MODE_1;
odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
dm_bdc_table->bdc_rx_idle_update_counter = 1;
PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode1 ))\n");
}
PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv + BF coextance mode] : (( Mode1 ))\n");
}
/* 2 mode 2 */
else if ((dm_bdc_table->num_txbfee_client == 0) && (dm_bdc_table->num_txbfer_client != 0)) {
current_bdc_mode = BDC_MODE_2;
if (current_bdc_mode != dm_bdc_table->bdc_mode) {
dm_bdc_table->bdc_mode = BDC_MODE_2;
dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
dm_bdc_table->bdc_try_flag = 0;
PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode2 ))\n");
}
PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv + BF coextance mode] : (( Mode2 ))\n");
}
/* 2 mode 3 */
else if ((dm_bdc_table->num_txbfee_client != 0) && (dm_bdc_table->num_txbfer_client != 0)) {
current_bdc_mode = BDC_MODE_3;
if (current_bdc_mode != dm_bdc_table->bdc_mode) {
dm_bdc_table->bdc_mode = BDC_MODE_3;
dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
dm_bdc_table->bdc_try_flag = 0;
dm_bdc_table->bdc_rx_idle_update_counter = 1;
PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode3 ))\n");
}
PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv + BF coextance mode] : (( Mode3 ))\n");
}
/* 2 mode 4 */
else if ((dm_bdc_table->num_txbfee_client == 0) && (dm_bdc_table->num_txbfer_client == 0)) {
current_bdc_mode = BDC_MODE_4;
if (current_bdc_mode != dm_bdc_table->bdc_mode) {
dm_bdc_table->bdc_mode = BDC_MODE_4;
odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode4 ))\n");
}
PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv + BF coextance mode] : (( Mode4 ))\n");
}
#endif
}
void
odm_div_train_state_setting(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
PHYDM_DBG(dm, DBG_ANT_DIV, "\n*****[S T A R T ]***** [2-0. DIV_TRAIN_STATE]\n");
dm_bdc_table->bdc_try_counter = 2;
dm_bdc_table->bdc_try_flag = 1;
dm_bdc_table->BDC_state = bdc_bfer_train_state;
odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
}
void
odm_bd_ccoex_bfee_rx_div_arbitration(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
boolean stop_bf_flag;
u8 bdc_active_mode;
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
PHYDM_DBG(dm, DBG_ANT_DIV, "***{ num_BFee, num_BFer, num_client} = (( %d , %d , %d))\n", dm_bdc_table->num_txbfee_client, dm_bdc_table->num_txbfer_client, dm_bdc_table->num_client);
PHYDM_DBG(dm, DBG_ANT_DIV, "***{ num_BF_tars, num_DIV_tars } = (( %d , %d ))\n", dm_bdc_table->num_bf_tar, dm_bdc_table->num_div_tar);
/* 2 [ MIB control ] */
if (dm->bdc_holdstate == 2) {
odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ BF STATE]\n");
return;
} else if (dm->bdc_holdstate == 1) {
dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n");
return;
}
/* ------------------------------------------------------------ */
/* 2 mode 2 & 3 */
if (dm_bdc_table->bdc_mode == BDC_MODE_2 || dm_bdc_table->bdc_mode == BDC_MODE_3) {
PHYDM_DBG(dm, DBG_ANT_DIV, "\n{ Try_flag, Try_counter } = { %d , %d }\n", dm_bdc_table->bdc_try_flag, dm_bdc_table->bdc_try_counter);
PHYDM_DBG(dm, DBG_ANT_DIV, "BDCcoexType = (( %d ))\n\n", dm_bdc_table->bd_ccoex_type_wbfer);
/* All Client have Bfer-Cap------------------------------- */
if (dm_bdc_table->num_txbfer_client == dm_bdc_table->num_client) { /* BFer STA Only?: yes */
PHYDM_DBG(dm, DBG_ANT_DIV, "BFer STA only? (( Yes ))\n");
dm_bdc_table->bdc_try_flag = 0;
dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
return;
} else
PHYDM_DBG(dm, DBG_ANT_DIV, "BFer STA only? (( No ))\n");
/* */
if (dm_bdc_table->is_all_bf_sta_idle == false && dm_bdc_table->is_all_div_sta_idle == true) {
PHYDM_DBG(dm, DBG_ANT_DIV, "All DIV-STA are idle, but BF-STA not\n");
dm_bdc_table->bdc_try_flag = 0;
dm_bdc_table->BDC_state = bdc_bfer_train_state;
odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
return;
} else if (dm_bdc_table->is_all_bf_sta_idle == true && dm_bdc_table->is_all_div_sta_idle == false) {
PHYDM_DBG(dm, DBG_ANT_DIV, "All BF-STA are idle, but DIV-STA not\n");
dm_bdc_table->bdc_try_flag = 0;
dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
return;
}
/* Select active mode-------------------------------------- */
if (dm_bdc_table->num_bf_tar == 0) { /* Selsect_1, Selsect_2 */
if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */
PHYDM_DBG(dm, DBG_ANT_DIV, "Select active mode (( 1 ))\n");
dm_bdc_table->bdc_active_mode = 1;
} else {
PHYDM_DBG(dm, DBG_ANT_DIV, "Select active mode (( 2 ))\n");
dm_bdc_table->bdc_active_mode = 2;
}
dm_bdc_table->bdc_try_flag = 0;
dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
return;
} else { /* num_bf_tar > 0 */
if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */
PHYDM_DBG(dm, DBG_ANT_DIV, "Select active mode (( 3 ))\n");
dm_bdc_table->bdc_active_mode = 3;
dm_bdc_table->bdc_try_flag = 0;
dm_bdc_table->BDC_state = bdc_bfer_train_state;
odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
return;
} else { /* Selsect_4 */
bdc_active_mode = 4;
PHYDM_DBG(dm, DBG_ANT_DIV, "Select active mode (( 4 ))\n");
if (bdc_active_mode != dm_bdc_table->bdc_active_mode) {
dm_bdc_table->bdc_active_mode = 4;
PHYDM_DBG(dm, DBG_ANT_DIV, "Change to active mode (( 4 )) & return!!!\n");
return;
}
}
}
#if 1
if (dm->bdc_holdstate == 0xff) {
dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n");
return;
}
#endif
/* Does Client number changed ? ------------------------------- */
if (dm_bdc_table->num_client != dm_bdc_table->pre_num_client) {
dm_bdc_table->bdc_try_flag = 0;
dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
PHYDM_DBG(dm, DBG_ANT_DIV, "[ The number of client has been changed !!!] return to (( BDC_DIV_TRAIN_STATE ))\n");
}
dm_bdc_table->pre_num_client = dm_bdc_table->num_client;
if (dm_bdc_table->bdc_try_flag == 0) {
/* 2 DIV_TRAIN_STATE (mode 2-0) */
if (dm_bdc_table->BDC_state == BDC_DIV_TRAIN_STATE)
odm_div_train_state_setting(dm);
/* 2 BFer_TRAIN_STATE (mode 2-1) */
else if (dm_bdc_table->BDC_state == bdc_bfer_train_state) {
PHYDM_DBG(dm, DBG_ANT_DIV, "*****[2-1. BFer_TRAIN_STATE ]*****\n");
/* if(dm_bdc_table->num_bf_tar==0) */
/* { */
/* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( No )), [ bdc_bfer_train_state ] >> [BDC_DIV_TRAIN_STATE]\n"); */
/* odm_div_train_state_setting( dm); */
/* } */
/* else */ /* num_bf_tar != 0 */
/* { */
dm_bdc_table->bdc_try_counter = 2;
dm_bdc_table->bdc_try_flag = 1;
dm_bdc_table->BDC_state = BDC_DECISION_STATE;
odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
PHYDM_DBG(dm, DBG_ANT_DIV, "BF_tars exist? : (( Yes )), [ bdc_bfer_train_state ] >> [BDC_DECISION_STATE]\n");
/* } */
}
/* 2 DECISION_STATE (mode 2-2) */
else if (dm_bdc_table->BDC_state == BDC_DECISION_STATE) {
PHYDM_DBG(dm, DBG_ANT_DIV, "*****[2-2. DECISION_STATE]*****\n");
/* if(dm_bdc_table->num_bf_tar==0) */
/* { */
/* ODM_AntDiv_Printk(("BF_tars exist? : (( No )), [ DECISION_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); */
/* odm_div_train_state_setting( dm); */
/* } */
/* else */ /* num_bf_tar != 0 */
/* { */
if (dm_bdc_table->BF_pass == false || dm_bdc_table->DIV_pass == false)
stop_bf_flag = true;
else
stop_bf_flag = false;
PHYDM_DBG(dm, DBG_ANT_DIV, "BF_tars exist? : (( Yes )), {BF_pass, DIV_pass, stop_bf_flag } = { %d, %d, %d }\n", dm_bdc_table->BF_pass, dm_bdc_table->DIV_pass, stop_bf_flag);
if (stop_bf_flag == true) { /* DIV_en */
dm_bdc_table->bdc_hold_counter = 10; /* 20 */
odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
PHYDM_DBG(dm, DBG_ANT_DIV, "[ stop_bf_flag= ((true)), BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE]\n");
} else { /* BF_en */
dm_bdc_table->bdc_hold_counter = 10; /* 20 */
odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
PHYDM_DBG(dm, DBG_ANT_DIV, "[stop_bf_flag= ((false)), BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE]\n");
}
/* } */
}
/* 2 BF-HOLD_STATE (mode 2-3) */
else if (dm_bdc_table->BDC_state == BDC_BF_HOLD_STATE) {
PHYDM_DBG(dm, DBG_ANT_DIV, "*****[2-3. BF_HOLD_STATE ]*****\n");
PHYDM_DBG(dm, DBG_ANT_DIV, "bdc_hold_counter = (( %d ))\n", dm_bdc_table->bdc_hold_counter);
if (dm_bdc_table->bdc_hold_counter == 1) {
PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n");
odm_div_train_state_setting(dm);
} else {
dm_bdc_table->bdc_hold_counter--;
/* if(dm_bdc_table->num_bf_tar==0) */
/* { */
/* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( No )), [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n"); */
/* odm_div_train_state_setting( dm); */
/* } */
/* else */ /* num_bf_tar != 0 */
/* { */
/* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( Yes ))\n"); */
dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE]\n");
/* } */
}
}
/* 2 DIV-HOLD_STATE (mode 2-4) */
else if (dm_bdc_table->BDC_state == BDC_DIV_HOLD_STATE) {
PHYDM_DBG(dm, DBG_ANT_DIV, "*****[2-4. DIV_HOLD_STATE ]*****\n");
PHYDM_DBG(dm, DBG_ANT_DIV, "bdc_hold_counter = (( %d ))\n", dm_bdc_table->bdc_hold_counter);
if (dm_bdc_table->bdc_hold_counter == 1) {
PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n");
odm_div_train_state_setting(dm);
} else {
dm_bdc_table->bdc_hold_counter--;
dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE]\n");
}
}
} else if (dm_bdc_table->bdc_try_flag == 1) {
/* 2 Set Training counter */
if (dm_bdc_table->bdc_try_counter > 1) {
dm_bdc_table->bdc_try_counter--;
if (dm_bdc_table->bdc_try_counter == 1)
dm_bdc_table->bdc_try_flag = 0;
PHYDM_DBG(dm, DBG_ANT_DIV, "Training !!\n");
/* return ; */
}
}
}
PHYDM_DBG(dm, DBG_ANT_DIV, "\n[end]\n");
#endif /* #if(DM_ODM_SUPPORT_TYPE == ODM_AP) */
}
#endif
#endif /* #ifdef BEAMFORMING_SUPPORT */
#if (RTL8188E_SUPPORT == 1)
void
odm_rx_hw_ant_div_init_88e(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 value32;
struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
#if 0
if (*(dm->mp_mode) == true) {
odm_set_bb_reg(dm, ODM_REG_IGI_A_11N, BIT(7), 0); /* disable HW AntDiv */
odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* 1:CG, 0:CS */
return;
}
#endif
PHYDM_DBG(dm, DBG_ANT_DIV, "***8188E AntDiv_Init => ant_div_type=[CGCS_RX_HW_ANTDIV]\n");
/* MAC setting */
value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD);
odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
/* Pin Settings */
odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */
odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */
odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */
odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* regb2c[31]=1'b1 */ /* output at CG only */
/* OFDM Settings */
odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
/* CCK Settings */
odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */
odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0001); /* antenna mapping table */
fat_tab->enable_ctrl_frame_antdiv = 1;
}
void
odm_trx_hw_ant_div_init_88e(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 value32;
struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
#if 0
if (*(dm->mp_mode) == true) {
odm_set_bb_reg(dm, ODM_REG_IGI_A_11N, BIT(7), 0); /* disable HW AntDiv */
odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT4 | BIT3, 0); /* Default RX (0/1) */
return;
}
#endif
PHYDM_DBG(dm, DBG_ANT_DIV, "***8188E AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV (SPDT)]\n");
/* MAC setting */
value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD);
odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
/* Pin Settings */
odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */
odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */
odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 0); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */
odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* regb2c[31]=1'b1 */ /* output at CG only */
/* OFDM Settings */
odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
/* CCK Settings */
odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */
odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
/* antenna mapping table */
if (!dm->is_mp_chip) { /* testchip */
odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
} else /* MPchip */
odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, MASKDWORD, 0x0201); /*Reg914=3'b010, Reg915=3'b001*/
fat_tab->enable_ctrl_frame_antdiv = 1;
}
#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
void
odm_smart_hw_ant_div_init_88e(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 value32, i;
struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
PHYDM_DBG(dm, DBG_ANT_DIV, "***8188E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n");
#if 0
if (*(dm->mp_mode) == true) {
PHYDM_DBG(dm, ODM_COMP_INIT, "dm->ant_div_type: %d\n", dm->ant_div_type);
return;
}
#endif
fat_tab->train_idx = 0;
fat_tab->fat_state = FAT_PREPARE_STATE;
dm->fat_comb_a = 5;
dm->antdiv_intvl = 0x64; /* 100ms */
for (i = 0; i < 6; i++)
fat_tab->bssid[i] = 0;
for (i = 0; i < (dm->fat_comb_a) ; i++) {
fat_tab->ant_sum_rssi[i] = 0;
fat_tab->ant_rssi_cnt[i] = 0;
fat_tab->ant_ave_rssi[i] = 0;
}
/* MAC setting */
value32 = odm_get_mac_reg(dm, 0x4c, MASKDWORD);
odm_set_mac_reg(dm, 0x4c, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
value32 = odm_get_mac_reg(dm, 0x7B4, MASKDWORD);
odm_set_mac_reg(dm, 0x7b4, MASKDWORD, value32 | (BIT(16) | BIT(17))); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */
/* value32 = platform_efio_read_4byte(adapter, 0x7B4); */
/* platform_efio_write_4byte(adapter, 0x7b4, value32|BIT(18)); */ /* append MACID in reponse packet */
/* Match MAC ADDR */
odm_set_mac_reg(dm, 0x7b4, 0xFFFF, 0);
odm_set_mac_reg(dm, 0x7b0, MASKDWORD, 0);
odm_set_bb_reg(dm, 0x870, BIT(9) | BIT(8), 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */
odm_set_bb_reg(dm, 0x864, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */
odm_set_bb_reg(dm, 0xb2c, BIT(22), 0); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */
odm_set_bb_reg(dm, 0xb2c, BIT(31), 0); /* regb2c[31]=1'b1 */ /* output at CS only */
odm_set_bb_reg(dm, 0xca4, MASKDWORD, 0x000000a0);
/* antenna mapping table */
if (dm->fat_comb_a == 2) {
if (!dm->is_mp_chip) { /* testchip */
odm_set_bb_reg(dm, 0x858, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
odm_set_bb_reg(dm, 0x858, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
} else { /* MPchip */
odm_set_bb_reg(dm, 0x914, MASKBYTE0, 1);
odm_set_bb_reg(dm, 0x914, MASKBYTE1, 2);
}
} else {
if (!dm->is_mp_chip) { /* testchip */
odm_set_bb_reg(dm, 0x858, BIT(10) | BIT(9) | BIT(8), 0); /* Reg858[10:8]=3'b000 */
odm_set_bb_reg(dm, 0x858, BIT(13) | BIT(12) | BIT(11), 1); /* Reg858[13:11]=3'b001 */
odm_set_bb_reg(dm, 0x878, BIT(16), 0);
odm_set_bb_reg(dm, 0x858, BIT(15) | BIT(14), 2); /* (Reg878[0],Reg858[14:15])=3'b010 */
odm_set_bb_reg(dm, 0x878, BIT(19) | BIT(18) | BIT(17), 3); /* Reg878[3:1]=3b'011 */
odm_set_bb_reg(dm, 0x878, BIT(22) | BIT(21) | BIT(20), 4); /* Reg878[6:4]=3b'100 */
odm_set_bb_reg(dm, 0x878, BIT(25) | BIT(24) | BIT(23), 5); /* Reg878[9:7]=3b'101 */
odm_set_bb_reg(dm, 0x878, BIT(28) | BIT(27) | BIT(26), 6); /* Reg878[12:10]=3b'110 */
odm_set_bb_reg(dm, 0x878, BIT(31) | BIT(30) | BIT(29), 7); /* Reg878[15:13]=3b'111 */
} else { /* MPchip */
odm_set_bb_reg(dm, 0x914, MASKBYTE0, 4); /* 0: 3b'000 */
odm_set_bb_reg(dm, 0x914, MASKBYTE1, 2); /* 1: 3b'001 */
odm_set_bb_reg(dm, 0x914, MASKBYTE2, 0); /* 2: 3b'010 */
odm_set_bb_reg(dm, 0x914, MASKBYTE3, 1); /* 3: 3b'011 */
odm_set_bb_reg(dm, 0x918, MASKBYTE0, 3); /* 4: 3b'100 */
odm_set_bb_reg(dm, 0x918, MASKBYTE1, 5); /* 5: 3b'101 */
odm_set_bb_reg(dm, 0x918, MASKBYTE2, 6); /* 6: 3b'110 */
odm_set_bb_reg(dm, 0x918, MASKBYTE3, 255); /* 7: 3b'111 */
}
}
/* Default ant setting when no fast training */
odm_set_bb_reg(dm, 0x864, BIT(5) | BIT(4) | BIT(3), 0); /* Default RX */
odm_set_bb_reg(dm, 0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Optional RX */
odm_set_bb_reg(dm, 0x860, BIT(14) | BIT(13) | BIT(12), 0); /* Default TX */
/* Enter Traing state */
odm_set_bb_reg(dm, 0x864, BIT(2) | BIT(1) | BIT(0), (dm->fat_comb_a - 1)); /* reg864[2:0]=3'd6 */ /* ant combination=reg864[2:0]+1 */
/* SW Control */
/* phy_set_bb_reg(adapter, 0x864, BIT10, 1); */
/* phy_set_bb_reg(adapter, 0x870, BIT9, 1); */
/* phy_set_bb_reg(adapter, 0x870, BIT8, 1); */
/* phy_set_bb_reg(adapter, 0x864, BIT11, 1); */
/* phy_set_bb_reg(adapter, 0x860, BIT9, 0); */
/* phy_set_bb_reg(adapter, 0x860, BIT8, 0); */
}