PicoRV32 - A Size-Optimized RISC-V CPU

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

IC design and development should be faster，simpler and more reliable

RTL, Cmodel, and testbench for NVDLA

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

SERV - The SErial RISC-V CPU

OpenXuantie - OpenC910 Core

Verilog PCI express components

An open source GPU based off of the AMD Southern Islands ISA.

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

32-bit Superscalar RISC-V CPU

3-stage RV32IMACZb* processor with debug

Various HDL (Verilog) IP Cores

A tiny Open POWER ISA softcore written in VHDL 2008

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

RISC-V Formal Verification Framework

Open source retro ISA video card

mor1kx - an OpenRISC 1000 processor IP core

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

Bus bridges and other odds and ends

VRoom! RISC-V CPU

Volumetric Display using an Acoustically Trapped Particle

Board designs, FPGA verilog, firmware for TKey, the flexible and open USB security key 🔑

iCESugar FPGA Board (base on iCE40UP5k)

current focus on Colorlight i5 and i9 & i9plus module

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

iCESugar series FPGA dev board

Support files for participating in a Fomu workshop