axi4stream_sinker.v

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module axi4stream_sinker #(
    parameter C_AXI_TDATA_WIDTH = 512
) (
    input  wire                               CLK          , // Clock
    input  wire                               RST_N        , // Rst (active low level)
    input  wire  [C_AXI_TDATA_WIDTH-1:0]      S_AXIS_TDATA ,
    input  wire                               S_AXIS_TLAST ,
    input  wire  [(C_AXI_TDATA_WIDTH/8)-1:0]  S_AXIS_TKEEP ,
    input  wire                               S_AXIS_TVALID,
    output  wire                              S_AXIS_TREADY
);
    assign S_AXIS_TREADY = 1'b1;

endmodule