ossc_pro.qsf

# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
# Date created = 11:23:54  September 01, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		ossc_pro_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CEFA5F23I7
set_global_assignment -name TOP_LEVEL_ENTITY ossc_pro
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:23:54  SEPTEMBER 01, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "23.1std.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name GENERATE_TTF_FILE ON
set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name IO_STANDARD "1.2 V" -to CLK27_i
set_instance_assignment -name IO_STANDARD "1.2 V" -to LED_o[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to LED_o[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to LED_o[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HDMI_INT_N_i
set_instance_assignment -name IO_STANDARD "1.2 V" -to FAN_PWM_o
set_instance_assignment -name IO_STANDARD "1.2 V" -to SI_INT_N_i
set_instance_assignment -name IO_STANDARD "1.2 V" -to LS_DIR_o[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to LS_DIR_o[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[4]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[5]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[6]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[7]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[8]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[9]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[10]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[11]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[12]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[13]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[14]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[15]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[16]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[17]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[18]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[19]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[20]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[21]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[22]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[23]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[24]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[25]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[26]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[27]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[28]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[29]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[30]
set_instance_assignment -name IO_STANDARD "1.2 V" -to EXT_IO_B_io[31]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HDMIRX_R_i
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HDMIRX_G_i
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HDMIRX_B_i
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HDMIRX_HSYNC_i
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HDMIRX_VSYNC_i
set_instance_assignment -name FAST_INPUT_REGISTER ON -to HDMIRX_DE_i
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMITX_R_o
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMITX_G_o
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMITX_B_o
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMITX_HSYNC_o
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMITX_VSYNC_o
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMITX_DE_o
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[13]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[14]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[15]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[16]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[17]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[18]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[19]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[20]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[21]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[22]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[23]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[24]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[25]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[26]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[27]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[28]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[29]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[30]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to EXT_IO_B_io[31]
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCQ128
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_pro_sdp.stp
set_global_assignment -name GENERATE_RBF_FILE ON


set_global_assignment -name OPTIMIZATION_MODE BALANCED

#memory stuff here

set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name ECO_REGENERATE_REPORT ON
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tbench -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME tbench -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tbench
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tbench -section_id tbench
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "3 ms" -section_id tbench
set_global_assignment -name EDA_TEST_BENCH_FILE rtl/tb/tbench.sv -section_id tbench
set_global_assignment -name EDA_TEST_BENCH_FILE rtl/tb/lpddr2model/mobile_ddr2.v -section_id tbench


set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"


set_location_assignment PIN_T19 -to AUDMUX_o
set_location_assignment PIN_V14 -to BTN_i[5]
set_location_assignment PIN_N9 -to BTN_i[4]
set_location_assignment PIN_U20 -to BTN_i[3]
set_location_assignment PIN_U17 -to BTN_i[2]
set_location_assignment PIN_AA12 -to BTN_i[1]
set_location_assignment PIN_P7 -to BTN_i[0]
set_location_assignment PIN_H16 -to CLK27_i
set_location_assignment PIN_H6 -to EXT_IO_B_io[31]
set_location_assignment PIN_F7 -to EXT_IO_B_io[30]
set_location_assignment PIN_G6 -to EXT_IO_B_io[29]
set_location_assignment PIN_C8 -to EXT_IO_B_io[28]
set_location_assignment PIN_D7 -to EXT_IO_B_io[27]
set_location_assignment PIN_D6 -to EXT_IO_B_io[26]
set_location_assignment PIN_C6 -to EXT_IO_B_io[25]
set_location_assignment PIN_B7 -to EXT_IO_B_io[24]
set_location_assignment PIN_B6 -to EXT_IO_B_io[23]
set_location_assignment PIN_C9 -to EXT_IO_B_io[22]
set_location_assignment PIN_A5 -to EXT_IO_B_io[21]
set_location_assignment PIN_B10 -to EXT_IO_B_io[20]
set_location_assignment PIN_F10 -to EXT_IO_B_io[19]
set_location_assignment PIN_G10 -to EXT_IO_B_io[18]
set_location_assignment PIN_F9 -to EXT_IO_B_io[17]
set_location_assignment PIN_E10 -to EXT_IO_B_io[16]
set_location_assignment PIN_F22 -to EXT_IO_B_io[15]
set_location_assignment PIN_B21 -to EXT_IO_B_io[14]
set_location_assignment PIN_G22 -to EXT_IO_B_io[13]
set_location_assignment PIN_C21 -to EXT_IO_B_io[12]
set_location_assignment PIN_B17 -to EXT_IO_B_io[11]
set_location_assignment PIN_J22 -to EXT_IO_B_io[10]
set_location_assignment PIN_B18 -to EXT_IO_B_io[9]
set_location_assignment PIN_J21 -to EXT_IO_B_io[8]
set_location_assignment PIN_B20 -to EXT_IO_B_io[7]
set_location_assignment PIN_D19 -to EXT_IO_B_io[6]
set_location_assignment PIN_C20 -to EXT_IO_B_io[5]
set_location_assignment PIN_E19 -to EXT_IO_B_io[4]
set_location_assignment PIN_D21 -to EXT_IO_B_io[3]
set_location_assignment PIN_G21 -to EXT_IO_B_io[2]
set_location_assignment PIN_E21 -to EXT_IO_B_io[1]
set_location_assignment PIN_H21 -to EXT_IO_B_io[0]
set_location_assignment PIN_U21 -to EXT_IO_A_io[5]
set_location_assignment PIN_U16 -to EXT_IO_A_io[4]
set_location_assignment PIN_V18 -to EXT_IO_A_io[3]
set_location_assignment PIN_V21 -to EXT_IO_A_io[2]
set_location_assignment PIN_V16 -to EXT_IO_A_io[1]
set_location_assignment PIN_W16 -to EXT_IO_A_io[0]
set_location_assignment PIN_AB11 -to FPGA_PCLK1x_o
set_location_assignment PIN_Y20 -to HDMIRX_AP_i
set_location_assignment PIN_AB15 -to HDMIRX_B_i[7]
set_location_assignment PIN_AA13 -to HDMIRX_B_i[6]
set_location_assignment PIN_T13 -to HDMIRX_B_i[5]
set_location_assignment PIN_AA14 -to HDMIRX_B_i[4]
set_location_assignment PIN_T12 -to HDMIRX_B_i[3]
set_location_assignment PIN_U13 -to HDMIRX_B_i[2]
set_location_assignment PIN_AB12 -to HDMIRX_B_i[1]
set_location_assignment PIN_V13 -to HDMIRX_B_i[0]
set_location_assignment PIN_AA22 -to HDMIRX_DE_i
set_location_assignment PIN_AB21 -to HDMIRX_G_i[7]
set_location_assignment PIN_Y16 -to HDMIRX_G_i[6]
set_location_assignment PIN_AB20 -to HDMIRX_G_i[5]
set_location_assignment PIN_AB18 -to HDMIRX_G_i[4]
set_location_assignment PIN_AB17 -to HDMIRX_G_i[3]
set_location_assignment PIN_Y15 -to HDMIRX_G_i[2]
set_location_assignment PIN_AA15 -to HDMIRX_G_i[1]
set_location_assignment PIN_Y14 -to HDMIRX_G_i[0]
set_location_assignment PIN_W19 -to HDMIRX_HSYNC_i
set_location_assignment PIN_Y19 -to HDMIRX_I2S_BCK_i
set_location_assignment PIN_W22 -to HDMIRX_I2S_WS_i
set_location_assignment PIN_L8 -to HDMI_INT_N_i
set_location_assignment PIN_V15 -to HDMIRX_PCLK_i
set_location_assignment PIN_Y22 -to HDMIRX_RESET_N_o
set_location_assignment PIN_AA20 -to HDMIRX_R_i[7]
set_location_assignment PIN_V20 -to HDMIRX_R_i[6]
set_location_assignment PIN_AA19 -to HDMIRX_R_i[5]
set_location_assignment PIN_AA18 -to HDMIRX_R_i[4]
set_location_assignment PIN_U15 -to HDMIRX_R_i[3]
set_location_assignment PIN_AA17 -to HDMIRX_R_i[2]
set_location_assignment PIN_T14 -to HDMIRX_R_i[1]
set_location_assignment PIN_Y17 -to HDMIRX_R_i[0]
set_location_assignment PIN_AB22 -to HDMIRX_VSYNC_i
set_location_assignment PIN_L19 -to HDMITX_B_o[7]
set_location_assignment PIN_K21 -to HDMITX_B_o[6]
set_location_assignment PIN_L18 -to HDMITX_B_o[5]
set_location_assignment PIN_K22 -to HDMITX_B_o[4]
set_location_assignment PIN_T22 -to HDMITX_B_o[3]
set_location_assignment PIN_R22 -to HDMITX_B_o[2]
set_location_assignment PIN_R21 -to HDMITX_B_o[1]
set_location_assignment PIN_P22 -to HDMITX_B_o[0]
set_location_assignment PIN_T17 -to HDMITX_DE_o
set_location_assignment PIN_N20 -to HDMITX_G_o[7]
set_location_assignment PIN_N21 -to HDMITX_G_o[6]
set_location_assignment PIN_N19 -to HDMITX_G_o[5]
set_location_assignment PIN_M18 -to HDMITX_G_o[4]
set_location_assignment PIN_K17 -to HDMITX_G_o[3]
set_location_assignment PIN_M20 -to HDMITX_G_o[2]
set_location_assignment PIN_L17 -to HDMITX_G_o[1]
set_location_assignment PIN_M21 -to HDMITX_G_o[0]
set_location_assignment PIN_T18 -to HDMITX_HSYNC_o
set_location_assignment PIN_U22 -to HDMITX_I2S_BCK_o
set_location_assignment PIN_R14 -to HDMITX_I2S_DATA_o
set_location_assignment PIN_W21 -to HDMITX_I2S_WS_o
set_location_assignment PIN_M22 -to HDMITX_PCLK_o
set_location_assignment PIN_T15 -to HDMITX_R_o[7]
set_location_assignment PIN_R15 -to HDMITX_R_o[6]
set_location_assignment PIN_R16 -to HDMITX_R_o[5]
set_location_assignment PIN_R17 -to HDMITX_R_o[4]
set_location_assignment PIN_P19 -to HDMITX_R_o[3]
set_location_assignment PIN_P16 -to HDMITX_R_o[2]
set_location_assignment PIN_P18 -to HDMITX_R_o[1]
set_location_assignment PIN_P17 -to HDMITX_R_o[0]
set_location_assignment PIN_V19 -to HDMITX_SPDIF_o
set_location_assignment PIN_T20 -to HDMITX_VSYNC_o
set_location_assignment PIN_L22 -to HDMITX_5V_EN_o
set_location_assignment PIN_A12 -to FAN_PWM_o
set_location_assignment PIN_P9 -to IR_RX_i
set_location_assignment PIN_Y9 -to ISL_B_i[7]
set_location_assignment PIN_R9 -to ISL_B_i[6]
set_location_assignment PIN_U11 -to ISL_B_i[5]
set_location_assignment PIN_R12 -to ISL_B_i[4]
set_location_assignment PIN_U12 -to ISL_B_i[3]
set_location_assignment PIN_P12 -to ISL_B_i[2]
set_location_assignment PIN_R10 -to ISL_B_i[1]
set_location_assignment PIN_R11 -to ISL_B_i[0]
set_location_assignment PIN_R5 -to ISL_VSYNC_i
set_location_assignment PIN_AB10 -to ISL_EXT_PCLK_o
set_location_assignment PIN_AA8 -to ISL_G_i[7]
set_location_assignment PIN_T9 -to ISL_G_i[6]
set_location_assignment PIN_AB8 -to ISL_G_i[5]
set_location_assignment PIN_U10 -to ISL_G_i[4]
set_location_assignment PIN_AA10 -to ISL_G_i[3]
set_location_assignment PIN_AA9 -to ISL_G_i[2]
set_location_assignment PIN_Y10 -to ISL_G_i[1]
set_location_assignment PIN_T10 -to ISL_G_i[0]
set_location_assignment PIN_R6 -to ISL_HSYNC_i
set_location_assignment PIN_Y11 -to ISL_HS_i
set_location_assignment PIN_W8 -to ISL_INT_N_i
set_location_assignment PIN_M9 -to ISL_PCLK_i
set_location_assignment PIN_P6 -to ISL_RESET_N_o
set_location_assignment PIN_AB6 -to ISL_R_i[7]
set_location_assignment PIN_V9 -to ISL_R_i[6]
set_location_assignment PIN_AB5 -to ISL_R_i[5]
set_location_assignment PIN_V10 -to ISL_R_i[4]
set_location_assignment PIN_P8 -to ISL_R_i[3]
set_location_assignment PIN_AA7 -to ISL_R_i[2]
set_location_assignment PIN_N8 -to ISL_R_i[1]
set_location_assignment PIN_AB7 -to ISL_R_i[0]
set_location_assignment PIN_U8 -to USB_DP_io
set_location_assignment PIN_U7 -to USB_DN_io
set_location_assignment PIN_G13 -to LED_o[2]
set_location_assignment PIN_H13 -to LED_o[1]
set_location_assignment PIN_H15 -to LED_o[0]
set_location_assignment PIN_D9 -to LS_DIR_o[1]
set_location_assignment PIN_B13 -to LS_DIR_o[0]
set_location_assignment PIN_M6 -to PCM_I2S_BCK_i
set_location_assignment PIN_M7 -to PCM_I2S_DATA_i
set_location_assignment PIN_R7 -to PCM_I2S_WS_i
set_location_assignment PIN_P14 -to SCL_io
set_location_assignment PIN_Y21 -to SDA_io
set_location_assignment PIN_N6 -to SD_CLK_o
set_location_assignment PIN_W9 -to SD_CMD_io
set_location_assignment PIN_T8 -to SD_DATA_io[3]
set_location_assignment PIN_V6 -to SD_DATA_io[2]
set_location_assignment PIN_U6 -to SD_DATA_io[1]
set_location_assignment PIN_T7 -to SD_DATA_io[0]
set_location_assignment PIN_AB13 -to SD_DETECT_i
set_location_assignment PIN_M16 -to SI_CLK_EXTRA_i
set_location_assignment PIN_J19 -to SI_INT_N_i
set_location_assignment PIN_N16 -to SI_PCLK_i
set_location_assignment PIN_M8 -to SPDIF_EXT_i
set_location_assignment PIN_B11 -to DDR_RZQ_i
set_location_assignment PIN_A7 -to DDR_CA_o[9]
set_location_assignment PIN_A8 -to DDR_CA_o[8]
set_location_assignment PIN_A9 -to DDR_CA_o[7]
set_location_assignment PIN_A10 -to DDR_CA_o[6]
set_location_assignment PIN_J8 -to DDR_CA_o[5]
set_location_assignment PIN_J7 -to DDR_CA_o[4]
set_location_assignment PIN_G8 -to DDR_CA_o[3]
set_location_assignment PIN_H8 -to DDR_CA_o[2]
set_location_assignment PIN_K7 -to DDR_CA_o[1]
set_location_assignment PIN_L7 -to DDR_CA_o[0]
set_location_assignment PIN_F14 -to DDR_CKE_o
set_location_assignment PIN_J9 -to DDR_CK_o_p
set_location_assignment PIN_H9 -to DDR_CK_o_n
set_location_assignment PIN_E9 -to DDR_CS_N_o
set_location_assignment PIN_E22 -to DDR_DM_o[3]
set_location_assignment PIN_B16 -to DDR_DM_o[2]
set_location_assignment PIN_J17 -to DDR_DM_o[1]
set_location_assignment PIN_G11 -to DDR_DM_o[0]
set_location_assignment PIN_D22 -to DDR_DQ_io[31]
set_location_assignment PIN_B22 -to DDR_DQ_io[30]
set_location_assignment PIN_C19 -to DDR_DQ_io[29]
set_location_assignment PIN_C18 -to DDR_DQ_io[28]
set_location_assignment PIN_F20 -to DDR_DQ_io[27]
set_location_assignment PIN_A20 -to DDR_DQ_io[26]
set_location_assignment PIN_A18 -to DDR_DQ_io[25]
set_location_assignment PIN_A17 -to DDR_DQ_io[24]
set_location_assignment PIN_C16 -to DDR_DQ_io[23]
set_location_assignment PIN_G17 -to DDR_DQ_io[22]
set_location_assignment PIN_D17 -to DDR_DQ_io[21]
set_location_assignment PIN_E16 -to DDR_DQ_io[20]
set_location_assignment PIN_J18 -to DDR_DQ_io[19]
set_location_assignment PIN_A15 -to DDR_DQ_io[18]
set_location_assignment PIN_E15 -to DDR_DQ_io[17]
set_location_assignment PIN_F15 -to DDR_DQ_io[16]
set_location_assignment PIN_K16 -to DDR_DQ_io[15]
set_location_assignment PIN_G15 -to DDR_DQ_io[14]
set_location_assignment PIN_C15 -to DDR_DQ_io[13]
set_location_assignment PIN_B15 -to DDR_DQ_io[12]
set_location_assignment PIN_A13 -to DDR_DQ_io[11]
set_location_assignment PIN_J11 -to DDR_DQ_io[10]
set_location_assignment PIN_E14 -to DDR_DQ_io[9]
set_location_assignment PIN_F13 -to DDR_DQ_io[8]
set_location_assignment PIN_F12 -to DDR_DQ_io[7]
set_location_assignment PIN_B12 -to DDR_DQ_io[6]
set_location_assignment PIN_D13 -to DDR_DQ_io[5]
set_location_assignment PIN_C13 -to DDR_DQ_io[4]
set_location_assignment PIN_K9 -to DDR_DQ_io[3]
set_location_assignment PIN_C11 -to DDR_DQ_io[2]
set_location_assignment PIN_D12 -to DDR_DQ_io[1]
set_location_assignment PIN_E12 -to DDR_DQ_io[0]
set_location_assignment PIN_F19 -to DDR_DQS_io_p[3]
set_location_assignment PIN_F18 -to DDR_DQS_io_n[3]
set_location_assignment PIN_G18 -to DDR_DQS_io_p[2]
set_location_assignment PIN_H18 -to DDR_DQS_io_n[2]
set_location_assignment PIN_H14 -to DDR_DQS_io_p[1]
set_location_assignment PIN_J13 -to DDR_DQS_io_n[1]
set_location_assignment PIN_H11 -to DDR_DQS_io_p[0]
set_location_assignment PIN_G12 -to DDR_DQS_io_n[0]


set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[4] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[4] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[5] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[5] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[6] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[6] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[7] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[7] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[8] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[8] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[9] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[9] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[10] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[10] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[11] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[11] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[12] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[12] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[13] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[13] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[14] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[14] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[15] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[15] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[16] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[16] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[17] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[17] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[18] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[18] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[19] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[19] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[20] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[20] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[21] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[21] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[22] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[22] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[23] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[23] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[24] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[24] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[25] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[25] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[26] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[26] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[27] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[27] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[28] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[28] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[29] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[29] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[30] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[30] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DQ_io[31] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQ_io[31] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V HSUL" -to DDR_DQS_io_p[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQS_io_p[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name D5_DELAY 4 -to DDR_DQS_io_p[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name D6_DELAY 0 -to DDR_DQS_io_p[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V HSUL" -to DDR_DQS_io_p[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQS_io_p[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name D5_DELAY 4 -to DDR_DQS_io_p[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name D6_DELAY 0 -to DDR_DQS_io_p[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V HSUL" -to DDR_DQS_io_p[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQS_io_p[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name D5_DELAY 4 -to DDR_DQS_io_p[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name D6_DELAY 0 -to DDR_DQS_io_p[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V HSUL" -to DDR_DQS_io_p[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQS_io_p[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name D5_DELAY 4 -to DDR_DQS_io_p[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name D6_DELAY 0 -to DDR_DQS_io_p[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V HSUL" -to DDR_DQS_io_n[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQS_io_n[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name D5_DELAY 4 -to DDR_DQS_io_n[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name D6_DELAY 0 -to DDR_DQS_io_n[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V HSUL" -to DDR_DQS_io_n[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQS_io_n[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name D5_DELAY 4 -to DDR_DQS_io_n[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name D6_DELAY 0 -to DDR_DQS_io_n[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V HSUL" -to DDR_DQS_io_n[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQS_io_n[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name D5_DELAY 4 -to DDR_DQS_io_n[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name D6_DELAY 0 -to DDR_DQS_io_n[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V HSUL" -to DDR_DQS_io_n[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DQS_io_n[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name D5_DELAY 4 -to DDR_DQS_io_n[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name D6_DELAY 0 -to DDR_DQS_io_n[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name D5_DELAY 4 -to DDR_CK_o_p -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V HSUL" -to DDR_CK_o_p -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_CK_o_p -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name D5_DELAY 4 -to DDR_CK_o_n -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V HSUL" -to DDR_CK_o_n -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_CK_o_n -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_CA_o[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_CA_o[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_CA_o[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_CA_o[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_CA_o[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_CA_o[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_CA_o[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_CA_o[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_CA_o[4] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_CA_o[4] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_CA_o[5] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_CA_o[5] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_CA_o[6] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_CA_o[6] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_CA_o[7] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_CA_o[7] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_CA_o[8] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_CA_o[8] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_CA_o[9] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_CA_o[9] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_CKE_o -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_CKE_o -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_CS_N_o -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_CS_N_o -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DM_o[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DM_o[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DM_o[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DM_o[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DM_o[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DM_o[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_DM_o[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITH CALIBRATION" -to DDR_DM_o[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.2-V HSUL" -to DDR_RZQ_i -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[4] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[5] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[6] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[7] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[8] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[9] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[10] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[11] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[12] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[13] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[14] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[15] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[16] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[17] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[18] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[19] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[20] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[21] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[22] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[23] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[24] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[25] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[26] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[27] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[28] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[29] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[30] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQ_io[31] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DM_o[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DM_o[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DM_o[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DM_o[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQS_io_p[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQS_io_p[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQS_io_p[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQS_io_p[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQS_io_n[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQS_io_n[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQS_io_n[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_DQS_io_n[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_CA_o[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_CA_o[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_CA_o[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_CA_o[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_CA_o[4] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_CA_o[5] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_CA_o[6] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_CA_o[7] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_CA_o[8] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_CA_o[9] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_CKE_o -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_CS_N_o -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_CK_o_p -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to DDR_CK_o_n -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to sys_inst|mem_if_lpddr2_emif_0|pll0|pll_avl_clk -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to sys_inst|mem_if_lpddr2_emif_0|pll0|pll_config_clk -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to sys_inst|mem_if_lpddr2_emif_0|p0|umemphy|ureset|phy_reset_mem_stable_n -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to sys_inst|mem_if_lpddr2_emif_0|p0|umemphy|ureset|phy_reset_n -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to sys_inst|mem_if_lpddr2_emif_0|s0|sequencer_rw_mgr_inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft_reset_n -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to sys_inst|mem_if_lpddr2_emif_0|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to sys_inst|mem_if_lpddr2_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to sys_inst|mem_if_lpddr2_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to sys_inst|mem_if_lpddr2_emif_0|p0|umemphy|uio_pads|dq_ddio[1].read_capture_clk_buffer -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to sys_inst|mem_if_lpddr2_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to sys_inst|mem_if_lpddr2_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to sys_inst|mem_if_lpddr2_emif_0|p0|umemphy|uio_pads|dq_ddio[2].read_capture_clk_buffer -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to sys_inst|mem_if_lpddr2_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to sys_inst|mem_if_lpddr2_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to sys_inst|mem_if_lpddr2_emif_0|p0|umemphy|uio_pads|dq_ddio[3].read_capture_clk_buffer -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to sys_inst|mem_if_lpddr2_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to sys_inst|mem_if_lpddr2_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3] -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to sys_inst|mem_if_lpddr2_emif_0 -tag __sys_mem_if_lpddr2_emif_0_p0
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to sys_inst|mem_if_lpddr2_emif_0|pll0|fbout -tag __sys_mem_if_lpddr2_emif_0_p0
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON
set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON


set_global_assignment -name SMART_RECOMPILE ON

set_global_assignment -name SEED 1

set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE





set_location_assignment CLKSEL_X28_Y0_N8 -to clkmux_capture
set_location_assignment CLKCTRL_G7 -to HDMIRX_PCLK_i~inputCLKENA0
set_global_assignment -name SDC_FILE ossc_pro.sdc
set_global_assignment -name QIP_FILE sys/synthesis/sys.qip
set_global_assignment -name VERILOG_FILE rtl/ic_frontends/isl51002/isl51002_frontend.v
set_global_assignment -name VERILOG_FILE rtl/ic_frontends/adv7611/adv7611_frontend.v
set_global_assignment -name VERILOG_FILE rtl/ic_frontends/adv7280a/adv7280a_frontend.v
set_global_assignment -name VERILOG_FILE rtl/scanconverter.v
set_global_assignment -name VERILOG_FILE rtl/linebuf_top.v
set_global_assignment -name VERILOG_FILE rtl/ir_rcv.v
set_global_assignment -name VERILOG_FILE rtl/pwm_2ch.v
set_global_assignment -name VERILOG_FILE rtl/dram_refresh_sched.v
set_global_assignment -name VERILOG_FILE rtl/output_csc.v
set_global_assignment -name SIP_FILE sys/simulation/sys.sip
set_global_assignment -name QIP_FILE software/sys_controller/mem_init/meminit.qip
set_global_assignment -name SIP_FILE software/sys_controller/mem_init/meminit.sip
set_global_assignment -name VERILOG_FILE rtl/ossc_pro.v
set_global_assignment -name SIGNALTAP_FILE output_files/ossc_pro_io.stp
set_global_assignment -name QIP_FILE rtl/linebuf.qip
set_global_assignment -name QIP_FILE rtl/linebuf_double.qip
set_global_assignment -name QIP_FILE rtl/char_array.qip
set_global_assignment -name QIP_FILE rtl/char_rom.qip
set_global_assignment -name QIP_FILE rtl/shmask_array.qip
set_global_assignment -name QIP_FILE rtl/dc_fifo_in.qip
set_global_assignment -name QIP_FILE rtl/dc_fifo_out.qip
set_global_assignment -name QIP_FILE rtl/lpm_mult_8x5_9.qip
set_global_assignment -name QIP_FILE rtl/lpm_mult_sl.qip
set_global_assignment -name QIP_FILE rtl/dc_fifo_emif_wr.qip
set_global_assignment -name QIP_FILE rtl/pll_sdp.qip
set_global_assignment -name SIP_FILE rtl/pll_sdp.sip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top