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pinctrl-keembay.c
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// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2020 Intel Corporation */
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include "core.h"
#include "pinmux.h"
/* GPIO data registers' offsets */
#define KEEMBAY_GPIO_DATA_OUT 0x000
#define KEEMBAY_GPIO_DATA_IN 0x020
#define KEEMBAY_GPIO_DATA_IN_RAW 0x040
#define KEEMBAY_GPIO_DATA_HIGH 0x060
#define KEEMBAY_GPIO_DATA_LOW 0x080
/* GPIO Interrupt and mode registers' offsets */
#define KEEMBAY_GPIO_INT_CFG 0x000
#define KEEMBAY_GPIO_MODE 0x070
/* GPIO mode register bit fields */
#define KEEMBAY_GPIO_MODE_PULLUP_MASK GENMASK(13, 12)
#define KEEMBAY_GPIO_MODE_DRIVE_MASK GENMASK(8, 7)
#define KEEMBAY_GPIO_MODE_INV_MASK GENMASK(5, 4)
#define KEEMBAY_GPIO_MODE_SELECT_MASK GENMASK(2, 0)
#define KEEMBAY_GPIO_MODE_DIR_OVR BIT(15)
#define KEEMBAY_GPIO_MODE_REN BIT(11)
#define KEEMBAY_GPIO_MODE_SCHMITT_EN BIT(10)
#define KEEMBAY_GPIO_MODE_SLEW_RATE BIT(9)
#define KEEMBAY_GPIO_IRQ_ENABLE BIT(7)
#define KEEMBAY_GPIO_MODE_DIR BIT(3)
#define KEEMBAY_GPIO_MODE_DEFAULT 0x7
#define KEEMBAY_GPIO_MODE_INV_VAL 0x3
#define KEEMBAY_GPIO_DISABLE 0
#define KEEMBAY_GPIO_PULL_UP 1
#define KEEMBAY_GPIO_PULL_DOWN 2
#define KEEMBAY_GPIO_BUS_HOLD 3
#define KEEMBAY_GPIO_NUM_IRQ 8
#define KEEMBAY_GPIO_MAX_PER_IRQ 4
#define KEEMBAY_GPIO_MAX_PER_REG 32
#define KEEMBAY_GPIO_MIN_STRENGTH 2
#define KEEMBAY_GPIO_MAX_STRENGTH 12
#define KEEMBAY_GPIO_SENSE_LOW (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)
/* GPIO reg address calculation */
#define KEEMBAY_GPIO_REG_OFFSET(pin) ((pin) * 4)
/**
* struct keembay_mux_desc - Mux properties of each GPIO pin
* @mode: Pin mode when operating in this function
* @name: Pin function name
*/
struct keembay_mux_desc {
u8 mode;
const char *name;
};
#define KEEMBAY_PIN_DESC(pin_number, pin_name, ...) { \
.number = pin_number, \
.name = pin_name, \
.drv_data = &(struct keembay_mux_desc[]) { \
__VA_ARGS__, { } }, \
} \
#define KEEMBAY_MUX(pin_mode, pin_function) { \
.mode = pin_mode, \
.name = pin_function, \
} \
/**
* struct keembay_gpio_irq - Config of each GPIO Interrupt sources
* @source: Interrupt source number (0 - 7)
* @line: Actual Interrupt line number
* @pins: Array of GPIO pins using this Interrupt line
* @trigger: Interrupt trigger type for this line
* @num_share: Number of pins currently using this Interrupt line
*/
struct keembay_gpio_irq {
unsigned int source;
unsigned int line;
unsigned int pins[KEEMBAY_GPIO_MAX_PER_IRQ];
unsigned int trigger;
unsigned int num_share;
};
/**
* struct keembay_pinctrl - Intel Keembay pinctrl structure
* @pctrl: Pointer to the pin controller device
* @base0: First register base address
* @base1: Second register base address
* @dev: Pointer to the device structure
* @chip: GPIO chip used by this pin controller
* @soc: Pin control configuration data based on SoC
* @lock: Spinlock to protect various gpio config register access
* @ngroups: Number of pin groups available
* @nfuncs: Number of pin functions available
* @npins: Number of GPIO pins available
* @irq: Store Interrupt source
* @max_gpios_level_type: Store max level trigger type
* @max_gpios_edge_type: Store max edge trigger type
*/
struct keembay_pinctrl {
struct pinctrl_dev *pctrl;
void __iomem *base0;
void __iomem *base1;
struct device *dev;
struct gpio_chip chip;
const struct keembay_pin_soc *soc;
raw_spinlock_t lock;
unsigned int ngroups;
unsigned int nfuncs;
unsigned int npins;
struct keembay_gpio_irq irq[KEEMBAY_GPIO_NUM_IRQ];
int max_gpios_level_type;
int max_gpios_edge_type;
};
/**
* struct keembay_pin_soc - Pin control config data based on SoC
* @pins: Pin description structure
*/
struct keembay_pin_soc {
const struct pinctrl_pin_desc *pins;
};
static const struct pinctrl_pin_desc keembay_pins[] = {
KEEMBAY_PIN_DESC(0, "GPIO0",
KEEMBAY_MUX(0x0, "I2S0_M0"),
KEEMBAY_MUX(0x1, "SD0_M1"),
KEEMBAY_MUX(0x2, "SLVDS0_M2"),
KEEMBAY_MUX(0x3, "I2C0_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(1, "GPIO1",
KEEMBAY_MUX(0x0, "I2S0_M0"),
KEEMBAY_MUX(0x1, "SD0_M1"),
KEEMBAY_MUX(0x2, "SLVDS0_M2"),
KEEMBAY_MUX(0x3, "I2C0_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(2, "GPIO2",
KEEMBAY_MUX(0x0, "I2S0_M0"),
KEEMBAY_MUX(0x1, "I2S0_M1"),
KEEMBAY_MUX(0x2, "SLVDS0_M2"),
KEEMBAY_MUX(0x3, "I2C1_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(3, "GPIO3",
KEEMBAY_MUX(0x0, "I2S0_M0"),
KEEMBAY_MUX(0x1, "I2S0_M1"),
KEEMBAY_MUX(0x2, "SLVDS0_M2"),
KEEMBAY_MUX(0x3, "I2C1_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(4, "GPIO4",
KEEMBAY_MUX(0x0, "I2S0_M0"),
KEEMBAY_MUX(0x1, "I2S0_M1"),
KEEMBAY_MUX(0x2, "SLVDS0_M2"),
KEEMBAY_MUX(0x3, "I2C2_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(5, "GPIO5",
KEEMBAY_MUX(0x0, "I2S0_M0"),
KEEMBAY_MUX(0x1, "I2S0_M1"),
KEEMBAY_MUX(0x2, "SLVDS0_M2"),
KEEMBAY_MUX(0x3, "I2C2_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(6, "GPIO6",
KEEMBAY_MUX(0x0, "I2S1_M0"),
KEEMBAY_MUX(0x1, "SD0_M1"),
KEEMBAY_MUX(0x2, "SLVDS0_M2"),
KEEMBAY_MUX(0x3, "I2C3_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(7, "GPIO7",
KEEMBAY_MUX(0x0, "I2S1_M0"),
KEEMBAY_MUX(0x1, "SD0_M1"),
KEEMBAY_MUX(0x2, "SLVDS0_M2"),
KEEMBAY_MUX(0x3, "I2C3_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(8, "GPIO8",
KEEMBAY_MUX(0x0, "I2S1_M0"),
KEEMBAY_MUX(0x1, "I2S1_M1"),
KEEMBAY_MUX(0x2, "SLVDS0_M2"),
KEEMBAY_MUX(0x3, "UART0_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(9, "GPIO9",
KEEMBAY_MUX(0x0, "I2S1_M0"),
KEEMBAY_MUX(0x1, "I2S1_M1"),
KEEMBAY_MUX(0x2, "PWM_M2"),
KEEMBAY_MUX(0x3, "UART0_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(10, "GPIO10",
KEEMBAY_MUX(0x0, "I2S2_M0"),
KEEMBAY_MUX(0x1, "SD0_M1"),
KEEMBAY_MUX(0x2, "PWM_M2"),
KEEMBAY_MUX(0x3, "UART0_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(11, "GPIO11",
KEEMBAY_MUX(0x0, "I2S2_M0"),
KEEMBAY_MUX(0x1, "SD0_M1"),
KEEMBAY_MUX(0x2, "PWM_M2"),
KEEMBAY_MUX(0x3, "UART0_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(12, "GPIO12",
KEEMBAY_MUX(0x0, "I2S2_M0"),
KEEMBAY_MUX(0x1, "I2S2_M1"),
KEEMBAY_MUX(0x2, "PWM_M2"),
KEEMBAY_MUX(0x3, "SPI0_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(13, "GPIO13",
KEEMBAY_MUX(0x0, "I2S2_M0"),
KEEMBAY_MUX(0x1, "I2S2_M1"),
KEEMBAY_MUX(0x2, "PWM_M2"),
KEEMBAY_MUX(0x3, "SPI0_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(14, "GPIO14",
KEEMBAY_MUX(0x0, "UART0_M0"),
KEEMBAY_MUX(0x1, "I2S3_M1"),
KEEMBAY_MUX(0x2, "PWM_M2"),
KEEMBAY_MUX(0x3, "SD1_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(15, "GPIO15",
KEEMBAY_MUX(0x0, "UART0_M0"),
KEEMBAY_MUX(0x1, "I2S3_M1"),
KEEMBAY_MUX(0x2, "UART0_M2"),
KEEMBAY_MUX(0x3, "SD1_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "SPI1_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(16, "GPIO16",
KEEMBAY_MUX(0x0, "UART0_M0"),
KEEMBAY_MUX(0x1, "I2S3_M1"),
KEEMBAY_MUX(0x2, "UART0_M2"),
KEEMBAY_MUX(0x3, "SD1_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "SPI1_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(17, "GPIO17",
KEEMBAY_MUX(0x0, "UART0_M0"),
KEEMBAY_MUX(0x1, "I2S3_M1"),
KEEMBAY_MUX(0x2, "I2S3_M2"),
KEEMBAY_MUX(0x3, "SD1_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "SPI1_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(18, "GPIO18",
KEEMBAY_MUX(0x0, "UART1_M0"),
KEEMBAY_MUX(0x1, "SPI0_M1"),
KEEMBAY_MUX(0x2, "I2S3_M2"),
KEEMBAY_MUX(0x3, "SD1_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "SPI1_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(19, "GPIO19",
KEEMBAY_MUX(0x0, "UART1_M0"),
KEEMBAY_MUX(0x1, "LCD_M1"),
KEEMBAY_MUX(0x2, "DEBUG_M2"),
KEEMBAY_MUX(0x3, "SD1_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "SPI1_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(20, "GPIO20",
KEEMBAY_MUX(0x0, "UART1_M0"),
KEEMBAY_MUX(0x1, "LCD_M1"),
KEEMBAY_MUX(0x2, "DEBUG_M2"),
KEEMBAY_MUX(0x3, "CPR_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "SPI1_M5"),
KEEMBAY_MUX(0x6, "SLVDS0_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(21, "GPIO21",
KEEMBAY_MUX(0x0, "UART1_M0"),
KEEMBAY_MUX(0x1, "LCD_M1"),
KEEMBAY_MUX(0x2, "DEBUG_M2"),
KEEMBAY_MUX(0x3, "CPR_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I3C0_M5"),
KEEMBAY_MUX(0x6, "SLVDS0_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(22, "GPIO22",
KEEMBAY_MUX(0x0, "I2C0_M0"),
KEEMBAY_MUX(0x1, "UART2_M1"),
KEEMBAY_MUX(0x2, "DEBUG_M2"),
KEEMBAY_MUX(0x3, "CPR_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I3C0_M5"),
KEEMBAY_MUX(0x6, "SLVDS0_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(23, "GPIO23",
KEEMBAY_MUX(0x0, "I2C0_M0"),
KEEMBAY_MUX(0x1, "UART2_M1"),
KEEMBAY_MUX(0x2, "DEBUG_M2"),
KEEMBAY_MUX(0x3, "CPR_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I3C1_M5"),
KEEMBAY_MUX(0x6, "SLVDS0_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(24, "GPIO24",
KEEMBAY_MUX(0x0, "I2C1_M0"),
KEEMBAY_MUX(0x1, "UART2_M1"),
KEEMBAY_MUX(0x2, "DEBUG_M2"),
KEEMBAY_MUX(0x3, "CPR_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I3C1_M5"),
KEEMBAY_MUX(0x6, "SLVDS0_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(25, "GPIO25",
KEEMBAY_MUX(0x0, "I2C1_M0"),
KEEMBAY_MUX(0x1, "UART2_M1"),
KEEMBAY_MUX(0x2, "SPI0_M2"),
KEEMBAY_MUX(0x3, "CPR_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I3C2_M5"),
KEEMBAY_MUX(0x6, "SLVDS0_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(26, "GPIO26",
KEEMBAY_MUX(0x0, "SPI0_M0"),
KEEMBAY_MUX(0x1, "I2C2_M1"),
KEEMBAY_MUX(0x2, "UART0_M2"),
KEEMBAY_MUX(0x3, "DSU_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I3C2_M5"),
KEEMBAY_MUX(0x6, "SLVDS0_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(27, "GPIO27",
KEEMBAY_MUX(0x0, "SPI0_M0"),
KEEMBAY_MUX(0x1, "I2C2_M1"),
KEEMBAY_MUX(0x2, "UART0_M2"),
KEEMBAY_MUX(0x3, "DSU_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I3C0_M5"),
KEEMBAY_MUX(0x6, "SLVDS0_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(28, "GPIO28",
KEEMBAY_MUX(0x0, "SPI0_M0"),
KEEMBAY_MUX(0x1, "I2C3_M1"),
KEEMBAY_MUX(0x2, "UART0_M2"),
KEEMBAY_MUX(0x3, "PWM_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I3C1_M5"),
KEEMBAY_MUX(0x6, "SLVDS0_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(29, "GPIO29",
KEEMBAY_MUX(0x0, "SPI0_M0"),
KEEMBAY_MUX(0x1, "I2C3_M1"),
KEEMBAY_MUX(0x2, "UART0_M2"),
KEEMBAY_MUX(0x3, "PWM_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I3C2_M5"),
KEEMBAY_MUX(0x6, "SLVDS1_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(30, "GPIO30",
KEEMBAY_MUX(0x0, "SPI0_M0"),
KEEMBAY_MUX(0x1, "I2S0_M1"),
KEEMBAY_MUX(0x2, "I2C4_M2"),
KEEMBAY_MUX(0x3, "PWM_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "SLVDS1_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(31, "GPIO31",
KEEMBAY_MUX(0x0, "SPI0_M0"),
KEEMBAY_MUX(0x1, "I2S0_M1"),
KEEMBAY_MUX(0x2, "I2C4_M2"),
KEEMBAY_MUX(0x3, "PWM_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "UART1_M5"),
KEEMBAY_MUX(0x6, "SLVDS1_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(32, "GPIO32",
KEEMBAY_MUX(0x0, "SD0_M0"),
KEEMBAY_MUX(0x1, "SPI0_M1"),
KEEMBAY_MUX(0x2, "UART1_M2"),
KEEMBAY_MUX(0x3, "PWM_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "PCIE_M5"),
KEEMBAY_MUX(0x6, "SLVDS1_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(33, "GPIO33",
KEEMBAY_MUX(0x0, "SD0_M0"),
KEEMBAY_MUX(0x1, "SPI0_M1"),
KEEMBAY_MUX(0x2, "UART1_M2"),
KEEMBAY_MUX(0x3, "PWM_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "PCIE_M5"),
KEEMBAY_MUX(0x6, "SLVDS1_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(34, "GPIO34",
KEEMBAY_MUX(0x0, "SD0_M0"),
KEEMBAY_MUX(0x1, "SPI0_M1"),
KEEMBAY_MUX(0x2, "I2C0_M2"),
KEEMBAY_MUX(0x3, "UART1_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I2S0_M5"),
KEEMBAY_MUX(0x6, "SLVDS1_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(35, "GPIO35",
KEEMBAY_MUX(0x0, "SD0_M0"),
KEEMBAY_MUX(0x1, "PCIE_M1"),
KEEMBAY_MUX(0x2, "I2C0_M2"),
KEEMBAY_MUX(0x3, "UART1_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I2S0_M5"),
KEEMBAY_MUX(0x6, "SLVDS1_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(36, "GPIO36",
KEEMBAY_MUX(0x0, "SD0_M0"),
KEEMBAY_MUX(0x1, "SPI3_M1"),
KEEMBAY_MUX(0x2, "I2C1_M2"),
KEEMBAY_MUX(0x3, "DEBUG_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I2S0_M5"),
KEEMBAY_MUX(0x6, "SLVDS1_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(37, "GPIO37",
KEEMBAY_MUX(0x0, "SD0_M0"),
KEEMBAY_MUX(0x1, "SPI3_M1"),
KEEMBAY_MUX(0x2, "I2C1_M2"),
KEEMBAY_MUX(0x3, "DEBUG_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I2S0_M5"),
KEEMBAY_MUX(0x6, "SLVDS1_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(38, "GPIO38",
KEEMBAY_MUX(0x0, "I3C1_M0"),
KEEMBAY_MUX(0x1, "SPI3_M1"),
KEEMBAY_MUX(0x2, "UART3_M2"),
KEEMBAY_MUX(0x3, "DEBUG_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2C2_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(39, "GPIO39",
KEEMBAY_MUX(0x0, "I3C1_M0"),
KEEMBAY_MUX(0x1, "SPI3_M1"),
KEEMBAY_MUX(0x2, "UART3_M2"),
KEEMBAY_MUX(0x3, "DEBUG_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2C2_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(40, "GPIO40",
KEEMBAY_MUX(0x0, "I2S2_M0"),
KEEMBAY_MUX(0x1, "SPI3_M1"),
KEEMBAY_MUX(0x2, "UART3_M2"),
KEEMBAY_MUX(0x3, "DEBUG_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2C3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(41, "GPIO41",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SPI3_M1"),
KEEMBAY_MUX(0x2, "SPI3_M2"),
KEEMBAY_MUX(0x3, "DEBUG_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2C3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(42, "GPIO42",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SD1_M1"),
KEEMBAY_MUX(0x2, "SPI3_M2"),
KEEMBAY_MUX(0x3, "CPR_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2C4_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(43, "GPIO43",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SD1_M1"),
KEEMBAY_MUX(0x2, "SPI3_M2"),
KEEMBAY_MUX(0x3, "CPR_M3"),
KEEMBAY_MUX(0x4, "I2S0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2C4_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(44, "GPIO44",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SD1_M1"),
KEEMBAY_MUX(0x2, "SPI0_M2"),
KEEMBAY_MUX(0x3, "CPR_M3"),
KEEMBAY_MUX(0x4, "I2S0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(45, "GPIO45",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SD1_M1"),
KEEMBAY_MUX(0x2, "SPI0_M2"),
KEEMBAY_MUX(0x3, "CPR_M3"),
KEEMBAY_MUX(0x4, "I2S0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(46, "GPIO46",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SD1_M1"),
KEEMBAY_MUX(0x2, "SPI0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(47, "GPIO47",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SD1_M1"),
KEEMBAY_MUX(0x2, "SPI0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(48, "GPIO48",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SPI2_M1"),
KEEMBAY_MUX(0x2, "UART2_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(49, "GPIO49",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SPI2_M1"),
KEEMBAY_MUX(0x2, "UART2_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S1_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(50, "GPIO50",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SPI2_M1"),
KEEMBAY_MUX(0x2, "UART2_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S1_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(51, "GPIO51",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SPI2_M1"),
KEEMBAY_MUX(0x2, "UART2_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S1_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(52, "GPIO52",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SPI2_M1"),
KEEMBAY_MUX(0x2, "SD0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S1_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(53, "GPIO53",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SPI2_M1"),
KEEMBAY_MUX(0x2, "SD0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S2_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(54, "GPIO54",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SPI2_M1"),
KEEMBAY_MUX(0x2, "SD0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S2_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(55, "GPIO55",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SPI2_M1"),
KEEMBAY_MUX(0x2, "SD1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S2_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(56, "GPIO56",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SPI2_M1"),
KEEMBAY_MUX(0x2, "SD1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S2_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(57, "GPIO57",
KEEMBAY_MUX(0x0, "SPI1_M0"),
KEEMBAY_MUX(0x1, "I2S1_M1"),
KEEMBAY_MUX(0x2, "SD1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "UART0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(58, "GPIO58",
KEEMBAY_MUX(0x0, "SPI1_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "SD0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "UART0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(59, "GPIO59",
KEEMBAY_MUX(0x0, "SPI1_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "SD0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "UART0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(60, "GPIO60",
KEEMBAY_MUX(0x0, "SPI1_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "I3C1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "UART0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(61, "GPIO61",
KEEMBAY_MUX(0x0, "SPI1_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "SD0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "UART1_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(62, "GPIO62",
KEEMBAY_MUX(0x0, "SPI1_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "SD1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "UART1_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(63, "GPIO63",
KEEMBAY_MUX(0x0, "I2S1_M0"),
KEEMBAY_MUX(0x1, "SPI1_M1"),
KEEMBAY_MUX(0x2, "SD1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "UART1_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(64, "GPIO64",
KEEMBAY_MUX(0x0, "I2S2_M0"),
KEEMBAY_MUX(0x1, "SPI1_M1"),
KEEMBAY_MUX(0x2, "ETH_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "UART1_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(65, "GPIO65",
KEEMBAY_MUX(0x0, "I3C0_M0"),
KEEMBAY_MUX(0x1, "SPI1_M1"),
KEEMBAY_MUX(0x2, "SD1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SPI0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(66, "GPIO66",
KEEMBAY_MUX(0x0, "I3C0_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "I2C0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SPI0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(67, "GPIO67",
KEEMBAY_MUX(0x0, "I3C1_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "I2C0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SPI0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2S3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(68, "GPIO68",
KEEMBAY_MUX(0x0, "I3C1_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "I2C1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SPI0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2S3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(69, "GPIO69",
KEEMBAY_MUX(0x0, "I3C2_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "I2C1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SPI0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2S3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(70, "GPIO70",
KEEMBAY_MUX(0x0, "I3C2_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "SPI0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SD0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2S3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(71, "GPIO71",
KEEMBAY_MUX(0x0, "I3C0_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "SLVDS1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SD0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2S3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(72, "GPIO72",
KEEMBAY_MUX(0x0, "I3C1_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "SLVDS1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SD0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "UART2_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(73, "GPIO73",
KEEMBAY_MUX(0x0, "I3C2_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "SLVDS1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SD0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "UART2_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(74, "GPIO74",
KEEMBAY_MUX(0x0, "I3C0_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "SLVDS1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SD0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "UART2_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(75, "GPIO75",
KEEMBAY_MUX(0x0, "I3C0_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "SLVDS1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SD0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "UART2_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(76, "GPIO76",
KEEMBAY_MUX(0x0, "I2C2_M0"),
KEEMBAY_MUX(0x1, "I3C0_M1"),
KEEMBAY_MUX(0x2, "SLVDS1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "ETH_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "UART3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(77, "GPIO77",
KEEMBAY_MUX(0x0, "PCIE_M0"),
KEEMBAY_MUX(0x1, "I3C1_M1"),
KEEMBAY_MUX(0x2, "SLVDS1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I3C2_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "UART3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(78, "GPIO78",
KEEMBAY_MUX(0x0, "PCIE_M0"),
KEEMBAY_MUX(0x1, "I3C2_M1"),
KEEMBAY_MUX(0x2, "SLVDS1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I3C2_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "UART3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(79, "GPIO79",
KEEMBAY_MUX(0x0, "PCIE_M0"),
KEEMBAY_MUX(0x1, "I2C2_M1"),
KEEMBAY_MUX(0x2, "SLVDS1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I3C2_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "UART3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
};
static inline u32 keembay_read_reg(void __iomem *base, unsigned int pin)
{
return readl(base + KEEMBAY_GPIO_REG_OFFSET(pin));
}
static inline u32 keembay_read_gpio_reg(void __iomem *base, unsigned int pin)
{
return keembay_read_reg(base, pin / KEEMBAY_GPIO_MAX_PER_REG);
}
static inline u32 keembay_read_pin(void __iomem *base, unsigned int pin)
{
u32 val = keembay_read_gpio_reg(base, pin);
return !!(val & BIT(pin % KEEMBAY_GPIO_MAX_PER_REG));
}
static inline void keembay_write_reg(u32 val, void __iomem *base, unsigned int pin)
{
writel(val, base + KEEMBAY_GPIO_REG_OFFSET(pin));
}
static inline void keembay_write_gpio_reg(u32 val, void __iomem *base, unsigned int pin)
{
keembay_write_reg(val, base, pin / KEEMBAY_GPIO_MAX_PER_REG);
}
static void keembay_gpio_invert(struct keembay_pinctrl *kpc, unsigned int pin)
{
unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
/*
* This IP doesn't support the falling edge and low level interrupt
* trigger. Invert API is used to mimic the falling edge and low
* level support
*/
val |= FIELD_PREP(KEEMBAY_GPIO_MODE_INV_MASK, KEEMBAY_GPIO_MODE_INV_VAL);
keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
}
static void keembay_gpio_restore_default(struct keembay_pinctrl *kpc, unsigned int pin)
{
unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
val &= FIELD_PREP(KEEMBAY_GPIO_MODE_INV_MASK, 0);
keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
}
static int keembay_request_gpio(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned int pin)
{
struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev);
unsigned int val;
if (pin >= kpc->npins)
return -EINVAL;
val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
val = FIELD_GET(KEEMBAY_GPIO_MODE_SELECT_MASK, val);
/* As per Pin Mux Map, Modes 0 to 6 are for peripherals */
if (val != KEEMBAY_GPIO_MODE_DEFAULT)
return -EBUSY;
return 0;
}
static int keembay_set_mux(struct pinctrl_dev *pctldev, unsigned int fun_sel,
unsigned int grp_sel)
{
struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev);
struct function_desc *func;
struct group_desc *grp;
unsigned int val;
u8 pin_mode;
int pin;
grp = pinctrl_generic_get_group(pctldev, grp_sel);
if (!grp)
return -EINVAL;
func = pinmux_generic_get_function(pctldev, fun_sel);
if (!func)
return -EINVAL;
/* Change modes for pins in the selected group */
pin = *grp->grp.pins;
pin_mode = *(u8 *)(func->data);
val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
val = u32_replace_bits(val, pin_mode, KEEMBAY_GPIO_MODE_SELECT_MASK);
keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
return 0;
}
static u32 keembay_pinconf_get_pull(struct keembay_pinctrl *kpc, unsigned int pin)
{
unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
return FIELD_GET(KEEMBAY_GPIO_MODE_PULLUP_MASK, val);
}
static int keembay_pinconf_set_pull(struct keembay_pinctrl *kpc, unsigned int pin,
unsigned int pull)
{
unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
val = u32_replace_bits(val, pull, KEEMBAY_GPIO_MODE_PULLUP_MASK);
keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
return 0;
}
static int keembay_pinconf_get_drive(struct keembay_pinctrl *kpc, unsigned int pin)
{
unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
val = FIELD_GET(KEEMBAY_GPIO_MODE_DRIVE_MASK, val) * 4;
if (val)
return val;
return KEEMBAY_GPIO_MIN_STRENGTH;
}
static int keembay_pinconf_set_drive(struct keembay_pinctrl *kpc, unsigned int pin,
unsigned int drive)
{
unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
unsigned int strength = clamp_val(drive, KEEMBAY_GPIO_MIN_STRENGTH,
KEEMBAY_GPIO_MAX_STRENGTH) / 4;
val = u32_replace_bits(val, strength, KEEMBAY_GPIO_MODE_DRIVE_MASK);
keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
return 0;
}
static int keembay_pinconf_get_slew_rate(struct keembay_pinctrl *kpc, unsigned int pin)