diff --git a/.gitignore b/.gitignore index 27b23c9..4f726bd 100644 --- a/.gitignore +++ b/.gitignore @@ -22,3 +22,6 @@ docs-pdf/Makefile docs-pdf/make.bat docs-pdf/mistral.fdb_latexmk docs-pdf/floorplans.pdf +docs-pdf/lab-common.pdf +docs-pdf/lab-cell.pdf +docs-pdf/lab-modes.pdf diff --git a/docs-html/_images/lab-cell.svg b/docs-html/_images/lab-cell.svg new file mode 100644 index 0000000..a5571aa --- /dev/null +++ b/docs-html/_images/lab-cell.svg @@ -0,0 +1,4534 @@ + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + F1 + + + + + + + + A + + + + + + + + + B + + + + + + + + + C + + + + + + + + + D + + + + + + + + + E0 + + + + + + + + + E1 + + + + + + + + F0 + + + + + + + + + + + LUT4 + + A + + + LUT3 + B + + + + + + LUT3 + C + + + + + + + + + LUT4 + D + + LUT3 + E + + + LUT3 + F + + A0 + A1 + A2 + A3 + A0 + A1 + A2 + A3 + A0 + A1 + A2 + A0 + A1 + A2 + A0 + A1 + A2 + A0 + A1 + A2 + + + + + + + + + + + + + + + + share + t + f + + + + + + + SHARE + + + + + + + + + + + + + + + + + + + + + 00 + 01 + 10 + 11 + + + + + + 00 + 01 + 10 + 11 + + + + + + + Adder + + I0 + I1 + I2 + S + C + + + + Adder + I0 + I1 + I2 + S + C + + + + + + share + t + f + + + + + + + + + CARRY + + + + + + + SHARE + + + + + + CARRY + 0 + 1 + + + 0 + 1 + 0 + 1 + + + 0 + 1 + + + + + + + + + + + FF + + + D + R + Q + FF + + + D + R + Q + + + + + 0 + 1 + + + + + + + + + + + + CLK0 + + + + + + CLK1 + + + + + + CLK2 + + + + + + + tclk_sel + bclk_sel + 0 + 0 + + + + + + 0 + + + tsclr_dis + + 1 + tpkreg0 + 0 + tsload_en + + + + + + + 0 + 1 + + 1 + tpkreg1 + + + + + + + SLOAD + + + + + + SCLR + + + + + adder + lut + arith_sel + + + + + e + f + tef_sel + + + + + + + + + + + + + + + + + + + + + + FF + + + D + R + Q + FF + + + D + R + Q + + + + + 0 + 1 + + + 0 + + + bsclr_dis + + 1 + bpkreg0 + 0 + bsload_en + + + + + + 0 + 1 + + 1 + bpkreg1 + + + + + + adder + lut + arith_sel + + + + + e + f + bef_sel + + + + + + + + + + + + + + + ACLR0 + + + + + + ACLR1 + + + + + + + + + + + tclr_sel + bclr_sel + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + tdff0 + tdff1 + tdff1l + + + + + + + + + + t_feedback_sel + + + + + + + + + + + + + + + + + + + + + + + + + + bdff0 + bdff1 + bdff1l + + + + + + + + + b_feedback_sel + + + + + + + + + FFT0 + + + + + + FFT1 + + + + + + FFT1L + + + + + + + + + + FFB0 + + + + + + FFB1 + + + + + + FFB1L + + + MODE + + + TA2 + TA3 + TS + BA2 + + + C + D + E0 + E1 + TFB + BFB + + BA3 + BS + + diff --git a/docs-html/_images/lab-common.svg b/docs-html/_images/lab-common.svg new file mode 100644 index 0000000..74c4d98 --- /dev/null +++ b/docs-html/_images/lab-common.svg @@ -0,0 +1,2221 @@ + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + DATAIN.3 + + + + + + + + ACLR.0 + + + + + + + + + ACLR.1 + + + + + + + + + CLKIN.0 + + + + + + + + + CLKIN.1 + + + + + + + + + + DATAIN.0 + + + + + + + + + DATAIN.1 + + + + + + + + DATAIN.2 + + + + + + + + + + + + + + + aclr0_sel + aclr0_inv + + t + f + + clk2 + + gin1 + + + + + + + + + + + + + + + + aclr1_sel + aclr1_inv + t + f + clk3 + gin0 + + + + + + + + + + + + + + + clka_sel + clk1_inv + t + f + clk2 + gin2 + + + + + + + + + + + + + + clkb_sel + clk1_inv + t + f + clk2 + gin3 + + + + + + + + clk2_inv + t + f + + + + + + + clk1_sel + + + + + + + clk0_sel + + + + + + + clk2_sel + + + + + + + + + + + + + + + + + + + + + + + + + + ACLR0 + ACLR1 + CLK0 + CLK1 + CLK2 + clka + clkb + + clka + clkb + clka + clkb + + + + + + + + + + + + + + + + + + + + + en0_inv + t + f + + + + + + + en0_sel + gin1 + gin3 + + + + + + + + + en1_inv + t + f + + + + + + + en1_sel + gin0 + gin3 + + + + + + + + + en2_inv + t + f + + + + + + + ? + ? + ? + + + + + + + + + + sclr_inv + t + f + + + + + + + sclr_sel + + + + + + SCLR + gin2 + gin3 + + + + + + + + + + sload_inv + t + f + + + + + + + sload_sel + + + + + + SLOAD + gin0 + gin3 + + + + + + + + + + + + + + + + + diff --git a/docs-html/_images/lab-modes.svg b/docs-html/_images/lab-modes.svg new file mode 100644 index 0000000..fd3f60a --- /dev/null +++ b/docs-html/_images/lab-modes.svg @@ -0,0 +1,3630 @@ + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + TA2 + TA3 + TS + BA2 + C + D + E0 + E1 + TFB + BFB + + + + + + + + + + l5 + + + + + + + + + + + + + + + + TA2 + TA3 + TS + BA2 + C + D + E0 + E1 + TFB + BFB + + + + + + + + + + l5_ft + + + TA2 + TA3 + TS + BA2 + C + D + E0 + E1 + TFB + BFB + + + + + + + + + + l5_fb + + TA2 + TA3 + TS + BA2 + C + D + E0 + E1 + TFB + BFB + + + + + + l6 + + TA2 + TA3 + TS + BA2 + C + D + E0 + E1 + TFB + BFB + + + + + + + + + + l6_ft + + TA2 + TA3 + TS + BA2 + C + D + E0 + E1 + TFB + BFB + + + + + + + + + + l6_fb + + TA2 + TA3 + TS + BA2 + C + D + E0 + E1 + TFB + BFB + + + + + + + + + + l6_ftb + + TA2 + TA3 + TS + BA2 + C + D + E0 + E1 + TFB + BFB + + + + + + + + + + l7_e0 + + TA2 + TA3 + TS + BA2 + C + D + E0 + E1 + TFB + BFB + + + + + + + + + + l7_e0_ft + + TA2 + TA3 + TS + BA2 + C + D + E0 + E1 + TFB + BFB + + + + + + + + + + l7_e0_fb + + TA2 + TA3 + TS + BA2 + C + D + E0 + E1 + TFB + BFB + + + + + + + + + + 7_e0_ftb + + TA2 + TA3 + TS + BA2 + C + D + E0 + E1 + TFB + BFB + + + + + + + + + + l7_e1 + + TA2 + TA3 + TS + BA2 + C + D + E0 + E1 + TFB + BFB + + + + + + + + + + l7_e1_fb + + TA2 + TA3 + TS + BA2 + C + D + E0 + E1 + TFB + BFB + + + + + + + + + + l7_e1_ft + + TA2 + TA3 + TS + BA2 + C + D + E0 + E1 + TFB + BFB + + + + + + + + + + l7_e1_ftb + BA3 + BS + + + BA3 + BS + + + BA3 + BS + + + BA3 + BS + + + BA3 + BS + + + BA3 + BS + + + BA3 + BS + + + BA3 + BS + + + BA3 + BS + BA3 + BS + + + BA3 + BS + + + BA3 + BS + + + BA3 + BS + + + BA3 + BS + + + BA3 + BS + + + BA3 + BS + + + + + + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + + + + + + + + + TA2 + TA3 + TS + BA2 + C + D + E0 + E1 + TFB + BFB + + + + + + + + + + l5_ftb + + + + + + + + + + + + + + + + + + + + diff --git a/docs-html/index.html b/docs-html/index.html index bf58303..c4d4535 100644 --- a/docs-html/index.html +++ b/docs-html/index.html @@ -477,18 +477,31 @@

Inner logic blocks

LAB¶

The LABs are the main combinatorial and register blocks of the FPGA. -A LAB tile includes 10 sub-blocks with 64 bits of LUT splitted in 6 -parts, four Flip-Flops, two 1-bit adders and a lot of routing logic. -In addition a common control subblock selects and dispatches clock, -enable, clear, etc signals.

+A LAB tile includes 10 sub-blocks called cells with 64 bits of LUT +splitted in 6 parts, four Flip-Flops, two 1-bit adders and a lot of +routing logic. In addition a common control subblock selects and +dispatches clock, enable, clear, etc signals.

+
+_images/lab-common.svg +

The part of the LAB shared by all ten cells that generates the +common signals.¶

+
+
+_images/lab-cell.svg +

One of the 10 cells of the LAB.¶

+
+
+_images/lab-modes.svg +

The 16 possible interconnection modes.¶

+
-----+++++ @@ -509,7 +522,7 @@

LAB¶

- + @@ -522,7 +535,7 @@

LAB¶

- + @@ -532,7 +545,7 @@

LAB¶

- + @@ -543,7 +556,7 @@

LAB¶

- + @@ -554,7 +567,7 @@

LAB¶

- + @@ -565,7 +578,7 @@

LAB¶

- + @@ -576,35 +589,35 @@

LAB¶

- + - + - + - + - + @@ -614,14 +627,14 @@

LAB¶

- + - + @@ -646,14 +659,14 @@

LAB¶

- + - + @@ -666,7 +679,7 @@

LAB¶

- + @@ -676,7 +689,7 @@

LAB¶

- + @@ -687,7 +700,7 @@

LAB¶

- + @@ -698,7 +711,7 @@

LAB¶

- + @@ -709,7 +722,7 @@

LAB¶

- + @@ -720,35 +733,35 @@

LAB¶

- + - + - + - + - + @@ -758,14 +771,14 @@

LAB¶

- + - + @@ -776,14 +789,14 @@

LAB¶

- + - + @@ -794,28 +807,28 @@

LAB¶

- + - + - + - + @@ -826,14 +839,14 @@

LAB¶

- + - + @@ -844,14 +857,14 @@

LAB¶

- + - + @@ -862,7 +875,7 @@

LAB¶

- + @@ -873,7 +886,7 @@

LAB¶

- + @@ -884,7 +897,7 @@

LAB¶

- + @@ -903,14 +916,14 @@

LAB¶

Bool

- + - + @@ -921,21 +934,21 @@

LAB¶

- + - + - + @@ -946,28 +959,28 @@

LAB¶

- + - + - + - + @@ -981,7 +994,7 @@

LAB¶

Bool

- + @@ -992,14 +1005,14 @@

LAB¶

- + - + @@ -1010,24 +1023,24 @@

LAB¶

- + - +

Name

lut

TODO

Select whether the data input of the FF is the LUTs or the adder

BCLK_SEL

0-9

off

TODO

Select the clock input to the two bottom FFs

BCLR_SEL

0-9

0

TODO

Select the aclr input to the two bottom FFs

BDFF0

0-9

reg

TODO

Select between LUT and FF for that output

BDFF1

0-9

reg

TODO

Select between LUT and FF for that output

BDFF1L

0-9

reg

TODO

Select between LUT and FF for that output

BEF_SEL

0-9

e

TODO

Select which input goes to the sdata input of the two bottom FFs

BPKREG0

0-9

Bool

t/f

f

TODO

Force the top FF of the bottom half to get its input from tef_sel

BPKREG1

0-9

Bool

t/f

f

TODO

Force the bottom FF of the bottom half to get its input from tef_sel

BSCLR_DIS

0-9

Bool

t/f

f

TODO

Disable sync clear for the bottom half

BSLOAD_EN

0-9

Bool

t/f

f

TODO

Select whether to enable the sync load line of the two bottom FFs

B_FEEDBACK_SEL

0-9

0

TODO

Select which of the FFs goes to the bottom feedback line

LUT_MASK

0-9

Ram

64 bits

0

TODO

LUT values, A has bits 0-15, B 16-23, C 24-31, D 32-47, E 48-55. F 56-63

MODE

0-9

l6

TODO

Connectivity mode of the cell

SHARE

0-9

Bool

t/f

f

TODO

Route the share line to the addition

TCLK_SEL

0-9

off

TODO

Select the clock input to the two top FFs

TCLR_SEL

0-9

0

TODO

Select the aclr input to the two top FFs

TDFF0

0-9

reg

TODO

Select between LUT and FF for that output

TDFF1

0-9

reg

TODO

Select between LUT and FF for that output

TDFF1L

0-9

reg

TODO

Select between LUT and FF for that output

TEF_SEL

0-9

e

TODO

Select which input goes to the sdata input of the two top FFs

TPKREG0

0-9

Bool

t/f

f

TODO

Force the top FF of the top half to get its input from tef_sel

TPKREG1

0-9

Bool

t/f

f

TODO

Force the bottom FF of the top half to get its input from tef_sel

TSCLR_DIS

0-9

Bool

t/f

f

TODO

Disable sync clear for the top half

TSLOAD_EN

0-9

Bool

t/f

f

TODO

Select whether to enable the sync load line of the two top FFs

T_FEEDBACK_SEL

0-9

0

TODO

Select which of the FFs goes to the top feedback line

ACLR0_INV

Bool

t/f

f

TODO

Optional inverter for asynchronous clear 0

ACLR0_SEL

gin1

TODO

Selects between clock and data for async clear 0

ACLR1_INV

Bool

t/f

f

TODO

Optional inverter for asynchronous clear 1

ACLR1_SEL

gin0

TODO

Selects between clock and data for async clear 1

BTO_DIS

Bool

t/f

f

TODO

Something to do with inter-block carry or share

BYPASS_DIS

Bool

t/f

t

TODO

Something to do with inter-block carry or share

CLK0_INV

Bool

t/f

f

TODO

Optional inverter for clock 0

CLK0_SEL

clka

TODO

Selects between the two intermedaite clock lines for clock 0

CLK1_INV

Bool

t/f

f

TODO

Optional inverter for clock 1

CLK1_SEL

clka

TODO

Selects between the two intermedaite clock lines for clock 1

CLK2_INV

Bool

t/f

f

TODO

Optional inverter for clock 2

CLK2_SEL

clka

TODO

Selects between the two intermedaite clock lines for clock 2

CLKA_SEL

clki0

TODO

Selects between clock and data for the clka intermediate line

CLKB_SEL

clki1

TODO

Selects between clock and data for the clkb intermediate line

DFT_MODE

t/f

t

TODO

Enables the enable 0 line (else always on)

EN0_NINV

Bool

t/f

t

TODO

Optional inverter for enable 0

EN0_SEL

gin1

TODO

Source selection for enable 0

EN1_EN

Bool

t/f

t

TODO

Enables the enable 1 line (else always on)

EN1_NINV

Bool

t/f

t

TODO

Optional inverter for enable 1

EN1_SEL

gin3

TODO

Source selection for enable 1

EN2_EN

Bool

t/f

t

TODO

Enables the enable 2 line (else always on)

EN2_NINV

Bool

t/f

t

TODO

Optional inverter for enable 2

EN_SCLK_LOAD_WHAT

Bool

t/f

f

TODO

Unclear, possibly source selection for enable 2

REGSCAN_LATCH_EN

t/f

f

TODO

Optional inverter for synchronous clear

SCLR_MUX

gin3

TODO

Source selection for sync clear, possibly more subtle (interaction with en2 and sload)

SLOAD_INV

Bool

t/f

t

TODO

Optional inverter for synchronous load

SLOAD_SEL

gin0

TODO

Source selection for sync load, possibly more subtle (interaction with en2 and sclr)

TTO_DIS

Bool

t/f

f

TODO

Something to do with inter-block carry or share
-----+++++ @@ -1042,103 +1055,103 @@

LAB¶

0-9

- + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - +

Port Name

GOUT

TODO

Data input to the lab cell

ACLR

0-1

TCLK

TODO

Common clock inputs for asynchronous clear of the FFs

B

0-9

GOUT

TODO

Data input to the lab cell

C

0-9

GOUT

TODO

Data input to the lab cell

CLKIN

0-1

TCLK

TODO

Common clock inputs for clocking of the FFs

D

0-9

GOUT

TODO

Data input to the lab cell

DATAIN

0-3

GOUT

TODO

Common data inputs for enables, sync clear and load

E0

0-9

GOUT

TODO

Data input to the lab cell

E1

0-9

GOUT

TODO

Data input to the lab cell

F0

0-9

GOUT

TODO

Data input to the lab cell

F1

0-9

GOUT

TODO

Data input to the lab cell

FFB0

0-9

GIN

TODO

Output from either the top FF of the bottom hslf of the lab cell or the bottomlut to data routing

FFB1

0-9

GIN

TODO

Output from either the bottom FF of the bottom hslf of the lab cell or the bottom lut to data routing

FFB1L

0-9

LD

TODO

Output from either the bottom FF of the bottom hslf of the lab cell or the bottom lut to local dispatch

FFT0

0-9

GIN

TODO

Output from either the top FF of the top hslf of the lab cell or the top lut to data routing

FFT1

0-9

GIN

TODO

Output from either the bottom FF of the top hslf of the lab cell or the top lut to data routing

FFT1L

0-9

LD

TODO

Output from either the bottom FF of the top hslf of the lab cell or the top lut to local dispatch
diff --git a/docs-pdf/mistral.pdf b/docs-pdf/mistral.pdf index 2a6a2f3..c0b1604 100644 Binary files a/docs-pdf/mistral.pdf and b/docs-pdf/mistral.pdf differ diff --git a/docs/cyclonev_details.rst b/docs/cyclonev_details.rst index da8839b..eff1606 100644 --- a/docs/cyclonev_details.rst +++ b/docs/cyclonev_details.rst @@ -73,10 +73,29 @@ LAB ^^^ The LABs are the main combinatorial and register blocks of the FPGA. -A LAB tile includes 10 sub-blocks with 64 bits of LUT splitted in 6 -parts, four Flip-Flops, two 1-bit adders and a lot of routing logic. -In addition a common control subblock selects and dispatches clock, -enable, clear, etc signals. +A LAB tile includes 10 sub-blocks called cells with 64 bits of LUT +splitted in 6 parts, four Flip-Flops, two 1-bit adders and a lot of +routing logic. In addition a common control subblock selects and +dispatches clock, enable, clear, etc signals. + +.. figure:: lab-common.* + :width: 50% + + The part of the LAB shared by all ten cells that generates the + common signals. + + +.. figure:: lab-cell.* + :width: 100% + + One of the 10 cells of the LAB. + + +.. figure:: lab-modes.* + :width: 100% + + The 16 possible interconnection modes. + .. include:: gendoc/lab-dmux.rst diff --git a/docs/gendoc/lab-dmux.rst b/docs/gendoc/lab-dmux.rst index 6a86ced..8cab35d 100644 --- a/docs/gendoc/lab-dmux.rst +++ b/docs/gendoc/lab-dmux.rst @@ -1,158 +1,158 @@ -+-------------------+----------+------+-------------+---------+---------------+ -| Name | Instance | Type | Values | Default | Documentation | -+===================+==========+======+=============+=========+===============+ -| ARITH_SEL | 0-9 | Mux | - adder | lut | TODO | -| | | | - lut | | | -+-------------------+----------+------+-------------+---------+---------------+ -| BCLK_SEL | 0-9 | Mux | - off | off | TODO | -| | | | - clk0 | | | -| | | | - clk1 | | | -| | | | - clk2 | | | -+-------------------+----------+------+-------------+---------+---------------+ -| BCLR_SEL | 0-9 | Num | - 0-1 | 0 | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| BDFF0 | 0-9 | Mux | - reg | reg | TODO | -| | | | - nlut | | | -+-------------------+----------+------+-------------+---------+---------------+ -| BDFF1 | 0-9 | Mux | - reg | reg | TODO | -| | | | - nlut | | | -+-------------------+----------+------+-------------+---------+---------------+ -| BDFF1L | 0-9 | Mux | - reg | reg | TODO | -| | | | - nlut | | | -+-------------------+----------+------+-------------+---------+---------------+ -| BEF_SEL | 0-9 | Mux | - e | e | TODO | -| | | | - f | | | -+-------------------+----------+------+-------------+---------+---------------+ -| BPKREG0 | 0-9 | Bool | t/f | f | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| BPKREG1 | 0-9 | Bool | t/f | f | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| BSCLR_DIS | 0-9 | Bool | t/f | f | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| BSLOAD_EN | 0-9 | Bool | t/f | f | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| B_FEEDBACK_SEL | 0-9 | Num | - 0-1 | 0 | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| LUT_MASK | 0-9 | Ram | 64 bits | 0 | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| MODE | 0-9 | Mux | - l5 | l6 | TODO | -| | | | - l5_ft | | | -| | | | - l5_fb | | | -| | | | - l5_ftb | | | -| | | | - l6 | | | -| | | | - l6_ft | | | -| | | | - l6_fb | | | -| | | | - l6_ftb | | | -| | | | - l7_e0 | | | -| | | | - l7_e0_ft | | | -| | | | - l7_e0_fb | | | -| | | | - l7_e0_ftb | | | -| | | | - l7_e1 | | | -| | | | - l7_e1_ft | | | -| | | | - l7_e1_fb | | | -| | | | - l7_e1_ftb | | | -+-------------------+----------+------+-------------+---------+---------------+ -| SHARE | 0-9 | Bool | t/f | f | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| TCLK_SEL | 0-9 | Mux | - off | off | TODO | -| | | | - clk0 | | | -| | | | - clk1 | | | -| | | | - clk2 | | | -+-------------------+----------+------+-------------+---------+---------------+ -| TCLR_SEL | 0-9 | Num | - 0-1 | 0 | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| TDFF0 | 0-9 | Mux | - reg | reg | TODO | -| | | | - nlut | | | -+-------------------+----------+------+-------------+---------+---------------+ -| TDFF1 | 0-9 | Mux | - reg | reg | TODO | -| | | | - nlut | | | -+-------------------+----------+------+-------------+---------+---------------+ -| TDFF1L | 0-9 | Mux | - reg | reg | TODO | -| | | | - nlut | | | -+-------------------+----------+------+-------------+---------+---------------+ -| TEF_SEL | 0-9 | Mux | - e | e | TODO | -| | | | - f | | | -+-------------------+----------+------+-------------+---------+---------------+ -| TPKREG0 | 0-9 | Bool | t/f | f | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| TPKREG1 | 0-9 | Bool | t/f | f | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| TSCLR_DIS | 0-9 | Bool | t/f | f | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| TSLOAD_EN | 0-9 | Bool | t/f | f | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| T_FEEDBACK_SEL | 0-9 | Num | - 0-1 | 0 | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| ACLR0_INV | | Bool | t/f | f | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| ACLR0_SEL | | Mux | - gin1 | gin1 | TODO | -| | | | - clki2 | | | -+-------------------+----------+------+-------------+---------+---------------+ -| ACLR1_INV | | Bool | t/f | f | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| ACLR1_SEL | | Mux | - gin0 | gin0 | TODO | -| | | | - clki3 | | | -+-------------------+----------+------+-------------+---------+---------------+ -| BTO_DIS | | Bool | t/f | f | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| BYPASS_DIS | | Bool | t/f | t | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| CLK0_INV | | Bool | t/f | f | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| CLK0_SEL | | Mux | - clka | clka | TODO | -| | | | - clkb | | | -+-------------------+----------+------+-------------+---------+---------------+ -| CLK1_INV | | Bool | t/f | f | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| CLK1_SEL | | Mux | - clka | clka | TODO | -| | | | - clkb | | | -+-------------------+----------+------+-------------+---------+---------------+ -| CLK2_INV | | Bool | t/f | f | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| CLK2_SEL | | Mux | - clka | clka | TODO | -| | | | - clkb | | | -+-------------------+----------+------+-------------+---------+---------------+ -| CLKA_SEL | | Mux | - clki0 | clki0 | TODO | -| | | | - gin2 | | | -+-------------------+----------+------+-------------+---------+---------------+ -| CLKB_SEL | | Mux | - clki1 | clki1 | TODO | -| | | | - gin3 | | | -+-------------------+----------+------+-------------+---------+---------------+ -| DFT_MODE | | Mux | - off | on | TODO | -| | | | - on | | | -| | | | - dft_pprog | | | -+-------------------+----------+------+-------------+---------+---------------+ -| EN0_EN | | Bool | t/f | t | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| EN0_NINV | | Bool | t/f | t | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| EN0_SEL | | Mux | - gin1 | gin1 | TODO | -| | | | - gin3 | | | -+-------------------+----------+------+-------------+---------+---------------+ -| EN1_EN | | Bool | t/f | t | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| EN1_NINV | | Bool | t/f | t | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| EN1_SEL | | Mux | - gin0 | gin3 | TODO | -| | | | - gin3 | | | -+-------------------+----------+------+-------------+---------+---------------+ -| EN2_EN | | Bool | t/f | t | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| EN2_NINV | | Bool | t/f | t | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| EN_SCLK_LOAD_WHAT | | Bool | t/f | f | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| REGSCAN_LATCH_EN | | Bool | t/f | f | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| SCLR_INV | | Bool | t/f | f | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| SCLR_MUX | | Mux | - gin3 | gin3 | TODO | -| | | | - gin2 | | | -+-------------------+----------+------+-------------+---------+---------------+ -| SLOAD_INV | | Bool | t/f | t | TODO | -+-------------------+----------+------+-------------+---------+---------------+ -| SLOAD_SEL | | Mux | - gin0 | gin0 | TODO | -| | | | - gin3 | | | -+-------------------+----------+------+-------------+---------+---------------+ -| TTO_DIS | | Bool | t/f | f | TODO | -+-------------------+----------+------+-------------+---------+---------------+ ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| Name | Instance | Type | Values | Default | Documentation | ++===================+==========+======+=============+=========+========================================================================================+ +| ARITH_SEL | 0-9 | Mux | - adder | lut | Select whether the data input of the FF is the LUTs or the adder | +| | | | - lut | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| BCLK_SEL | 0-9 | Mux | - off | off | Select the clock input to the two bottom FFs | +| | | | - clk0 | | | +| | | | - clk1 | | | +| | | | - clk2 | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| BCLR_SEL | 0-9 | Num | - 0-1 | 0 | Select the aclr input to the two bottom FFs | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| BDFF0 | 0-9 | Mux | - reg | reg | Select between LUT and FF for that output | +| | | | - nlut | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| BDFF1 | 0-9 | Mux | - reg | reg | Select between LUT and FF for that output | +| | | | - nlut | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| BDFF1L | 0-9 | Mux | - reg | reg | Select between LUT and FF for that output | +| | | | - nlut | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| BEF_SEL | 0-9 | Mux | - e | e | Select which input goes to the sdata input of the two bottom FFs | +| | | | - f | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| BPKREG0 | 0-9 | Bool | t/f | f | Force the top FF of the bottom half to get its input from tef_sel | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| BPKREG1 | 0-9 | Bool | t/f | f | Force the bottom FF of the bottom half to get its input from tef_sel | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| BSCLR_DIS | 0-9 | Bool | t/f | f | Disable sync clear for the bottom half | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| BSLOAD_EN | 0-9 | Bool | t/f | f | Select whether to enable the sync load line of the two bottom FFs | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| B_FEEDBACK_SEL | 0-9 | Num | - 0-1 | 0 | Select which of the FFs goes to the bottom feedback line | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| LUT_MASK | 0-9 | Ram | 64 bits | 0 | LUT values, A has bits 0-15, B 16-23, C 24-31, D 32-47, E 48-55. F 56-63 | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| MODE | 0-9 | Mux | - l5 | l6 | Connectivity mode of the cell | +| | | | - l5_ft | | | +| | | | - l5_fb | | | +| | | | - l5_ftb | | | +| | | | - l6 | | | +| | | | - l6_ft | | | +| | | | - l6_fb | | | +| | | | - l6_ftb | | | +| | | | - l7_e0 | | | +| | | | - l7_e0_ft | | | +| | | | - l7_e0_fb | | | +| | | | - l7_e0_ftb | | | +| | | | - l7_e1 | | | +| | | | - l7_e1_ft | | | +| | | | - l7_e1_fb | | | +| | | | - l7_e1_ftb | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| SHARE | 0-9 | Bool | t/f | f | Route the share line to the addition | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| TCLK_SEL | 0-9 | Mux | - off | off | Select the clock input to the two top FFs | +| | | | - clk0 | | | +| | | | - clk1 | | | +| | | | - clk2 | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| TCLR_SEL | 0-9 | Num | - 0-1 | 0 | Select the aclr input to the two top FFs | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| TDFF0 | 0-9 | Mux | - reg | reg | Select between LUT and FF for that output | +| | | | - nlut | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| TDFF1 | 0-9 | Mux | - reg | reg | Select between LUT and FF for that output | +| | | | - nlut | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| TDFF1L | 0-9 | Mux | - reg | reg | Select between LUT and FF for that output | +| | | | - nlut | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| TEF_SEL | 0-9 | Mux | - e | e | Select which input goes to the sdata input of the two top FFs | +| | | | - f | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| TPKREG0 | 0-9 | Bool | t/f | f | Force the top FF of the top half to get its input from tef_sel | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| TPKREG1 | 0-9 | Bool | t/f | f | Force the bottom FF of the top half to get its input from tef_sel | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| TSCLR_DIS | 0-9 | Bool | t/f | f | Disable sync clear for the top half | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| TSLOAD_EN | 0-9 | Bool | t/f | f | Select whether to enable the sync load line of the two top FFs | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| T_FEEDBACK_SEL | 0-9 | Num | - 0-1 | 0 | Select which of the FFs goes to the top feedback line | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| ACLR0_INV | | Bool | t/f | f | Optional inverter for asynchronous clear 0 | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| ACLR0_SEL | | Mux | - gin1 | gin1 | Selects between clock and data for async clear 0 | +| | | | - clki2 | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| ACLR1_INV | | Bool | t/f | f | Optional inverter for asynchronous clear 1 | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| ACLR1_SEL | | Mux | - gin0 | gin0 | Selects between clock and data for async clear 1 | +| | | | - clki3 | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| BTO_DIS | | Bool | t/f | f | Something to do with inter-block carry or share | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| BYPASS_DIS | | Bool | t/f | t | Something to do with inter-block carry or share | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| CLK0_INV | | Bool | t/f | f | Optional inverter for clock 0 | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| CLK0_SEL | | Mux | - clka | clka | Selects between the two intermedaite clock lines for clock 0 | +| | | | - clkb | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| CLK1_INV | | Bool | t/f | f | Optional inverter for clock 1 | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| CLK1_SEL | | Mux | - clka | clka | Selects between the two intermedaite clock lines for clock 1 | +| | | | - clkb | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| CLK2_INV | | Bool | t/f | f | Optional inverter for clock 2 | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| CLK2_SEL | | Mux | - clka | clka | Selects between the two intermedaite clock lines for clock 2 | +| | | | - clkb | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| CLKA_SEL | | Mux | - clki0 | clki0 | Selects between clock and data for the clka intermediate line | +| | | | - gin2 | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| CLKB_SEL | | Mux | - clki1 | clki1 | Selects between clock and data for the clkb intermediate line | +| | | | - gin3 | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| DFT_MODE | | Mux | - off | on | TODO | +| | | | - on | | | +| | | | - dft_pprog | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| EN0_EN | | Bool | t/f | t | Enables the enable 0 line (else always on) | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| EN0_NINV | | Bool | t/f | t | Optional inverter for enable 0 | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| EN0_SEL | | Mux | - gin1 | gin1 | Source selection for enable 0 | +| | | | - gin3 | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| EN1_EN | | Bool | t/f | t | Enables the enable 1 line (else always on) | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| EN1_NINV | | Bool | t/f | t | Optional inverter for enable 1 | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| EN1_SEL | | Mux | - gin0 | gin3 | Source selection for enable 1 | +| | | | - gin3 | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| EN2_EN | | Bool | t/f | t | Enables the enable 2 line (else always on) | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| EN2_NINV | | Bool | t/f | t | Optional inverter for enable 2 | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| EN_SCLK_LOAD_WHAT | | Bool | t/f | f | Unclear, possibly source selection for enable 2 | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| REGSCAN_LATCH_EN | | Bool | t/f | f | TODO | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| SCLR_INV | | Bool | t/f | f | Optional inverter for synchronous clear | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| SCLR_MUX | | Mux | - gin3 | gin3 | Source selection for sync clear, possibly more subtle (interaction with en2 and sload) | +| | | | - gin2 | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| SLOAD_INV | | Bool | t/f | t | Optional inverter for synchronous load | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| SLOAD_SEL | | Mux | - gin0 | gin0 | Source selection for sync load, possibly more subtle (interaction with en2 and sclr) | +| | | | - gin3 | | | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ +| TTO_DIS | | Bool | t/f | f | Something to do with inter-block carry or share | ++-------------------+----------+------+-------------+---------+----------------------------------------------------------------------------------------+ diff --git a/docs/gendoc/lab-dp2r.rst b/docs/gendoc/lab-dp2r.rst index 8cb2120..6b53d96 100644 --- a/docs/gendoc/lab-dp2r.rst +++ b/docs/gendoc/lab-dp2r.rst @@ -1,37 +1,37 @@ -+-----------+----------+-----------+-----------------+---------------+ -| Port Name | Instance | Port bits | Route node type | Documentation | -+===========+==========+===========+=================+===============+ -| A | 0-9 | | GOUT | TODO | -+-----------+----------+-----------+-----------------+---------------+ -| ACLR | | 0-1 | TCLK | TODO | -+-----------+----------+-----------+-----------------+---------------+ -| B | 0-9 | | GOUT | TODO | -+-----------+----------+-----------+-----------------+---------------+ -| C | 0-9 | | GOUT | TODO | -+-----------+----------+-----------+-----------------+---------------+ -| CLKIN | | 0-1 | TCLK | TODO | -+-----------+----------+-----------+-----------------+---------------+ -| D | 0-9 | | GOUT | TODO | -+-----------+----------+-----------+-----------------+---------------+ -| DATAIN | | 0-3 | GOUT | TODO | -+-----------+----------+-----------+-----------------+---------------+ -| E0 | 0-9 | | GOUT | TODO | -+-----------+----------+-----------+-----------------+---------------+ -| E1 | 0-9 | | GOUT | TODO | -+-----------+----------+-----------+-----------------+---------------+ -| F0 | 0-9 | | GOUT | TODO | -+-----------+----------+-----------+-----------------+---------------+ -| F1 | 0-9 | | GOUT | TODO | -+-----------+----------+-----------+-----------------+---------------+ -| FFB0 | 0-9 | | GIN | TODO | -+-----------+----------+-----------+-----------------+---------------+ -| FFB1 | 0-9 | | GIN | TODO | -+-----------+----------+-----------+-----------------+---------------+ -| FFB1L | 0-9 | | LD | TODO | -+-----------+----------+-----------+-----------------+---------------+ -| FFT0 | 0-9 | | GIN | TODO | -+-----------+----------+-----------+-----------------+---------------+ -| FFT1 | 0-9 | | GIN | TODO | -+-----------+----------+-----------+-----------------+---------------+ -| FFT1L | 0-9 | | LD | TODO | -+-----------+----------+-----------+-----------------+---------------+ ++-----------+----------+-----------+-----------------+---------------------------------------------------------------------------------------------------------+ +| Port Name | Instance | Port bits | Route node type | Documentation | ++===========+==========+===========+=================+=========================================================================================================+ +| A | 0-9 | | GOUT | Data input to the lab cell | ++-----------+----------+-----------+-----------------+---------------------------------------------------------------------------------------------------------+ +| ACLR | | 0-1 | TCLK | Common clock inputs for asynchronous clear of the FFs | ++-----------+----------+-----------+-----------------+---------------------------------------------------------------------------------------------------------+ +| B | 0-9 | | GOUT | Data input to the lab cell | ++-----------+----------+-----------+-----------------+---------------------------------------------------------------------------------------------------------+ +| C | 0-9 | | GOUT | Data input to the lab cell | ++-----------+----------+-----------+-----------------+---------------------------------------------------------------------------------------------------------+ +| CLKIN | | 0-1 | TCLK | Common clock inputs for clocking of the FFs | ++-----------+----------+-----------+-----------------+---------------------------------------------------------------------------------------------------------+ +| D | 0-9 | | GOUT | Data input to the lab cell | ++-----------+----------+-----------+-----------------+---------------------------------------------------------------------------------------------------------+ +| DATAIN | | 0-3 | GOUT | Common data inputs for enables, sync clear and load | ++-----------+----------+-----------+-----------------+---------------------------------------------------------------------------------------------------------+ +| E0 | 0-9 | | GOUT | Data input to the lab cell | ++-----------+----------+-----------+-----------------+---------------------------------------------------------------------------------------------------------+ +| E1 | 0-9 | | GOUT | Data input to the lab cell | ++-----------+----------+-----------+-----------------+---------------------------------------------------------------------------------------------------------+ +| F0 | 0-9 | | GOUT | Data input to the lab cell | ++-----------+----------+-----------+-----------------+---------------------------------------------------------------------------------------------------------+ +| F1 | 0-9 | | GOUT | Data input to the lab cell | ++-----------+----------+-----------+-----------------+---------------------------------------------------------------------------------------------------------+ +| FFB0 | 0-9 | | GIN | Output from either the top FF of the bottom hslf of the lab cell or the bottomlut to data routing | ++-----------+----------+-----------+-----------------+---------------------------------------------------------------------------------------------------------+ +| FFB1 | 0-9 | | GIN | Output from either the bottom FF of the bottom hslf of the lab cell or the bottom lut to data routing | ++-----------+----------+-----------+-----------------+---------------------------------------------------------------------------------------------------------+ +| FFB1L | 0-9 | | LD | Output from either the bottom FF of the bottom hslf of the lab cell or the bottom lut to local dispatch | ++-----------+----------+-----------+-----------------+---------------------------------------------------------------------------------------------------------+ +| FFT0 | 0-9 | | GIN | Output from either the top FF of the top hslf of the lab cell or the top lut to data routing | ++-----------+----------+-----------+-----------------+---------------------------------------------------------------------------------------------------------+ +| FFT1 | 0-9 | | GIN | Output from either the bottom FF of the top hslf of the lab cell or the top lut to data routing | ++-----------+----------+-----------+-----------------+---------------------------------------------------------------------------------------------------------+ +| FFT1L | 0-9 | | LD | Output from either the bottom FF of the top hslf of the lab cell or the top lut to local dispatch | ++-----------+----------+-----------+-----------------+---------------------------------------------------------------------------------------------------------+ diff --git a/docs/lab-cell.pdf b/docs/lab-cell.pdf new file mode 100644 index 0000000..c718a99 Binary files /dev/null and b/docs/lab-cell.pdf differ diff --git a/docs/lab-cell.svg b/docs/lab-cell.svg new file mode 100644 index 0000000..a5571aa --- /dev/null +++ b/docs/lab-cell.svg @@ -0,0 +1,4534 @@ + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + F1 + + + + + + + + A + + + + + + + + + B + + + + + + + + + C + + + + + + + + + D + + + + + + + + + E0 + + + + + + + + + E1 + + + + + + + + F0 + + + + + + + + + + + LUT4 + + A + + + LUT3 + B + + + + + + LUT3 + C + + + + + + + + + LUT4 + D + + LUT3 + E + + + LUT3 + F + + A0 + A1 + A2 + A3 + A0 + A1 + A2 + A3 + A0 + A1 + A2 + A0 + A1 + A2 + A0 + A1 + A2 + A0 + A1 + A2 + + + + + + + + + + + + + + + + share + t + f + + + + + + + SHARE + + + + + + + + + + + + + + + + + + + + + 00 + 01 + 10 + 11 + + + + + + 00 + 01 + 10 + 11 + + + + + + + Adder + + I0 + I1 + I2 + S + C + + + + Adder + I0 + I1 + I2 + S + C + + + + + + share + t + f + + + + + + + + + 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b/docs/srcdoc/lab-doc.txt index 879d18a..007ee2a 100644 --- a/docs/srcdoc/lab-doc.txt +++ b/docs/srcdoc/lab-doc.txt @@ -1,56 +1,56 @@ -tdff0 -tdff1 -tdff1l -bdff0 -bdff1 -bdff1l -tsload_en -tsclr_dis -tpkreg0 -tpkreg1 -tclk_sel -tclr_sel -tef_sel -bsload_en -bsclr_dis -bpkreg0 -bpkreg1 -bclk_sel -bclr_sel -bef_sel -share -t_feedback_sel -b_feedback_sel -arith_sel -mode -lut_mask -en0_en -en1_en -en2_en +tdff0 Select between LUT and FF for that output +tdff1 Select between LUT and FF for that output +tdff1l Select between LUT and FF for that output +bdff0 Select between LUT and FF for that output +bdff1 Select between LUT and FF for that output +bdff1l Select between LUT and FF for that output +tsload_en Select whether to enable the sync load line of the two top FFs +tsclr_dis Disable sync clear for the top half +tpkreg0 Force the top FF of the top half to get its input from tef_sel +tpkreg1 Force the bottom FF of the top half to get its input from tef_sel +tclk_sel Select the clock input to the two top FFs +tclr_sel Select the aclr input to the two top FFs +tef_sel Select which input goes to the sdata input of the two top FFs +bsload_en Select whether to enable the sync load line of the two bottom FFs +bsclr_dis Disable sync clear for the bottom half +bpkreg0 Force the top FF of the bottom half to get its input from tef_sel +bpkreg1 Force the bottom FF of the bottom half to get its input from tef_sel +bclk_sel Select the clock input to the two bottom FFs +bclr_sel Select the aclr input to the two bottom FFs +bef_sel Select which input goes to the sdata input of the two bottom FFs +share Route the share line to the addition +t_feedback_sel Select which of the FFs goes to the top feedback line +b_feedback_sel Select which of the FFs goes to the bottom feedback line +arith_sel Select whether the data input of the FF is the LUTs or the adder +mode Connectivity mode of the cell +lut_mask LUT values, A has bits 0-15, B 16-23, C 24-31, D 32-47, E 48-55. F 56-63 +en0_en Enables the enable 0 line (else always on) +en1_en Enables the enable 1 line (else always on) +en2_en Enables the enable 2 line (else always on) dft_mode -clka_sel -clkb_sel -clk0_sel -clk0_inv -clk1_sel -clk1_inv -clk2_sel -clk2_inv -en0_ninv -en1_ninv -en2_ninv +clka_sel Selects between clock and data for the clka intermediate line +clkb_sel Selects between clock and data for the clkb intermediate line +clk0_sel Selects between the two intermedaite clock lines for clock 0 +clk0_inv Optional inverter for clock 0 +clk1_sel Selects between the two intermedaite clock lines for clock 1 +clk1_inv Optional inverter for clock 1 +clk2_sel Selects between the two intermedaite clock lines for clock 2 +clk2_inv Optional inverter for clock 2 +en0_ninv Optional inverter for enable 0 +en1_ninv Optional inverter for enable 1 +en2_ninv Optional inverter for enable 2 regscan_latch_en -en0_sel -en1_sel -en_sclk_load_what -sclr_mux -sclr_inv -sload_sel -sload_inv -aclr0_sel -aclr0_inv -aclr1_sel -aclr1_inv -bypass_dis -tto_dis -bto_dis +en0_sel Source selection for enable 0 +en1_sel Source selection for enable 1 +en_sclk_load_what Unclear, possibly source selection for enable 2 +sclr_mux Source selection for sync clear, possibly more subtle (interaction with en2 and sload) +sclr_inv Optional inverter for synchronous clear +sload_sel Source selection for sync load, possibly more subtle (interaction with en2 and sclr) +sload_inv Optional inverter for synchronous load +aclr0_sel Selects between clock and data for async clear 0 +aclr0_inv Optional inverter for asynchronous clear 0 +aclr1_sel Selects between clock and data for async clear 1 +aclr1_inv Optional inverter for asynchronous clear 1 +bypass_dis Something to do with inter-block carry or share +tto_dis Something to do with inter-block carry or share +bto_dis Something to do with inter-block carry or share diff --git a/docs/srcdoc/p2r-doc.txt b/docs/srcdoc/p2r-doc.txt index e69de29..b2fd7c2 100644 --- a/docs/srcdoc/p2r-doc.txt +++ b/docs/srcdoc/p2r-doc.txt @@ -0,0 +1,17 @@ +lab.a Data input to the lab cell +lab.b Data input to the lab cell +lab.c Data input to the lab cell +lab.d Data input to the lab cell +lab.e0 Data input to the lab cell +lab.e1 Data input to the lab cell +lab.f0 Data input to the lab cell +lab.f1 Data input to the lab cell +lab.fft0 Output from either the top FF of the top hslf of the lab cell or the top lut to data routing +lab.fft1 Output from either the bottom FF of the top hslf of the lab cell or the top lut to data routing +lab.fft1l Output from either the bottom FF of the top hslf of the lab cell or the top lut to local dispatch +lab.ffb0 Output from either the top FF of the bottom hslf of the lab cell or the bottomlut to data routing +lab.ffb1 Output from either the bottom FF of the bottom hslf of the lab cell or the bottom lut to data routing +lab.ffb1l Output from either the bottom FF of the bottom hslf of the lab cell or the bottom lut to local dispatch +lab.aclr Common clock inputs for asynchronous clear of the FFs +lab.clkin Common clock inputs for clocking of the FFs +lab.datain Common data inputs for enables, sync clear and load