From 7c289385b84d136089b8a1149321ebffa5193595 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 5 Feb 2011 10:41:55 +0000 Subject: [PATCH] ALSA: AACI: allow writes to MAINCR to take effect The AACI TRM requires the MAINCR enable bit to be held zero for two bitclk cycles plus three apb_pclk cycles. Use a delay of 1us to ensure this. Ensure that writes to MAINCR to change the addressed codec only happen when required, and that they take effect in a similar manner to the above, otherwise we seem to occasionally have stuck slot busy bits. Signed-off-by: Russell King --- sound/arm/aaci.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/sound/arm/aaci.c b/sound/arm/aaci.c index 24d3013c02312e..7c1fc64cb53d85 100644 --- a/sound/arm/aaci.c +++ b/sound/arm/aaci.c @@ -50,7 +50,11 @@ static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97) if (v & SLFR_1RXV) readl(aaci->base + AACI_SL1RX); - writel(maincr, aaci->base + AACI_MAINCR); + if (maincr != readl(aaci->base + AACI_MAINCR)) { + writel(maincr, aaci->base + AACI_MAINCR); + readl(aaci->base + AACI_MAINCR); + udelay(1); + } } /* @@ -993,6 +997,8 @@ static unsigned int __devinit aaci_size_fifo(struct aaci *aaci) * disabling the channel doesn't clear the FIFO. */ writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR); + readl(aaci->base + AACI_MAINCR); + udelay(1); writel(aaci->maincr, aaci->base + AACI_MAINCR); /*