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Commits on Oct 21, 2019

• [DV] Update simulation terminate argument

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  towoe

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  0728fb7

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• [DV] testplan documentation (lowRISC#409)

  

  udinator

  authored
  c808fed

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• [DV] Add interrupt wfi test to address coverage hole (lowRISC#410)

  

  udinator

  authored
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Commits on Oct 17, 2019

• Tracer: Decode an all-zero instruction as c.unimp

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  imphil

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• Add Greg Chadwick to CREDITS.md

  GregAC

  committed
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• [Doc] Added extra setup info for Verification

  GregAC

  committed
  6b1a7ad

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• Update google_riscv-dv to chipsalliance/riscv-dv@033fccf (lowRISC#406)

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  udinator

  authored
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• [DV] Debug_ebreak test fix (lowRISC#405)

  

  udinator

  authored
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Commits on Oct 16, 2019

• Add RV32IM test (lowRISC#404)

  taoliug

  authored
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• Licensing documentation: Add commercial support info

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  imphil

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• Improve copyright/licensing page

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  imphil

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• [RTL] Fix single stepping on exceptions

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  GregAC

  committed
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• [RTL] Fix ebreak behaviour in U-mode

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  GregAC

  committed
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• [RTL] Fix ebreak and cleanup debug

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  GregAC

  committed
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Commits on Oct 15, 2019

• [DV] Fix bugs in mem_error test to circumvent test deadlock (lowRISC#400)

  

  udinator

  authored
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• [RTL] Prevent CSR write on any illegal CSR reason

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  GregAC

  committed
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Commits on Oct 14, 2019

• [DV] Fix lint warnings (lowRISC#397)

  

  udinator

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• Remove non-ASCII characters from .sv and .rst files

  vogelpi

  committed
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Commits on Oct 11, 2019

• [DV] Let time-consuming checker tasks detect failures (lowRISC#395)

  

  udinator

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Commits on Oct 10, 2019

• [DV] Add reset test (lowRISC#392)

  

  udinator

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• [DV] Update csr description for U-mode changes (lowRISC#387)

  

  udinator

  authored
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• [RTL] Enable reading mstatus.tw (lowRISC#388)

  

  udinator

  authored
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• [CI] Stop pinning an old attrs version

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  asb

  committed
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Commits on Oct 9, 2019

• Remove outdated waiver

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  imphil

  committed
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• Tie off csr_pmp_* signals for all lint tools

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  imphil

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• Avoid self-determined bit length of signals

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  imphil

  committed
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• ibex_cs_registers: Add missing generate name

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  imphil

  committed
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• [RTL LSU] Change unaligned error behaviour

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  Tom Roberts

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  tomeroberts

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Commits on Oct 8, 2019

• Update google_riscv-dv to chipsalliance/riscv-dv@ad6fe56 (lowRISC#385)

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  udinator

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• [DV] Added unaligned memory error test (lowRISC#378)

  

  udinator

  authored
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• Update description for running RISC-V compliance

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  towoe

  committed
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• Remove reference to simulation

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  towoe

  committed
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Commits on Oct 6, 2019

• Tracer: Reference Verilator bug for miscompilation

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  imphil

  committed
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Commits on Oct 5, 2019

• Include rs1 and rd in trace of c.addi16sp

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  imphil

  committed
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Commits on Oct 4, 2019

• [DV] Top level toggle coverage (lowRISC#371)

  

  udinator

  authored
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