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Commits on Nov 5, 2019

• [DV] clean up stale TODOs (lowRISC#448)

  

  udinator

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  502b5a9

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Commits on Nov 4, 2019

• Update google_riscv-dv to chipsalliance/riscv-dv@44bec76 (lowRISC#447)

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  udinator

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  taoliug

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• [DV/flow] Integrate with RISCV-DV (lowRISC#446)

  

  udinator

  authored
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• Update google_riscv-dv to chipsalliance/riscv-dv@cce71d2 (lowRISC#445)

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  udinator

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Commits on Nov 1, 2019

• [verilator] Fix a few verilator DV issues

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  Tom Roberts

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  tomeroberts

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  48adda0

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• [rtl] Remove unused set-less-or-equal-than ALU ops

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  vogelpi

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  275c331

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Commits on Oct 31, 2019

• [DV] Assert interrupt during write to MSTATUS and MIE (lowRISC#435)

  

  udinator

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Commits on Oct 30, 2019

• Add performance counter utils for verilator sims

  GregAC

  committed
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• [DV] Add registers testbench

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  Tom Roberts

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  tomeroberts

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  70b5306

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Commits on Oct 28, 2019

• Error synthesis in Vivado

  

  Pascal Cotret

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  imphil

  committed
  e5cf0c0

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Commits on Oct 26, 2019

• [rtl/lsu] Rework assertion checking response valid

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  vogelpi

  committed
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Commits on Oct 25, 2019

• [DV] Increase number of resets in reset_test (lowRISC#418)

  

  udinator

  authored
  edf9371

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• [DV] Increase number of illegal instructions generated (lowRISC#426)

  

  udinator

  authored
  d3c7b88

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• [rtl/alu] Remove unused comparison operations

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  vogelpi

  committed
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Commits on Oct 24, 2019

• [RTL] Add MultiplierImplementation parameter in top level

  

  MarekPikula

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  imphil

  committed
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Commits on Oct 23, 2019

• Update google_riscv-dv to chipsalliance/riscv-dv@46ec4bc (lowRISC#417)

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  udinator

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• [RTL/Tracer] Fix compressed jump RD write (lowRISC#416)

  

  udinator

  authored
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• [DV] Enable timer interrupts (lowRISC#415)

  

  udinator

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Commits on Oct 21, 2019

• [DV] Update simulation terminate argument

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  towoe

  committed
  0728fb7

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• [DV] testplan documentation (lowRISC#409)

  

  udinator

  authored
  c808fed

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• [DV] Add interrupt wfi test to address coverage hole (lowRISC#410)

  

  udinator

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Commits on Oct 17, 2019

• Tracer: Decode an all-zero instruction as c.unimp

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  imphil

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  1c3903e

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• Add Greg Chadwick to CREDITS.md

  GregAC

  committed
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• [Doc] Added extra setup info for Verification

  GregAC

  committed
  6b1a7ad

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• Update google_riscv-dv to chipsalliance/riscv-dv@033fccf (lowRISC#406)

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  udinator

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• [DV] Debug_ebreak test fix (lowRISC#405)

  

  udinator

  authored
  fc80203

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Commits on Oct 16, 2019

• Add RV32IM test (lowRISC#404)

  taoliug

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  1b71320

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• Licensing documentation: Add commercial support info

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  imphil

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• Improve copyright/licensing page

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  imphil

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• [RTL] Fix single stepping on exceptions

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  GregAC

  committed
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• [RTL] Fix ebreak behaviour in U-mode

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  GregAC

  committed
  b949614

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• [RTL] Fix ebreak and cleanup debug

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  GregAC

  committed
  7aa8715

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Commits on Oct 15, 2019

• [DV] Fix bugs in mem_error test to circumvent test deadlock (lowRISC#400)

  

  udinator

  authored
  6b8b376

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• [RTL] Prevent CSR write on any illegal CSR reason

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  GregAC

  committed
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Commits on Oct 14, 2019

• [DV] Fix lint warnings (lowRISC#397)

  

  udinator

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