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main.out: file format elf32-littlearm
Disassembly of section .text:
00000000 <myvectors>:
0: 00 08 00 20 11 00 00 00 e5 00 00 00 f1 00 00 00 ... ............
00000010 <main>:
*
* Description: The main subroutine
*
*************************************************************************/
int main(void)
{
10: b580 push {r7, lr}
12: af00 add r7, sp, #0
*NVIC_CCR = *NVIC_CCR | 0x200; /* Set STKALIGN in NVIC */
14: f64e 5314 movw r3, #60692 ; 0xed14
18: f2ce 0300 movt r3, #57344 ; 0xe000
1c: f64e 5214 movw r2, #60692 ; 0xed14
20: f2ce 0200 movt r2, #57344 ; 0xe000
24: 6812 ldr r2, [r2, #0]
26: f442 7200 orr.w r2, r2, #512 ; 0x200
2a: 601a str r2, [r3, #0]
// Init clock system
Clk_Init();
2c: f000 f878 bl 120 <Clk_Init>
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
30: f04f 0001 mov.w r0, #1 ; 0x1
34: f04f 0101 mov.w r1, #1 ; 0x1
38: f000 fc46 bl 8c8 <RCC_APB2PeriphClockCmd>
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOA, ENABLE);
3c: f04f 0014 mov.w r0, #20 ; 0x14
40: f04f 0101 mov.w r1, #1 ; 0x1
44: f000 fc40 bl 8c8 <RCC_APB2PeriphClockCmd>
// Configure PC.12 as output push-pull (LED)
GPIO_WriteBit(GPIOC,GPIO_Pin_12,Bit_SET);
48: f241 0000 movw r0, #4096 ; 0x1000
4c: f2c4 0001 movt r0, #16385 ; 0x4001
50: f44f 5180 mov.w r1, #4096 ; 0x1000
54: f04f 0201 mov.w r2, #1 ; 0x1
58: f000 ff72 bl f40 <GPIO_WriteBit>
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
5c: f240 0300 movw r3, #0 ; 0x0
60: f2c2 0300 movt r3, #8192 ; 0x2000
64: f44f 5280 mov.w r2, #4096 ; 0x1000
68: 801a strh r2, [r3, #0]
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
6a: f240 0300 movw r3, #0 ; 0x0
6e: f2c2 0300 movt r3, #8192 ; 0x2000
72: f04f 0210 mov.w r2, #16 ; 0x10
76: 70da strb r2, [r3, #3]
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
78: f240 0300 movw r3, #0 ; 0x0
7c: f2c2 0300 movt r3, #8192 ; 0x2000
80: f04f 0203 mov.w r2, #3 ; 0x3
84: 709a strb r2, [r3, #2]
GPIO_Init(GPIOC, &GPIO_InitStructure);
86: f241 0000 movw r0, #4096 ; 0x1000
8a: f2c4 0001 movt r0, #16385 ; 0x4001
8e: f240 0100 movw r1, #0 ; 0x0
92: f2c2 0100 movt r1, #8192 ; 0x2000
96: f000 fe03 bl ca0 <GPIO_Init>
while(1)
{
GPIOC->BRR |= 0x00001000;
9a: f241 0300 movw r3, #4096 ; 0x1000
9e: f2c4 0301 movt r3, #16385 ; 0x4001
a2: f241 0200 movw r2, #4096 ; 0x1000
a6: f2c4 0201 movt r2, #16385 ; 0x4001
aa: 6952 ldr r2, [r2, #20]
ac: f442 5280 orr.w r2, r2, #4096 ; 0x1000
b0: 615a str r2, [r3, #20]
myDelay(500000);
b2: f24a 1020 movw r0, #41248 ; 0xa120
b6: f2c0 0007 movt r0, #7 ; 0x7
ba: f000 f81f bl fc <myDelay>
GPIOC->BSRR |= 0x00001000;
be: f241 0300 movw r3, #4096 ; 0x1000
c2: f2c4 0301 movt r3, #16385 ; 0x4001
c6: f241 0200 movw r2, #4096 ; 0x1000
ca: f2c4 0201 movt r2, #16385 ; 0x4001
ce: 6912 ldr r2, [r2, #16]
d0: f442 5280 orr.w r2, r2, #4096 ; 0x1000
d4: 611a str r2, [r3, #16]
myDelay(1500000);
d6: f24e 3060 movw r0, #58208 ; 0xe360
da: f2c0 0016 movt r0, #22 ; 0x16
de: f000 f80d bl fc <myDelay>
}
e2: e7da b.n 9a <main+0x8a>
000000e4 <nmi_handler>:
}
void nmi_handler(void)
{
e4: b480 push {r7}
e6: af00 add r7, sp, #0
return ;
}
e8: 46bd mov sp, r7
ea: bc80 pop {r7}
ec: 4770 bx lr
ee: 46c0 nop (mov r8, r8)
000000f0 <hardfault_handler>:
void hardfault_handler(void)
{
f0: b480 push {r7}
f2: af00 add r7, sp, #0
return ;
}
f4: 46bd mov sp, r7
f6: bc80 pop {r7}
f8: 4770 bx lr
fa: 46c0 nop (mov r8, r8)
000000fc <myDelay>:
//Functions definitions
void myDelay(unsigned long delay )
{
fc: b480 push {r7}
fe: b083 sub sp, #12
100: af00 add r7, sp, #0
102: 6078 str r0, [r7, #4]
while(delay) delay--;
104: e003 b.n 10e <myDelay+0x12>
106: 687b ldr r3, [r7, #4]
108: f103 33ff add.w r3, r3, #4294967295 ; 0xffffffff
10c: 607b str r3, [r7, #4]
10e: 687b ldr r3, [r7, #4]
110: 2b00 cmp r3, #0
112: d1f8 bne.n 106 <myDelay+0xa>
}
114: f107 070c add.w r7, r7, #12 ; 0xc
118: 46bd mov sp, r7
11a: bc80 pop {r7}
11c: 4770 bx lr
11e: 46c0 nop (mov r8, r8)
00000120 <Clk_Init>:
* Description: Init clock system
*
*************************************************************************/
void Clk_Init (void)
{
120: b580 push {r7, lr}
122: af00 add r7, sp, #0
// 1. Cloking the controller from internal HSI RC (8 MHz)
RCC_HSICmd(ENABLE);
124: f04f 0001 mov.w r0, #1 ; 0x1
128: f000 f920 bl 36c <RCC_HSICmd>
// wait until the HSI is ready
while(RCC_GetFlagStatus(RCC_FLAG_HSIRDY) == RESET);
12c: f04f 0020 mov.w r0, #32 ; 0x20
130: f000 fcaa bl a88 <RCC_GetFlagStatus>
134: 4603 mov r3, r0
136: 2b00 cmp r3, #0
138: d0f8 beq.n 12c <Clk_Init+0xc>
RCC_SYSCLKConfig(RCC_SYSCLKSource_HSI);
13a: f04f 0000 mov.w r0, #0 ; 0x0
13e: f000 f95b bl 3f8 <RCC_SYSCLKConfig>
// 2. Enable ext. high frequency OSC
RCC_HSEConfig(RCC_HSE_ON);
142: f44f 3080 mov.w r0, #65536 ; 0x10000
146: f000 f8ab bl 2a0 <RCC_HSEConfig>
// wait until the HSE is ready
while(RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET);
14a: f04f 0031 mov.w r0, #49 ; 0x31
14e: f000 fc9b bl a88 <RCC_GetFlagStatus>
152: 4603 mov r3, r0
154: 2b00 cmp r3, #0
156: d0f8 beq.n 14a <Clk_Init+0x2a>
// 3. Init PLL
RCC_PLLConfig(RCC_PLLSource_HSE_Div1,RCC_PLLMul_9); // 72MHz
158: f44f 3080 mov.w r0, #65536 ; 0x10000
15c: f44f 11e0 mov.w r1, #1835008 ; 0x1c0000
160: f000 f914 bl 38c <RCC_PLLConfig>
// RCC_PLLConfig(RCC_PLLSource_HSE_Div2,RCC_PLLMul_9); // 72MHz
RCC_PLLCmd(ENABLE);
164: f04f 0001 mov.w r0, #1 ; 0x1
168: f000 f936 bl 3d8 <RCC_PLLCmd>
// wait until the PLL is ready
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
16c: f04f 0039 mov.w r0, #57 ; 0x39
170: f000 fc8a bl a88 <RCC_GetFlagStatus>
174: 4603 mov r3, r0
176: 2b00 cmp r3, #0
178: d0f8 beq.n 16c <Clk_Init+0x4c>
// 4. Set system clock divders
RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_1Div5);
17a: f04f 0000 mov.w r0, #0 ; 0x0
17e: f000 fa05 bl 58c <RCC_USBCLKConfig>
RCC_ADCCLKConfig(RCC_PCLK2_Div8);
182: f44f 4040 mov.w r0, #49152 ; 0xc000
186: f000 fa11 bl 5ac <RCC_ADCCLKConfig>
RCC_PCLK2Config(RCC_HCLK_Div1);
18a: f04f 0000 mov.w r0, #0 ; 0x0
18e: f000 f9a7 bl 4e0 <RCC_PCLK2Config>
RCC_PCLK1Config(RCC_HCLK_Div2);
192: f44f 6080 mov.w r0, #1024 ; 0x400
196: f000 f981 bl 49c <RCC_PCLK1Config>
RCC_HCLKConfig(RCC_SYSCLK_Div1);
19a: f04f 0000 mov.w r0, #0 ; 0x0
19e: f000 f95b bl 458 <RCC_HCLKConfig>
// Flash 1 wait state
*(vu32 *)0x40022000 = 0x12;
1a2: f242 0300 movw r3, #8192 ; 0x2000
1a6: f2c4 0302 movt r3, #16386 ; 0x4002
1aa: f04f 0212 mov.w r2, #18 ; 0x12
1ae: 601a str r2, [r3, #0]
// 5. Clock system from PLL
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
1b0: f04f 0002 mov.w r0, #2 ; 0x2
1b4: f000 f920 bl 3f8 <RCC_SYSCLKConfig>
}
1b8: 46bd mov sp, r7
1ba: bd80 pop {r7, pc}
000001bc <RCC_DeInit>:
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void RCC_DeInit(void)
{
1bc: b480 push {r7}
1be: af00 add r7, sp, #0
/* Disable APB2 Peripheral Reset */
RCC->APB2RSTR = 0x00000000;
1c0: f241 0300 movw r3, #4096 ; 0x1000
1c4: f2c4 0302 movt r3, #16386 ; 0x4002
1c8: f04f 0200 mov.w r2, #0 ; 0x0
1cc: 60da str r2, [r3, #12]
/* Disable APB1 Peripheral Reset */
RCC->APB1RSTR = 0x00000000;
1ce: f241 0300 movw r3, #4096 ; 0x1000
1d2: f2c4 0302 movt r3, #16386 ; 0x4002
1d6: f04f 0200 mov.w r2, #0 ; 0x0
1da: 611a str r2, [r3, #16]
/* FLITF and SRAM Clock ON */
RCC->AHBENR = 0x00000014;
1dc: f241 0300 movw r3, #4096 ; 0x1000
1e0: f2c4 0302 movt r3, #16386 ; 0x4002
1e4: f04f 0214 mov.w r2, #20 ; 0x14
1e8: 615a str r2, [r3, #20]
/* Disable APB2 Peripheral Clock */
RCC->APB2ENR = 0x00000000;
1ea: f241 0300 movw r3, #4096 ; 0x1000
1ee: f2c4 0302 movt r3, #16386 ; 0x4002
1f2: f04f 0200 mov.w r2, #0 ; 0x0
1f6: 619a str r2, [r3, #24]
/* Disable APB1 Peripheral Clock */
RCC->APB1ENR = 0x00000000;
1f8: f241 0300 movw r3, #4096 ; 0x1000
1fc: f2c4 0302 movt r3, #16386 ; 0x4002
200: f04f 0200 mov.w r2, #0 ; 0x0
204: 61da str r2, [r3, #28]
/* Set HSION bit */
RCC->CR |= (u32)0x00000001;
206: f241 0300 movw r3, #4096 ; 0x1000
20a: f2c4 0302 movt r3, #16386 ; 0x4002
20e: f241 0200 movw r2, #4096 ; 0x1000
212: f2c4 0202 movt r2, #16386 ; 0x4002
216: 6812 ldr r2, [r2, #0]
218: f042 0201 orr.w r2, r2, #1 ; 0x1
21c: 601a str r2, [r3, #0]
/* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits*/
RCC->CFGR &= 0xF8FF0000;
21e: f241 0200 movw r2, #4096 ; 0x1000
222: f2c4 0202 movt r2, #16386 ; 0x4002
226: f241 0300 movw r3, #4096 ; 0x1000
22a: f2c4 0302 movt r3, #16386 ; 0x4002
22e: 6859 ldr r1, [r3, #4]
230: f240 0300 movw r3, #0 ; 0x0
234: f6cf 03ff movt r3, #63743 ; 0xf8ff
238: ea01 0303 and.w r3, r1, r3
23c: 6053 str r3, [r2, #4]
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= 0xFEF6FFFF;
23e: f241 0300 movw r3, #4096 ; 0x1000
242: f2c4 0302 movt r3, #16386 ; 0x4002
246: f241 0200 movw r2, #4096 ; 0x1000
24a: f2c4 0202 movt r2, #16386 ; 0x4002
24e: 6812 ldr r2, [r2, #0]
250: f022 7284 bic.w r2, r2, #17301504 ; 0x1080000
254: f422 3280 bic.w r2, r2, #65536 ; 0x10000
258: 601a str r2, [r3, #0]
/* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFF;
25a: f241 0300 movw r3, #4096 ; 0x1000
25e: f2c4 0302 movt r3, #16386 ; 0x4002
262: f241 0200 movw r2, #4096 ; 0x1000
266: f2c4 0202 movt r2, #16386 ; 0x4002
26a: 6812 ldr r2, [r2, #0]
26c: f422 2280 bic.w r2, r2, #262144 ; 0x40000
270: 601a str r2, [r3, #0]
/* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
RCC->CFGR &= 0xFF80FFFF;
272: f241 0300 movw r3, #4096 ; 0x1000
276: f2c4 0302 movt r3, #16386 ; 0x4002
27a: f241 0200 movw r2, #4096 ; 0x1000
27e: f2c4 0202 movt r2, #16386 ; 0x4002
282: 6852 ldr r2, [r2, #4]
284: f422 02fe bic.w r2, r2, #8323072 ; 0x7f0000
288: 605a str r2, [r3, #4]
/* Disable all interrupts */
RCC->CIR = 0x00000000;
28a: f241 0300 movw r3, #4096 ; 0x1000
28e: f2c4 0302 movt r3, #16386 ; 0x4002
292: f04f 0200 mov.w r2, #0 ; 0x0
296: 609a str r2, [r3, #8]
}
298: 46bd mov sp, r7
29a: bc80 pop {r7}
29c: 4770 bx lr
29e: 46c0 nop (mov r8, r8)
000002a0 <RCC_HSEConfig>:
* clock
* Output : None
* Return : None
*******************************************************************************/
void RCC_HSEConfig(u32 RCC_HSE)
{
2a0: b480 push {r7}
2a2: b083 sub sp, #12
2a4: af00 add r7, sp, #0
2a6: 6078 str r0, [r7, #4]
/* Check the parameters */
assert(IS_RCC_HSE(RCC_HSE));
/* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
/* Reset HSEON bit */
RCC->CR &= CR_HSEON_Reset;
2a8: f241 0300 movw r3, #4096 ; 0x1000
2ac: f2c4 0302 movt r3, #16386 ; 0x4002
2b0: f241 0200 movw r2, #4096 ; 0x1000
2b4: f2c4 0202 movt r2, #16386 ; 0x4002
2b8: 6812 ldr r2, [r2, #0]
2ba: f422 3280 bic.w r2, r2, #65536 ; 0x10000
2be: 601a str r2, [r3, #0]
/* Reset HSEBYP bit */
RCC->CR &= CR_HSEBYP_Reset;
2c0: f241 0300 movw r3, #4096 ; 0x1000
2c4: f2c4 0302 movt r3, #16386 ; 0x4002
2c8: f241 0200 movw r2, #4096 ; 0x1000
2cc: f2c4 0202 movt r2, #16386 ; 0x4002
2d0: 6812 ldr r2, [r2, #0]
2d2: f422 2280 bic.w r2, r2, #262144 ; 0x40000
2d6: 601a str r2, [r3, #0]
/* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
switch(RCC_HSE)
2d8: 687b ldr r3, [r7, #4]
2da: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
2de: d003 beq.n 2e8 <RCC_HSEConfig+0x48>
2e0: f5b3 2f80 cmp.w r3, #262144 ; 0x40000
2e4: d00d beq.n 302 <RCC_HSEConfig+0x62>
2e6: e018 b.n 31a <RCC_HSEConfig+0x7a>
{
case RCC_HSE_ON:
/* Set HSEON bit */
RCC->CR |= CR_HSEON_Set;
2e8: f241 0300 movw r3, #4096 ; 0x1000
2ec: f2c4 0302 movt r3, #16386 ; 0x4002
2f0: f241 0200 movw r2, #4096 ; 0x1000
2f4: f2c4 0202 movt r2, #16386 ; 0x4002
2f8: 6812 ldr r2, [r2, #0]
2fa: f442 3280 orr.w r2, r2, #65536 ; 0x10000
2fe: 601a str r2, [r3, #0]
break;
300: e00b b.n 31a <RCC_HSEConfig+0x7a>
case RCC_HSE_Bypass:
/* Set HSEBYP and HSEON bits */
RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
302: f241 0300 movw r3, #4096 ; 0x1000
306: f2c4 0302 movt r3, #16386 ; 0x4002
30a: f241 0200 movw r2, #4096 ; 0x1000
30e: f2c4 0202 movt r2, #16386 ; 0x4002
312: 6812 ldr r2, [r2, #0]
314: f442 22a0 orr.w r2, r2, #327680 ; 0x50000
318: 601a str r2, [r3, #0]
break;
default:
break;
}
}
31a: f107 070c add.w r7, r7, #12 ; 0xc
31e: 46bd mov sp, r7
320: bc80 pop {r7}
322: 4770 bx lr
00000324 <RCC_AdjustHSICalibrationValue>:
* This parameter must be a number between 0 and 0x1F.
* Output : None
* Return : None
*******************************************************************************/
void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue)
{
324: b480 push {r7}
326: b085 sub sp, #20
328: af00 add r7, sp, #0
32a: 4603 mov r3, r0
32c: 71fb strb r3, [r7, #7]
u32 tmpreg = 0;
32e: f04f 0300 mov.w r3, #0 ; 0x0
332: 60fb str r3, [r7, #12]
/* Check the parameters */
assert(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
tmpreg = RCC->CR;
334: f241 0300 movw r3, #4096 ; 0x1000
338: f2c4 0302 movt r3, #16386 ; 0x4002
33c: 681b ldr r3, [r3, #0]
33e: 60fb str r3, [r7, #12]
/* Clear HSITRIM[7:3] bits */
tmpreg &= CR_HSITRIM_Mask;
340: 68fb ldr r3, [r7, #12]
342: f023 03f8 bic.w r3, r3, #248 ; 0xf8
346: 60fb str r3, [r7, #12]
/* Set the HSITRIM[7:3] bits according to HSICalibrationValue value */
tmpreg |= (u32)HSICalibrationValue << 3;
348: 79fb ldrb r3, [r7, #7]
34a: ea4f 03c3 mov.w r3, r3, lsl #3
34e: 68fa ldr r2, [r7, #12]
350: ea42 0303 orr.w r3, r2, r3
354: 60fb str r3, [r7, #12]
/* Store the new value */
RCC->CR = tmpreg;
356: f241 0300 movw r3, #4096 ; 0x1000
35a: f2c4 0302 movt r3, #16386 ; 0x4002
35e: 68fa ldr r2, [r7, #12]
360: 601a str r2, [r3, #0]
}
362: f107 0714 add.w r7, r7, #20 ; 0x14
366: 46bd mov sp, r7
368: bc80 pop {r7}
36a: 4770 bx lr
0000036c <RCC_HSICmd>:
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void RCC_HSICmd(FunctionalState NewState)
{
36c: b480 push {r7}
36e: b083 sub sp, #12
370: af00 add r7, sp, #0
372: 4603 mov r3, r0
374: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CR_HSION_BB = (u32)NewState;
376: f240 0300 movw r3, #0 ; 0x0
37a: f2c4 2342 movt r3, #16962 ; 0x4242
37e: 79fa ldrb r2, [r7, #7]
380: 601a str r2, [r3, #0]
}
382: f107 070c add.w r7, r7, #12 ; 0xc
386: 46bd mov sp, r7
388: bc80 pop {r7}
38a: 4770 bx lr
0000038c <RCC_PLLConfig>:
* This parameter can be RCC_PLLMul_x where x:[2,16]
* Output : None
* Return : None
*******************************************************************************/
void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul)
{
38c: b480 push {r7}
38e: b085 sub sp, #20
390: af00 add r7, sp, #0
392: 6078 str r0, [r7, #4]
394: 6039 str r1, [r7, #0]
u32 tmpreg = 0;
396: f04f 0300 mov.w r3, #0 ; 0x0
39a: 60fb str r3, [r7, #12]
/* Check the parameters */
assert(IS_RCC_PLL_SOURCE(RCC_PLLSource));
assert(IS_RCC_PLL_MUL(RCC_PLLMul));
tmpreg = RCC->CFGR;
39c: f241 0300 movw r3, #4096 ; 0x1000
3a0: f2c4 0302 movt r3, #16386 ; 0x4002
3a4: 685b ldr r3, [r3, #4]
3a6: 60fb str r3, [r7, #12]
/* Clear PLLSRC, PLLXTPRE and PLLMUL[21:18] bits */
tmpreg &= CFGR_PLL_Mask;
3a8: 68fb ldr r3, [r7, #12]
3aa: f423 137c bic.w r3, r3, #4128768 ; 0x3f0000
3ae: 60fb str r3, [r7, #12]
/* Set the PLL configuration bits */
tmpreg |= RCC_PLLSource | RCC_PLLMul;
3b0: 687a ldr r2, [r7, #4]
3b2: 683b ldr r3, [r7, #0]
3b4: ea42 0303 orr.w r3, r2, r3
3b8: 68fa ldr r2, [r7, #12]
3ba: ea42 0303 orr.w r3, r2, r3
3be: 60fb str r3, [r7, #12]
/* Store the new value */
RCC->CFGR = tmpreg;
3c0: f241 0300 movw r3, #4096 ; 0x1000
3c4: f2c4 0302 movt r3, #16386 ; 0x4002
3c8: 68fa ldr r2, [r7, #12]
3ca: 605a str r2, [r3, #4]
}
3cc: f107 0714 add.w r7, r7, #20 ; 0x14
3d0: 46bd mov sp, r7
3d2: bc80 pop {r7}
3d4: 4770 bx lr
3d6: 46c0 nop (mov r8, r8)
000003d8 <RCC_PLLCmd>:
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void RCC_PLLCmd(FunctionalState NewState)
{
3d8: b480 push {r7}
3da: b083 sub sp, #12
3dc: af00 add r7, sp, #0
3de: 4603 mov r3, r0
3e0: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CR_PLLON_BB = (u32)NewState;
3e2: f240 0360 movw r3, #96 ; 0x60
3e6: f2c4 2342 movt r3, #16962 ; 0x4242
3ea: 79fa ldrb r2, [r7, #7]
3ec: 601a str r2, [r3, #0]
}
3ee: f107 070c add.w r7, r7, #12 ; 0xc
3f2: 46bd mov sp, r7
3f4: bc80 pop {r7}
3f6: 4770 bx lr
000003f8 <RCC_SYSCLKConfig>:
* - RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
* Output : None
* Return : None
*******************************************************************************/
void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource)
{
3f8: b480 push {r7}
3fa: b085 sub sp, #20
3fc: af00 add r7, sp, #0
3fe: 6078 str r0, [r7, #4]
u32 tmpreg = 0;
400: f04f 0300 mov.w r3, #0 ; 0x0
404: 60fb str r3, [r7, #12]
/* Check the parameters */
assert(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
tmpreg = RCC->CFGR;
406: f241 0300 movw r3, #4096 ; 0x1000
40a: f2c4 0302 movt r3, #16386 ; 0x4002
40e: 685b ldr r3, [r3, #4]
410: 60fb str r3, [r7, #12]
/* Clear SW[1:0] bits */
tmpreg &= CFGR_SW_Mask;
412: 68fb ldr r3, [r7, #12]
414: f023 0303 bic.w r3, r3, #3 ; 0x3
418: 60fb str r3, [r7, #12]
/* Set SW[1:0] bits according to RCC_SYSCLKSource value */
tmpreg |= RCC_SYSCLKSource;
41a: 68fa ldr r2, [r7, #12]
41c: 687b ldr r3, [r7, #4]
41e: ea42 0303 orr.w r3, r2, r3
422: 60fb str r3, [r7, #12]
/* Store the new value */
RCC->CFGR = tmpreg;
424: f241 0300 movw r3, #4096 ; 0x1000
428: f2c4 0302 movt r3, #16386 ; 0x4002
42c: 68fa ldr r2, [r7, #12]
42e: 605a str r2, [r3, #4]
}
430: f107 0714 add.w r7, r7, #20 ; 0x14
434: 46bd mov sp, r7
436: bc80 pop {r7}
438: 4770 bx lr
43a: 46c0 nop (mov r8, r8)
0000043c <RCC_GetSYSCLKSource>:
* - 0x00: HSI used as system clock
* - 0x04: HSE used as system clock
* - 0x08: PLL used as system clock
*******************************************************************************/
u8 RCC_GetSYSCLKSource(void)
{
43c: b480 push {r7}
43e: af00 add r7, sp, #0
return ((u8)(RCC->CFGR & CFGR_SWS_Mask));
440: f241 0300 movw r3, #4096 ; 0x1000
444: f2c4 0302 movt r3, #16386 ; 0x4002
448: 685b ldr r3, [r3, #4]
44a: b2db uxtb r3, r3
44c: f003 030c and.w r3, r3, #12 ; 0xc
}
450: 4618 mov r0, r3
452: 46bd mov sp, r7
454: bc80 pop {r7}
456: 4770 bx lr
00000458 <RCC_HCLKConfig>:
* - RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
* Output : None
* Return : None
*******************************************************************************/
void RCC_HCLKConfig(u32 RCC_HCLK)
{
458: b480 push {r7}
45a: b085 sub sp, #20
45c: af00 add r7, sp, #0
45e: 6078 str r0, [r7, #4]
u32 tmpreg = 0;
460: f04f 0300 mov.w r3, #0 ; 0x0
464: 60fb str r3, [r7, #12]
/* Check the parameters */
assert(IS_RCC_HCLK(RCC_HCLK));
tmpreg = RCC->CFGR;
466: f241 0300 movw r3, #4096 ; 0x1000
46a: f2c4 0302 movt r3, #16386 ; 0x4002
46e: 685b ldr r3, [r3, #4]
470: 60fb str r3, [r7, #12]
/* Clear HPRE[7:4] bits */
tmpreg &= CFGR_HPRE_Reset_Mask;
472: 68fb ldr r3, [r7, #12]
474: f023 03f0 bic.w r3, r3, #240 ; 0xf0
478: 60fb str r3, [r7, #12]
/* Set HPRE[7:4] bits according to RCC_HCLK value */
tmpreg |= RCC_HCLK;
47a: 68fa ldr r2, [r7, #12]
47c: 687b ldr r3, [r7, #4]
47e: ea42 0303 orr.w r3, r2, r3
482: 60fb str r3, [r7, #12]
/* Store the new value */
RCC->CFGR = tmpreg;
484: f241 0300 movw r3, #4096 ; 0x1000
488: f2c4 0302 movt r3, #16386 ; 0x4002
48c: 68fa ldr r2, [r7, #12]
48e: 605a str r2, [r3, #4]
}
490: f107 0714 add.w r7, r7, #20 ; 0x14
494: 46bd mov sp, r7
496: bc80 pop {r7}
498: 4770 bx lr
49a: 46c0 nop (mov r8, r8)
0000049c <RCC_PCLK1Config>:
* - RCC_HCLK_Div16: APB1 clock = HCLK/16
* Output : None
* Return : None
*******************************************************************************/
void RCC_PCLK1Config(u32 RCC_PCLK1)
{
49c: b480 push {r7}
49e: b085 sub sp, #20
4a0: af00 add r7, sp, #0
4a2: 6078 str r0, [r7, #4]
u32 tmpreg = 0;
4a4: f04f 0300 mov.w r3, #0 ; 0x0
4a8: 60fb str r3, [r7, #12]
/* Check the parameters */
assert(IS_RCC_PCLK(RCC_PCLK1));
tmpreg = RCC->CFGR;
4aa: f241 0300 movw r3, #4096 ; 0x1000
4ae: f2c4 0302 movt r3, #16386 ; 0x4002
4b2: 685b ldr r3, [r3, #4]
4b4: 60fb str r3, [r7, #12]
/* Clear PPRE1[10:8] bits */
tmpreg &= CFGR_PPRE1_Reset_Mask;
4b6: 68fb ldr r3, [r7, #12]
4b8: f423 63e0 bic.w r3, r3, #1792 ; 0x700
4bc: 60fb str r3, [r7, #12]
/* Set PPRE1[10:8] bits according to RCC_PCLK1 value */
tmpreg |= RCC_PCLK1;
4be: 68fa ldr r2, [r7, #12]
4c0: 687b ldr r3, [r7, #4]
4c2: ea42 0303 orr.w r3, r2, r3
4c6: 60fb str r3, [r7, #12]
/* Store the new value */
RCC->CFGR = tmpreg;
4c8: f241 0300 movw r3, #4096 ; 0x1000
4cc: f2c4 0302 movt r3, #16386 ; 0x4002
4d0: 68fa ldr r2, [r7, #12]
4d2: 605a str r2, [r3, #4]
}
4d4: f107 0714 add.w r7, r7, #20 ; 0x14
4d8: 46bd mov sp, r7
4da: bc80 pop {r7}
4dc: 4770 bx lr
4de: 46c0 nop (mov r8, r8)
000004e0 <RCC_PCLK2Config>:
* - RCC_HCLK_Div16: APB2 clock = HCLK/16
* Output : None
* Return : None
*******************************************************************************/
void RCC_PCLK2Config(u32 RCC_PCLK2)
{
4e0: b480 push {r7}
4e2: b085 sub sp, #20
4e4: af00 add r7, sp, #0
4e6: 6078 str r0, [r7, #4]
u32 tmpreg = 0;
4e8: f04f 0300 mov.w r3, #0 ; 0x0
4ec: 60fb str r3, [r7, #12]
/* Check the parameters */
assert(IS_RCC_PCLK(RCC_PCLK2));
tmpreg = RCC->CFGR;
4ee: f241 0300 movw r3, #4096 ; 0x1000
4f2: f2c4 0302 movt r3, #16386 ; 0x4002
4f6: 685b ldr r3, [r3, #4]
4f8: 60fb str r3, [r7, #12]
/* Clear PPRE2[13:11] bits */
tmpreg &= CFGR_PPRE2_Reset_Mask;
4fa: 68fb ldr r3, [r7, #12]
4fc: f423 5360 bic.w r3, r3, #14336 ; 0x3800
500: 60fb str r3, [r7, #12]
/* Set PPRE2[13:11] bits according to RCC_PCLK2 value */
tmpreg |= RCC_PCLK2 << 3;
502: 687b ldr r3, [r7, #4]
504: ea4f 03c3 mov.w r3, r3, lsl #3
508: 68fa ldr r2, [r7, #12]
50a: ea42 0303 orr.w r3, r2, r3
50e: 60fb str r3, [r7, #12]
/* Store the new value */
RCC->CFGR = tmpreg;
510: f241 0300 movw r3, #4096 ; 0x1000
514: f2c4 0302 movt r3, #16386 ; 0x4002
518: 68fa ldr r2, [r7, #12]
51a: 605a str r2, [r3, #4]
}
51c: f107 0714 add.w r7, r7, #20 ; 0x14
520: 46bd mov sp, r7
522: bc80 pop {r7}
524: 4770 bx lr
526: 46c0 nop (mov r8, r8)
00000528 <RCC_ITConfig>:
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState)
{
528: b480 push {r7}
52a: b083 sub sp, #12
52c: af00 add r7, sp, #0
52e: 4602 mov r2, r0
530: 460b mov r3, r1
532: 71fa strb r2, [r7, #7]
534: 71bb strb r3, [r7, #6]
/* Check the parameters */
assert(IS_RCC_IT(RCC_IT));
assert(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
536: 79bb ldrb r3, [r7, #6]
538: 2b00 cmp r3, #0
53a: d00f beq.n 55c <RCC_ITConfig+0x34>
{
/* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
*(vu8 *) 0x40021009 |= RCC_IT;
53c: f241 0309 movw r3, #4105 ; 0x1009
540: f2c4 0302 movt r3, #16386 ; 0x4002
544: f241 0209 movw r2, #4105 ; 0x1009
548: f2c4 0202 movt r2, #16386 ; 0x4002
54c: 7812 ldrb r2, [r2, #0]
54e: b2d1 uxtb r1, r2
550: 79fa ldrb r2, [r7, #7]
552: ea41 0202 orr.w r2, r1, r2
556: b2d2 uxtb r2, r2
558: 701a strb r2, [r3, #0]
55a: e011 b.n 580 <RCC_ITConfig+0x58>
}
else
{
/* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
*(vu8 *) 0x40021009 &= ~(u32)RCC_IT;
55c: f241 0309 movw r3, #4105 ; 0x1009
560: f2c4 0302 movt r3, #16386 ; 0x4002
564: f241 0209 movw r2, #4105 ; 0x1009
568: f2c4 0202 movt r2, #16386 ; 0x4002
56c: 7812 ldrb r2, [r2, #0]
56e: b2d1 uxtb r1, r2
570: 79fa ldrb r2, [r7, #7]
572: ea6f 0202 mvn.w r2, r2
576: b2d2 uxtb r2, r2
578: ea01 0202 and.w r2, r1, r2
57c: b2d2 uxtb r2, r2
57e: 701a strb r2, [r3, #0]
}
}
580: f107 070c add.w r7, r7, #12 ; 0xc
584: 46bd mov sp, r7
586: bc80 pop {r7}
588: 4770 bx lr
58a: 46c0 nop (mov r8, r8)
0000058c <RCC_USBCLKConfig>:
* clock source
* Output : None
* Return : None
*******************************************************************************/
void RCC_USBCLKConfig(u32 RCC_USBCLKSource)
{
58c: b480 push {r7}
58e: b083 sub sp, #12
590: af00 add r7, sp, #0
592: 6078 str r0, [r7, #4]
/* Check the parameters */
assert(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
*(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource;
594: f240 03d8 movw r3, #216 ; 0xd8
598: f2c4 2342 movt r3, #16962 ; 0x4242
59c: 687a ldr r2, [r7, #4]
59e: 601a str r2, [r3, #0]
}
5a0: f107 070c add.w r7, r7, #12 ; 0xc
5a4: 46bd mov sp, r7
5a6: bc80 pop {r7}
5a8: 4770 bx lr
5aa: 46c0 nop (mov r8, r8)
000005ac <RCC_ADCCLKConfig>:
* - RCC_PCLK2_Div8: ADC clock = PCLK2/8
* Output : None
* Return : None
*******************************************************************************/
void RCC_ADCCLKConfig(u32 RCC_ADCCLK)
{
5ac: b480 push {r7}
5ae: b085 sub sp, #20
5b0: af00 add r7, sp, #0
5b2: 6078 str r0, [r7, #4]
u32 tmpreg = 0;
5b4: f04f 0300 mov.w r3, #0 ; 0x0
5b8: 60fb str r3, [r7, #12]
/* Check the parameters */
assert(IS_RCC_ADCCLK(RCC_ADCCLK));
tmpreg = RCC->CFGR;
5ba: f241 0300 movw r3, #4096 ; 0x1000
5be: f2c4 0302 movt r3, #16386 ; 0x4002
5c2: 685b ldr r3, [r3, #4]
5c4: 60fb str r3, [r7, #12]
/* Clear ADCPRE[15:14] bits */
tmpreg &= CFGR_ADCPRE_Reset_Mask;
5c6: 68fb ldr r3, [r7, #12]
5c8: f423 4340 bic.w r3, r3, #49152 ; 0xc000
5cc: 60fb str r3, [r7, #12]
/* Set ADCPRE[15:14] bits according to RCC_ADCCLK value */
tmpreg |= RCC_ADCCLK;
5ce: 68fa ldr r2, [r7, #12]
5d0: 687b ldr r3, [r7, #4]
5d2: ea42 0303 orr.w r3, r2, r3
5d6: 60fb str r3, [r7, #12]
/* Store the new value */
RCC->CFGR = tmpreg;
5d8: f241 0300 movw r3, #4096 ; 0x1000
5dc: f2c4 0302 movt r3, #16386 ; 0x4002
5e0: 68fa ldr r2, [r7, #12]
5e2: 605a str r2, [r3, #4]
}
5e4: f107 0714 add.w r7, r7, #20 ; 0x14
5e8: 46bd mov sp, r7
5ea: bc80 pop {r7}
5ec: 4770 bx lr
5ee: 46c0 nop (mov r8, r8)
000005f0 <RCC_LSEConfig>:
* clock
* Output : None
* Return : None
*******************************************************************************/
void RCC_LSEConfig(u32 RCC_LSE)
{
5f0: b480 push {r7}
5f2: b083 sub sp, #12
5f4: af00 add r7, sp, #0
5f6: 6078 str r0, [r7, #4]
/* Check the parameters */
assert(IS_RCC_LSE(RCC_LSE));
/* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
/* Reset LSEON bit */
*(vu8 *) BDCR_BASE = RCC_LSE_OFF;
5f8: f241 0320 movw r3, #4128 ; 0x1020
5fc: f2c4 0302 movt r3, #16386 ; 0x4002
600: f04f 0200 mov.w r2, #0 ; 0x0
604: 701a strb r2, [r3, #0]
/* Reset LSEBYP bit */
*(vu8 *) BDCR_BASE = RCC_LSE_OFF;
606: f241 0320 movw r3, #4128 ; 0x1020
60a: f2c4 0302 movt r3, #16386 ; 0x4002
60e: f04f 0200 mov.w r2, #0 ; 0x0
612: 701a strb r2, [r3, #0]
/* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
switch(RCC_LSE)
614: 687b ldr r3, [r7, #4]
616: 2b01 cmp r3, #1
618: d002 beq.n 620 <RCC_LSEConfig+0x30>
61a: 2b04 cmp r3, #4
61c: d008 beq.n 630 <RCC_LSEConfig+0x40>
61e: e00e b.n 63e <RCC_LSEConfig+0x4e>
{
case RCC_LSE_ON:
/* Set LSEON bit */
*(vu8 *) BDCR_BASE = RCC_LSE_ON;
620: f241 0320 movw r3, #4128 ; 0x1020
624: f2c4 0302 movt r3, #16386 ; 0x4002
628: f04f 0201 mov.w r2, #1 ; 0x1
62c: 701a strb r2, [r3, #0]
break;
62e: e006 b.n 63e <RCC_LSEConfig+0x4e>
case RCC_LSE_Bypass:
/* Set LSEBYP and LSEON bits */
*(vu8 *) BDCR_BASE = RCC_LSE_Bypass | RCC_LSE_ON;
630: f241 0320 movw r3, #4128 ; 0x1020
634: f2c4 0302 movt r3, #16386 ; 0x4002
638: f04f 0205 mov.w r2, #5 ; 0x5
63c: 701a strb r2, [r3, #0]
break;
default:
break;
}
}
63e: f107 070c add.w r7, r7, #12 ; 0xc
642: 46bd mov sp, r7
644: bc80 pop {r7}
646: 4770 bx lr
00000648 <RCC_LSICmd>: