From d6fc82af471e34b5a65922ce50ff4c7db0ba62a4 Mon Sep 17 00:00:00 2001 From: Frank Laub Date: Tue, 31 Jan 2023 21:18:02 -0800 Subject: [PATCH] Add riscv-tests and fix divide extern (#359) * Add riscv-tests https://github.com/riscv-software-src/riscv-tests --- risc0/zkvm/Cargo.toml | 4 +- risc0/zkvm/src/prove/exec.rs | 25 +++---- risc0/zkvm/src/testdata/riscv-tests.tgz | Bin 0 -> 26246 bytes risc0/zkvm/src/tests.rs | 90 ++++++++++++++++++++++++ 4 files changed, 104 insertions(+), 15 deletions(-) create mode 100644 risc0/zkvm/src/testdata/riscv-tests.tgz diff --git a/risc0/zkvm/Cargo.toml b/risc0/zkvm/Cargo.toml index 1b422aaa58..6938f73e18 100644 --- a/risc0/zkvm/Cargo.toml +++ b/risc0/zkvm/Cargo.toml @@ -57,6 +57,7 @@ tracing-subscriber = { version = "0.3", features = ["env-filter"] } [target.'cfg(not(target_os = "zkvm"))'.dev-dependencies] env_logger = "0.10" +flate2 = "1.0" lazy_static = "1.4" risc0-zkvm-methods = { path = "methods" } serial_test = "1.0" @@ -65,6 +66,7 @@ tempdir = "0.3" test-log = { version = "0.2", features = ["trace"] } [features] +binfmt = ["dep:elf", "std"] cuda = ["risc0-circuit-rv32im/cuda", "risc0-zkp/cuda"] metal = ["risc0-circuit-rv32im/metal", "risc0-zkp/metal"] default = ["prove"] @@ -72,6 +74,7 @@ dual = [] insecure_skip_seal = [] profiler = ["dep:addr2line", "dep:gimli", "dep:prost", "dep:prost-build", "dep:protobuf-src"] prove = [ + "binfmt", "dep:lazy-regex", "dep:rand", "dep:rayon", @@ -81,4 +84,3 @@ prove = [ "std", ] std = ["anyhow/std", "risc0-circuit-rv32im/std", "risc0-zeroio/std", "risc0-zkp/std", "serde/std"] -binfmt = ["dep:elf", "std"] diff --git a/risc0/zkvm/src/prove/exec.rs b/risc0/zkvm/src/prove/exec.rs index 2c2bf15371..0ecc67b633 100644 --- a/risc0/zkvm/src/prove/exec.rs +++ b/risc0/zkvm/src/prove/exec.rs @@ -538,18 +538,18 @@ impl<'a, H: HostHandler> MachineContext<'a, H> { (BabyBearElem, BabyBearElem, BabyBearElem, BabyBearElem), (BabyBearElem, BabyBearElem, BabyBearElem, BabyBearElem), ) { - let mut numer = merge_word8(numer) as i64; - let mut denom = merge_word8(denom) as i64; + let mut numer = merge_word8(numer) as u32; + let mut denom = merge_word8(denom) as u32; let sign: u32 = sign.into(); // debug!("divide: [{sign}] {numer} / {denom}"); - let ones_comp = (sign == 2) as i64; - let neg_numer = sign != 0 && numer < 0; - let neg_denom = sign == 1 && denom < 0; + let ones_comp = (sign == 2) as u32; + let neg_numer = sign != 0 && (numer as i32) < 0; + let neg_denom = sign == 1 && (denom as i32) < 0; if neg_numer { - numer = -numer - ones_comp; + numer = (!numer).overflowing_add(1 - ones_comp).0; } if neg_denom { - denom = -denom - ones_comp; + denom = (!denom).overflowing_add(1 - ones_comp).0; } let (mut quot, mut rem) = if denom == 0 { (0xffffffff, numer) @@ -559,16 +559,13 @@ impl<'a, H: HostHandler> MachineContext<'a, H> { let quot_neg_out = (neg_numer as u32 ^ neg_denom as u32) - ((denom == 0) as u32 * neg_numer as u32); if quot_neg_out != 0 { - quot = -quot - ones_comp; + quot = (!quot).overflowing_add(1 - ones_comp).0; } if neg_numer { - rem = -rem - ones_comp; + rem = (!rem).overflowing_add(1 - ones_comp).0; } - // debug!(" {quot}, {rem}"); - ( - split_word8(quot as i32 as u32), - split_word8(rem as i32 as u32), - ) + // debug!(" quot: {quot}, rem: {rem}"); + (split_word8(quot), split_word8(rem)) } fn extract_trace(&mut self, message: &str, args: &[BabyBearElem]) -> Result<()> { diff --git a/risc0/zkvm/src/testdata/riscv-tests.tgz b/risc0/zkvm/src/testdata/riscv-tests.tgz new file mode 100644 index 0000000000000000000000000000000000000000..eaabb468f90b3695bd9e18a893ad981d4c990db3 GIT binary patch literal 26246 zcmZ5{c|4R~`@d4DY#~dLDJn|#Bv~feDzc>Pj5TFR_H|~8>|08aFd~VvlWa4|nlKc` zJ~0^C#uzhW*84X-&-43!KhO7%>pthY&biL(e%<$3uH}6|sRy}i+9o}?xYyhHW1PA} z^(snNY#HP+m|KRj=k{y098 z`<^M>(K1mgAQV5|HIGfgoHhmKZy8?a{?42Hb9my`gZfkNhMzuN%iU)nMSu?t%tWIH zHgE2A1TE`Yj9mBDLl?9^e-pW^<4sCH&X^2M2HnEGLXuo#pP84n<|y6zPWUkzz6WSk zyV9cepvL-bs?JXUYTbb9Mz=w+qc?(*?ybu8_*V&4T~pZoazI!!$@y$ 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These tests come from: +// https://github.com/riscv-software-src/riscv-tests +// They were built using the toolchain from: +// https://github.com/risc0/toolchain/releases/tag/2022.03.25 +mod riscv_tests { + macro_rules! test_case { + ($func_name:ident) => { + #[test_log::test] + fn $func_name() { + use std::io::Read; + + use flate2::read::GzDecoder; + use risc0_zkvm_platform::{memory::MEM_SIZE, PAGE_SIZE}; + use tar::Archive; + use $crate::{MemoryImage, Program, Prover}; + + let bytes = include_bytes!("testdata/riscv-tests.tgz"); + let gz = GzDecoder::new(&bytes[..]); + let mut tar = Archive::new(gz); + for entry in tar.entries().unwrap() { + let mut entry = entry.unwrap(); + if !entry.header().entry_type().is_file() { + continue; + } + let path = entry.path().unwrap(); + let filename = path.file_name().unwrap().to_str().unwrap(); + if filename != stringify!($func_name) { + continue; + } + let mut elf = Vec::new(); + entry.read_to_end(&mut elf).unwrap(); + + let program = Program::load_elf(elf.as_slice(), MEM_SIZE as u32).unwrap(); + let image = MemoryImage::new(&program, PAGE_SIZE as u32); + + let mut prover = Prover::new(elf.as_slice(), image.root).unwrap(); + prover.run().unwrap(); + } + } + }; + } + + test_case!(add); + test_case!(addi); + test_case!(and); + test_case!(andi); + test_case!(auipc); + test_case!(beq); + test_case!(bge); + test_case!(bgeu); + test_case!(blt); + test_case!(bltu); + test_case!(bne); + test_case!(div); + test_case!(divu); + test_case!(jal); + test_case!(jalr); + test_case!(lb); + test_case!(lbu); + test_case!(lh); + test_case!(lhu); + test_case!(lui); + test_case!(lw); + test_case!(mul); + test_case!(mulh); + test_case!(mulhsu); + test_case!(mulhu); + test_case!(or); + test_case!(ori); + test_case!(rem); + test_case!(remu); + test_case!(sb); + test_case!(sh); + test_case!(simple); + test_case!(sll); + test_case!(slli); + test_case!(slt); + test_case!(slti); + test_case!(sltiu); + test_case!(sltu); + test_case!(sra); + test_case!(srai); + test_case!(srl); + test_case!(srli); + test_case!(sub); + test_case!(sw); + test_case!(xor); + test_case!(xori); +}