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picoxcell_crypto.c
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/*
* Copyright (c) 2010-2011 Picochip Ltd., Jamie Iles
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <crypto/aead.h>
#include <crypto/aes.h>
#include <crypto/algapi.h>
#include <crypto/authenc.h>
#include <crypto/des.h>
#include <crypto/md5.h>
#include <crypto/sha.h>
#include <crypto/internal/skcipher.h>
#include <linux/clk.h>
#include <linux/crypto.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/dmapool.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/rtnetlink.h>
#include <linux/scatterlist.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/timer.h>
#include "picoxcell_crypto_regs.h"
/*
* The threshold for the number of entries in the CMD FIFO available before
* the CMD0_CNT interrupt is raised. Increasing this value will reduce the
* number of interrupts raised to the CPU.
*/
#define CMD0_IRQ_THRESHOLD 1
/*
* The timeout period (in jiffies) for a PDU. When the the number of PDUs in
* flight is greater than the STAT_IRQ_THRESHOLD or 0 the timer is disabled.
* When there are packets in flight but lower than the threshold, we enable
* the timer and at expiry, attempt to remove any processed packets from the
* queue and if there are still packets left, schedule the timer again.
*/
#define PACKET_TIMEOUT 1
/* The priority to register each algorithm with. */
#define SPACC_CRYPTO_ALG_PRIORITY 10000
#define SPACC_CRYPTO_KASUMI_F8_KEY_LEN 16
#define SPACC_CRYPTO_IPSEC_CIPHER_PG_SZ 64
#define SPACC_CRYPTO_IPSEC_HASH_PG_SZ 64
#define SPACC_CRYPTO_IPSEC_MAX_CTXS 32
#define SPACC_CRYPTO_IPSEC_FIFO_SZ 32
#define SPACC_CRYPTO_L2_CIPHER_PG_SZ 64
#define SPACC_CRYPTO_L2_HASH_PG_SZ 64
#define SPACC_CRYPTO_L2_MAX_CTXS 128
#define SPACC_CRYPTO_L2_FIFO_SZ 128
#define MAX_DDT_LEN 16
/* DDT format. This must match the hardware DDT format exactly. */
struct spacc_ddt {
dma_addr_t p;
u32 len;
};
/*
* Asynchronous crypto request structure.
*
* This structure defines a request that is either queued for processing or
* being processed.
*/
struct spacc_req {
struct list_head list;
struct spacc_engine *engine;
struct crypto_async_request *req;
int result;
bool is_encrypt;
unsigned ctx_id;
dma_addr_t src_addr, dst_addr;
struct spacc_ddt *src_ddt, *dst_ddt;
void (*complete)(struct spacc_req *req);
/* AEAD specific bits. */
u8 *giv;
size_t giv_len;
dma_addr_t giv_pa;
};
struct spacc_engine {
void __iomem *regs;
struct list_head pending;
int next_ctx;
spinlock_t hw_lock;
int in_flight;
struct list_head completed;
struct list_head in_progress;
struct tasklet_struct complete;
unsigned long fifo_sz;
void __iomem *cipher_ctx_base;
void __iomem *hash_key_base;
struct spacc_alg *algs;
unsigned num_algs;
struct list_head registered_algs;
size_t cipher_pg_sz;
size_t hash_pg_sz;
const char *name;
struct clk *clk;
struct device *dev;
unsigned max_ctxs;
struct timer_list packet_timeout;
unsigned stat_irq_thresh;
struct dma_pool *req_pool;
};
/* Algorithm type mask. */
#define SPACC_CRYPTO_ALG_MASK 0x7
/* SPACC definition of a crypto algorithm. */
struct spacc_alg {
unsigned long ctrl_default;
unsigned long type;
struct crypto_alg alg;
struct spacc_engine *engine;
struct list_head entry;
int key_offs;
int iv_offs;
};
/* Generic context structure for any algorithm type. */
struct spacc_generic_ctx {
struct spacc_engine *engine;
int flags;
int key_offs;
int iv_offs;
};
/* Block cipher context. */
struct spacc_ablk_ctx {
struct spacc_generic_ctx generic;
u8 key[AES_MAX_KEY_SIZE];
u8 key_len;
/*
* The fallback cipher. If the operation can't be done in hardware,
* fallback to a software version.
*/
struct crypto_ablkcipher *sw_cipher;
};
/* AEAD cipher context. */
struct spacc_aead_ctx {
struct spacc_generic_ctx generic;
u8 cipher_key[AES_MAX_KEY_SIZE];
u8 hash_ctx[SPACC_CRYPTO_IPSEC_HASH_PG_SZ];
u8 cipher_key_len;
u8 hash_key_len;
struct crypto_aead *sw_cipher;
size_t auth_size;
u8 salt[AES_BLOCK_SIZE];
};
static int spacc_ablk_submit(struct spacc_req *req);
static inline struct spacc_alg *to_spacc_alg(struct crypto_alg *alg)
{
return alg ? container_of(alg, struct spacc_alg, alg) : NULL;
}
static inline int spacc_fifo_cmd_full(struct spacc_engine *engine)
{
u32 fifo_stat = readl(engine->regs + SPA_FIFO_STAT_REG_OFFSET);
return fifo_stat & SPA_FIFO_CMD_FULL;
}
/*
* Given a cipher context, and a context number, get the base address of the
* context page.
*
* Returns the address of the context page where the key/context may
* be written.
*/
static inline void __iomem *spacc_ctx_page_addr(struct spacc_generic_ctx *ctx,
unsigned indx,
bool is_cipher_ctx)
{
return is_cipher_ctx ? ctx->engine->cipher_ctx_base +
(indx * ctx->engine->cipher_pg_sz) :
ctx->engine->hash_key_base + (indx * ctx->engine->hash_pg_sz);
}
/* The context pages can only be written with 32-bit accesses. */
static inline void memcpy_toio32(u32 __iomem *dst, const void *src,
unsigned count)
{
const u32 *src32 = (const u32 *) src;
while (count--)
writel(*src32++, dst++);
}
static void spacc_cipher_write_ctx(struct spacc_generic_ctx *ctx,
void __iomem *page_addr, const u8 *key,
size_t key_len, const u8 *iv, size_t iv_len)
{
void __iomem *key_ptr = page_addr + ctx->key_offs;
void __iomem *iv_ptr = page_addr + ctx->iv_offs;
memcpy_toio32(key_ptr, key, key_len / 4);
memcpy_toio32(iv_ptr, iv, iv_len / 4);
}
/*
* Load a context into the engines context memory.
*
* Returns the index of the context page where the context was loaded.
*/
static unsigned spacc_load_ctx(struct spacc_generic_ctx *ctx,
const u8 *ciph_key, size_t ciph_len,
const u8 *iv, size_t ivlen, const u8 *hash_key,
size_t hash_len)
{
unsigned indx = ctx->engine->next_ctx++;
void __iomem *ciph_page_addr, *hash_page_addr;
ciph_page_addr = spacc_ctx_page_addr(ctx, indx, 1);
hash_page_addr = spacc_ctx_page_addr(ctx, indx, 0);
ctx->engine->next_ctx &= ctx->engine->fifo_sz - 1;
spacc_cipher_write_ctx(ctx, ciph_page_addr, ciph_key, ciph_len, iv,
ivlen);
writel(ciph_len | (indx << SPA_KEY_SZ_CTX_INDEX_OFFSET) |
(1 << SPA_KEY_SZ_CIPHER_OFFSET),
ctx->engine->regs + SPA_KEY_SZ_REG_OFFSET);
if (hash_key) {
memcpy_toio32(hash_page_addr, hash_key, hash_len / 4);
writel(hash_len | (indx << SPA_KEY_SZ_CTX_INDEX_OFFSET),
ctx->engine->regs + SPA_KEY_SZ_REG_OFFSET);
}
return indx;
}
/* Count the number of scatterlist entries in a scatterlist. */
static int sg_count(struct scatterlist *sg_list, int nbytes)
{
struct scatterlist *sg = sg_list;
int sg_nents = 0;
while (nbytes > 0) {
++sg_nents;
nbytes -= sg->length;
sg = sg_next(sg);
}
return sg_nents;
}
static inline void ddt_set(struct spacc_ddt *ddt, dma_addr_t phys, size_t len)
{
ddt->p = phys;
ddt->len = len;
}
/*
* Take a crypto request and scatterlists for the data and turn them into DDTs
* for passing to the crypto engines. This also DMA maps the data so that the
* crypto engines can DMA to/from them.
*/
static struct spacc_ddt *spacc_sg_to_ddt(struct spacc_engine *engine,
struct scatterlist *payload,
unsigned nbytes,
enum dma_data_direction dir,
dma_addr_t *ddt_phys)
{
unsigned nents, mapped_ents;
struct scatterlist *cur;
struct spacc_ddt *ddt;
int i;
nents = sg_count(payload, nbytes);
mapped_ents = dma_map_sg(engine->dev, payload, nents, dir);
if (mapped_ents + 1 > MAX_DDT_LEN)
goto out;
ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, ddt_phys);
if (!ddt)
goto out;
for_each_sg(payload, cur, mapped_ents, i)
ddt_set(&ddt[i], sg_dma_address(cur), sg_dma_len(cur));
ddt_set(&ddt[mapped_ents], 0, 0);
return ddt;
out:
dma_unmap_sg(engine->dev, payload, nents, dir);
return NULL;
}
static int spacc_aead_make_ddts(struct spacc_req *req, u8 *giv)
{
struct aead_request *areq = container_of(req->req, struct aead_request,
base);
struct spacc_engine *engine = req->engine;
struct spacc_ddt *src_ddt, *dst_ddt;
unsigned ivsize = crypto_aead_ivsize(crypto_aead_reqtfm(areq));
unsigned nents = sg_count(areq->src, areq->cryptlen);
dma_addr_t iv_addr;
struct scatterlist *cur;
int i, dst_ents, src_ents, assoc_ents;
u8 *iv = giv ? giv : areq->iv;
src_ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, &req->src_addr);
if (!src_ddt)
return -ENOMEM;
dst_ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, &req->dst_addr);
if (!dst_ddt) {
dma_pool_free(engine->req_pool, src_ddt, req->src_addr);
return -ENOMEM;
}
req->src_ddt = src_ddt;
req->dst_ddt = dst_ddt;
assoc_ents = dma_map_sg(engine->dev, areq->assoc,
sg_count(areq->assoc, areq->assoclen), DMA_TO_DEVICE);
if (areq->src != areq->dst) {
src_ents = dma_map_sg(engine->dev, areq->src, nents,
DMA_TO_DEVICE);
dst_ents = dma_map_sg(engine->dev, areq->dst, nents,
DMA_FROM_DEVICE);
} else {
src_ents = dma_map_sg(engine->dev, areq->src, nents,
DMA_BIDIRECTIONAL);
dst_ents = 0;
}
/*
* Map the IV/GIV. For the GIV it needs to be bidirectional as it is
* formed by the crypto block and sent as the ESP IV for IPSEC.
*/
iv_addr = dma_map_single(engine->dev, iv, ivsize,
giv ? DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
req->giv_pa = iv_addr;
/*
* Map the associated data. For decryption we don't copy the
* associated data.
*/
for_each_sg(areq->assoc, cur, assoc_ents, i) {
ddt_set(src_ddt++, sg_dma_address(cur), sg_dma_len(cur));
if (req->is_encrypt)
ddt_set(dst_ddt++, sg_dma_address(cur),
sg_dma_len(cur));
}
ddt_set(src_ddt++, iv_addr, ivsize);
if (giv || req->is_encrypt)
ddt_set(dst_ddt++, iv_addr, ivsize);
/*
* Now map in the payload for the source and destination and terminate
* with the NULL pointers.
*/
for_each_sg(areq->src, cur, src_ents, i) {
ddt_set(src_ddt++, sg_dma_address(cur), sg_dma_len(cur));
if (areq->src == areq->dst)
ddt_set(dst_ddt++, sg_dma_address(cur),
sg_dma_len(cur));
}
for_each_sg(areq->dst, cur, dst_ents, i)
ddt_set(dst_ddt++, sg_dma_address(cur),
sg_dma_len(cur));
ddt_set(src_ddt, 0, 0);
ddt_set(dst_ddt, 0, 0);
return 0;
}
static void spacc_aead_free_ddts(struct spacc_req *req)
{
struct aead_request *areq = container_of(req->req, struct aead_request,
base);
struct spacc_alg *alg = to_spacc_alg(req->req->tfm->__crt_alg);
struct spacc_ablk_ctx *aead_ctx = crypto_tfm_ctx(req->req->tfm);
struct spacc_engine *engine = aead_ctx->generic.engine;
unsigned ivsize = alg->alg.cra_aead.ivsize;
unsigned nents = sg_count(areq->src, areq->cryptlen);
if (areq->src != areq->dst) {
dma_unmap_sg(engine->dev, areq->src, nents, DMA_TO_DEVICE);
dma_unmap_sg(engine->dev, areq->dst,
sg_count(areq->dst, areq->cryptlen),
DMA_FROM_DEVICE);
} else
dma_unmap_sg(engine->dev, areq->src, nents, DMA_BIDIRECTIONAL);
dma_unmap_sg(engine->dev, areq->assoc,
sg_count(areq->assoc, areq->assoclen), DMA_TO_DEVICE);
dma_unmap_single(engine->dev, req->giv_pa, ivsize, DMA_BIDIRECTIONAL);
dma_pool_free(engine->req_pool, req->src_ddt, req->src_addr);
dma_pool_free(engine->req_pool, req->dst_ddt, req->dst_addr);
}
static void spacc_free_ddt(struct spacc_req *req, struct spacc_ddt *ddt,
dma_addr_t ddt_addr, struct scatterlist *payload,
unsigned nbytes, enum dma_data_direction dir)
{
unsigned nents = sg_count(payload, nbytes);
dma_unmap_sg(req->engine->dev, payload, nents, dir);
dma_pool_free(req->engine->req_pool, ddt, ddt_addr);
}
/*
* Set key for a DES operation in an AEAD cipher. This also performs weak key
* checking if required.
*/
static int spacc_aead_des_setkey(struct crypto_aead *aead, const u8 *key,
unsigned int len)
{
struct crypto_tfm *tfm = crypto_aead_tfm(aead);
struct spacc_aead_ctx *ctx = crypto_tfm_ctx(tfm);
u32 tmp[DES_EXPKEY_WORDS];
if (unlikely(!des_ekey(tmp, key)) &&
(crypto_aead_get_flags(aead)) & CRYPTO_TFM_REQ_WEAK_KEY) {
tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
return -EINVAL;
}
memcpy(ctx->cipher_key, key, len);
ctx->cipher_key_len = len;
return 0;
}
/* Set the key for the AES block cipher component of the AEAD transform. */
static int spacc_aead_aes_setkey(struct crypto_aead *aead, const u8 *key,
unsigned int len)
{
struct crypto_tfm *tfm = crypto_aead_tfm(aead);
struct spacc_aead_ctx *ctx = crypto_tfm_ctx(tfm);
/*
* IPSec engine only supports 128 and 256 bit AES keys. If we get a
* request for any other size (192 bits) then we need to do a software
* fallback.
*/
if (len != AES_KEYSIZE_128 && len != AES_KEYSIZE_256) {
/*
* Set the fallback transform to use the same request flags as
* the hardware transform.
*/
ctx->sw_cipher->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
ctx->sw_cipher->base.crt_flags |=
tfm->crt_flags & CRYPTO_TFM_REQ_MASK;
return crypto_aead_setkey(ctx->sw_cipher, key, len);
}
memcpy(ctx->cipher_key, key, len);
ctx->cipher_key_len = len;
return 0;
}
static int spacc_aead_setkey(struct crypto_aead *tfm, const u8 *key,
unsigned int keylen)
{
struct spacc_aead_ctx *ctx = crypto_aead_ctx(tfm);
struct spacc_alg *alg = to_spacc_alg(tfm->base.__crt_alg);
struct rtattr *rta = (void *)key;
struct crypto_authenc_key_param *param;
unsigned int authkeylen, enckeylen;
int err = -EINVAL;
if (!RTA_OK(rta, keylen))
goto badkey;
if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
goto badkey;
if (RTA_PAYLOAD(rta) < sizeof(*param))
goto badkey;
param = RTA_DATA(rta);
enckeylen = be32_to_cpu(param->enckeylen);
key += RTA_ALIGN(rta->rta_len);
keylen -= RTA_ALIGN(rta->rta_len);
if (keylen < enckeylen)
goto badkey;
authkeylen = keylen - enckeylen;
if (enckeylen > AES_MAX_KEY_SIZE)
goto badkey;
if ((alg->ctrl_default & SPACC_CRYPTO_ALG_MASK) ==
SPA_CTRL_CIPH_ALG_AES)
err = spacc_aead_aes_setkey(tfm, key + authkeylen, enckeylen);
else
err = spacc_aead_des_setkey(tfm, key + authkeylen, enckeylen);
if (err)
goto badkey;
memcpy(ctx->hash_ctx, key, authkeylen);
ctx->hash_key_len = authkeylen;
return 0;
badkey:
crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
return -EINVAL;
}
static int spacc_aead_setauthsize(struct crypto_aead *tfm,
unsigned int authsize)
{
struct spacc_aead_ctx *ctx = crypto_tfm_ctx(crypto_aead_tfm(tfm));
ctx->auth_size = authsize;
return 0;
}
/*
* Check if an AEAD request requires a fallback operation. Some requests can't
* be completed in hardware because the hardware may not support certain key
* sizes. In these cases we need to complete the request in software.
*/
static int spacc_aead_need_fallback(struct spacc_req *req)
{
struct aead_request *aead_req;
struct crypto_tfm *tfm = req->req->tfm;
struct crypto_alg *alg = req->req->tfm->__crt_alg;
struct spacc_alg *spacc_alg = to_spacc_alg(alg);
struct spacc_aead_ctx *ctx = crypto_tfm_ctx(tfm);
aead_req = container_of(req->req, struct aead_request, base);
/*
* If we have a non-supported key-length, then we need to do a
* software fallback.
*/
if ((spacc_alg->ctrl_default & SPACC_CRYPTO_ALG_MASK) ==
SPA_CTRL_CIPH_ALG_AES &&
ctx->cipher_key_len != AES_KEYSIZE_128 &&
ctx->cipher_key_len != AES_KEYSIZE_256)
return 1;
return 0;
}
static int spacc_aead_do_fallback(struct aead_request *req, unsigned alg_type,
bool is_encrypt)
{
struct crypto_tfm *old_tfm = crypto_aead_tfm(crypto_aead_reqtfm(req));
struct spacc_aead_ctx *ctx = crypto_tfm_ctx(old_tfm);
int err;
if (ctx->sw_cipher) {
/*
* Change the request to use the software fallback transform,
* and once the ciphering has completed, put the old transform
* back into the request.
*/
aead_request_set_tfm(req, ctx->sw_cipher);
err = is_encrypt ? crypto_aead_encrypt(req) :
crypto_aead_decrypt(req);
aead_request_set_tfm(req, __crypto_aead_cast(old_tfm));
} else
err = -EINVAL;
return err;
}
static void spacc_aead_complete(struct spacc_req *req)
{
spacc_aead_free_ddts(req);
req->req->complete(req->req, req->result);
}
static int spacc_aead_submit(struct spacc_req *req)
{
struct crypto_tfm *tfm = req->req->tfm;
struct spacc_aead_ctx *ctx = crypto_tfm_ctx(tfm);
struct crypto_alg *alg = req->req->tfm->__crt_alg;
struct spacc_alg *spacc_alg = to_spacc_alg(alg);
struct spacc_engine *engine = ctx->generic.engine;
u32 ctrl, proc_len, assoc_len;
struct aead_request *aead_req =
container_of(req->req, struct aead_request, base);
req->result = -EINPROGRESS;
req->ctx_id = spacc_load_ctx(&ctx->generic, ctx->cipher_key,
ctx->cipher_key_len, aead_req->iv, alg->cra_aead.ivsize,
ctx->hash_ctx, ctx->hash_key_len);
/* Set the source and destination DDT pointers. */
writel(req->src_addr, engine->regs + SPA_SRC_PTR_REG_OFFSET);
writel(req->dst_addr, engine->regs + SPA_DST_PTR_REG_OFFSET);
writel(0, engine->regs + SPA_OFFSET_REG_OFFSET);
assoc_len = aead_req->assoclen;
proc_len = aead_req->cryptlen + assoc_len;
/*
* If we aren't generating an IV, then we need to include the IV in the
* associated data so that it is included in the hash.
*/
if (!req->giv) {
assoc_len += crypto_aead_ivsize(crypto_aead_reqtfm(aead_req));
proc_len += crypto_aead_ivsize(crypto_aead_reqtfm(aead_req));
} else
proc_len += req->giv_len;
/*
* If we are decrypting, we need to take the length of the ICV out of
* the processing length.
*/
if (!req->is_encrypt)
proc_len -= ctx->auth_size;
writel(proc_len, engine->regs + SPA_PROC_LEN_REG_OFFSET);
writel(assoc_len, engine->regs + SPA_AAD_LEN_REG_OFFSET);
writel(ctx->auth_size, engine->regs + SPA_ICV_LEN_REG_OFFSET);
writel(0, engine->regs + SPA_ICV_OFFSET_REG_OFFSET);
writel(0, engine->regs + SPA_AUX_INFO_REG_OFFSET);
ctrl = spacc_alg->ctrl_default | (req->ctx_id << SPA_CTRL_CTX_IDX) |
(1 << SPA_CTRL_ICV_APPEND);
if (req->is_encrypt)
ctrl |= (1 << SPA_CTRL_ENCRYPT_IDX) | (1 << SPA_CTRL_AAD_COPY);
else
ctrl |= (1 << SPA_CTRL_KEY_EXP);
mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT);
writel(ctrl, engine->regs + SPA_CTRL_REG_OFFSET);
return -EINPROGRESS;
}
static int spacc_req_submit(struct spacc_req *req);
static void spacc_push(struct spacc_engine *engine)
{
struct spacc_req *req;
while (!list_empty(&engine->pending) &&
engine->in_flight + 1 <= engine->fifo_sz) {
++engine->in_flight;
req = list_first_entry(&engine->pending, struct spacc_req,
list);
list_move_tail(&req->list, &engine->in_progress);
req->result = spacc_req_submit(req);
}
}
/*
* Setup an AEAD request for processing. This will configure the engine, load
* the context and then start the packet processing.
*
* @giv Pointer to destination address for a generated IV. If the
* request does not need to generate an IV then this should be set to NULL.
*/
static int spacc_aead_setup(struct aead_request *req, u8 *giv,
unsigned alg_type, bool is_encrypt)
{
struct crypto_alg *alg = req->base.tfm->__crt_alg;
struct spacc_engine *engine = to_spacc_alg(alg)->engine;
struct spacc_req *dev_req = aead_request_ctx(req);
int err = -EINPROGRESS;
unsigned long flags;
unsigned ivsize = crypto_aead_ivsize(crypto_aead_reqtfm(req));
dev_req->giv = giv;
dev_req->giv_len = ivsize;
dev_req->req = &req->base;
dev_req->is_encrypt = is_encrypt;
dev_req->result = -EBUSY;
dev_req->engine = engine;
dev_req->complete = spacc_aead_complete;
if (unlikely(spacc_aead_need_fallback(dev_req)))
return spacc_aead_do_fallback(req, alg_type, is_encrypt);
spacc_aead_make_ddts(dev_req, dev_req->giv);
err = -EINPROGRESS;
spin_lock_irqsave(&engine->hw_lock, flags);
if (unlikely(spacc_fifo_cmd_full(engine)) ||
engine->in_flight + 1 > engine->fifo_sz) {
if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
err = -EBUSY;
spin_unlock_irqrestore(&engine->hw_lock, flags);
goto out_free_ddts;
}
list_add_tail(&dev_req->list, &engine->pending);
} else {
list_add_tail(&dev_req->list, &engine->pending);
spacc_push(engine);
}
spin_unlock_irqrestore(&engine->hw_lock, flags);
goto out;
out_free_ddts:
spacc_aead_free_ddts(dev_req);
out:
return err;
}
static int spacc_aead_encrypt(struct aead_request *req)
{
struct crypto_aead *aead = crypto_aead_reqtfm(req);
struct crypto_tfm *tfm = crypto_aead_tfm(aead);
struct spacc_alg *alg = to_spacc_alg(tfm->__crt_alg);
return spacc_aead_setup(req, NULL, alg->type, 1);
}
static int spacc_aead_givencrypt(struct aead_givcrypt_request *req)
{
struct crypto_aead *tfm = aead_givcrypt_reqtfm(req);
struct spacc_aead_ctx *ctx = crypto_aead_ctx(tfm);
size_t ivsize = crypto_aead_ivsize(tfm);
struct spacc_alg *alg = to_spacc_alg(tfm->base.__crt_alg);
unsigned len;
__be64 seq;
memcpy(req->areq.iv, ctx->salt, ivsize);
len = ivsize;
if (ivsize > sizeof(u64)) {
memset(req->giv, 0, ivsize - sizeof(u64));
len = sizeof(u64);
}
seq = cpu_to_be64(req->seq);
memcpy(req->giv + ivsize - len, &seq, len);
return spacc_aead_setup(&req->areq, req->giv, alg->type, 1);
}
static int spacc_aead_decrypt(struct aead_request *req)
{
struct crypto_aead *aead = crypto_aead_reqtfm(req);
struct crypto_tfm *tfm = crypto_aead_tfm(aead);
struct spacc_alg *alg = to_spacc_alg(tfm->__crt_alg);
return spacc_aead_setup(req, NULL, alg->type, 0);
}
/*
* Initialise a new AEAD context. This is responsible for allocating the
* fallback cipher and initialising the context.
*/
static int spacc_aead_cra_init(struct crypto_tfm *tfm)
{
struct spacc_aead_ctx *ctx = crypto_tfm_ctx(tfm);
struct crypto_alg *alg = tfm->__crt_alg;
struct spacc_alg *spacc_alg = to_spacc_alg(alg);
struct spacc_engine *engine = spacc_alg->engine;
ctx->generic.flags = spacc_alg->type;
ctx->generic.engine = engine;
ctx->sw_cipher = crypto_alloc_aead(alg->cra_name, 0,
CRYPTO_ALG_ASYNC |
CRYPTO_ALG_NEED_FALLBACK);
if (IS_ERR(ctx->sw_cipher)) {
dev_warn(engine->dev, "failed to allocate fallback for %s\n",
alg->cra_name);
ctx->sw_cipher = NULL;
}
ctx->generic.key_offs = spacc_alg->key_offs;
ctx->generic.iv_offs = spacc_alg->iv_offs;
get_random_bytes(ctx->salt, sizeof(ctx->salt));
tfm->crt_aead.reqsize = sizeof(struct spacc_req);
return 0;
}
/*
* Destructor for an AEAD context. This is called when the transform is freed
* and must free the fallback cipher.
*/
static void spacc_aead_cra_exit(struct crypto_tfm *tfm)
{
struct spacc_aead_ctx *ctx = crypto_tfm_ctx(tfm);
if (ctx->sw_cipher)
crypto_free_aead(ctx->sw_cipher);
ctx->sw_cipher = NULL;
}
/*
* Set the DES key for a block cipher transform. This also performs weak key
* checking if the transform has requested it.
*/
static int spacc_des_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
unsigned int len)
{
struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
u32 tmp[DES_EXPKEY_WORDS];
if (len > DES3_EDE_KEY_SIZE) {
crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
return -EINVAL;
}
if (unlikely(!des_ekey(tmp, key)) &&
(crypto_ablkcipher_get_flags(cipher) & CRYPTO_TFM_REQ_WEAK_KEY)) {
tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
return -EINVAL;
}
memcpy(ctx->key, key, len);
ctx->key_len = len;
return 0;
}
/*
* Set the key for an AES block cipher. Some key lengths are not supported in
* hardware so this must also check whether a fallback is needed.
*/
static int spacc_aes_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
unsigned int len)
{
struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
int err = 0;
if (len > AES_MAX_KEY_SIZE) {
crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
return -EINVAL;
}
/*
* IPSec engine only supports 128 and 256 bit AES keys. If we get a
* request for any other size (192 bits) then we need to do a software
* fallback.
*/
if ((len != AES_KEYSIZE_128 || len != AES_KEYSIZE_256) &&
ctx->sw_cipher) {
/*
* Set the fallback transform to use the same request flags as
* the hardware transform.
*/
ctx->sw_cipher->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
ctx->sw_cipher->base.crt_flags |=
cipher->base.crt_flags & CRYPTO_TFM_REQ_MASK;
err = crypto_ablkcipher_setkey(ctx->sw_cipher, key, len);
if (err)
goto sw_setkey_failed;
} else if ((len != AES_KEYSIZE_128 || len != AES_KEYSIZE_256) &&
!ctx->sw_cipher)
err = -EINVAL;
memcpy(ctx->key, key, len);
ctx->key_len = len;
sw_setkey_failed:
if (err && ctx->sw_cipher) {
tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK;
tfm->crt_flags |=
ctx->sw_cipher->base.crt_flags & CRYPTO_TFM_RES_MASK;
}
return err;
}
static int spacc_kasumi_f8_setkey(struct crypto_ablkcipher *cipher,
const u8 *key, unsigned int len)
{
struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
int err = 0;
if (len > AES_MAX_KEY_SIZE) {
crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
err = -EINVAL;
goto out;
}
memcpy(ctx->key, key, len);
ctx->key_len = len;
out:
return err;
}
static int spacc_ablk_need_fallback(struct spacc_req *req)
{
struct spacc_ablk_ctx *ctx;
struct crypto_tfm *tfm = req->req->tfm;
struct crypto_alg *alg = req->req->tfm->__crt_alg;
struct spacc_alg *spacc_alg = to_spacc_alg(alg);
ctx = crypto_tfm_ctx(tfm);
return (spacc_alg->ctrl_default & SPACC_CRYPTO_ALG_MASK) ==
SPA_CTRL_CIPH_ALG_AES &&
ctx->key_len != AES_KEYSIZE_128 &&
ctx->key_len != AES_KEYSIZE_256;
}
static void spacc_ablk_complete(struct spacc_req *req)
{
struct ablkcipher_request *ablk_req =
container_of(req->req, struct ablkcipher_request, base);
if (ablk_req->src != ablk_req->dst) {
spacc_free_ddt(req, req->src_ddt, req->src_addr, ablk_req->src,
ablk_req->nbytes, DMA_TO_DEVICE);
spacc_free_ddt(req, req->dst_ddt, req->dst_addr, ablk_req->dst,
ablk_req->nbytes, DMA_FROM_DEVICE);
} else
spacc_free_ddt(req, req->dst_ddt, req->dst_addr, ablk_req->dst,
ablk_req->nbytes, DMA_BIDIRECTIONAL);
req->req->complete(req->req, req->result);
}
static int spacc_ablk_submit(struct spacc_req *req)
{
struct crypto_tfm *tfm = req->req->tfm;
struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
struct ablkcipher_request *ablk_req = ablkcipher_request_cast(req->req);
struct crypto_alg *alg = req->req->tfm->__crt_alg;
struct spacc_alg *spacc_alg = to_spacc_alg(alg);
struct spacc_engine *engine = ctx->generic.engine;
u32 ctrl;
req->ctx_id = spacc_load_ctx(&ctx->generic, ctx->key,
ctx->key_len, ablk_req->info, alg->cra_ablkcipher.ivsize,
NULL, 0);
writel(req->src_addr, engine->regs + SPA_SRC_PTR_REG_OFFSET);
writel(req->dst_addr, engine->regs + SPA_DST_PTR_REG_OFFSET);
writel(0, engine->regs + SPA_OFFSET_REG_OFFSET);
writel(ablk_req->nbytes, engine->regs + SPA_PROC_LEN_REG_OFFSET);
writel(0, engine->regs + SPA_ICV_OFFSET_REG_OFFSET);
writel(0, engine->regs + SPA_AUX_INFO_REG_OFFSET);
writel(0, engine->regs + SPA_AAD_LEN_REG_OFFSET);
ctrl = spacc_alg->ctrl_default | (req->ctx_id << SPA_CTRL_CTX_IDX) |
(req->is_encrypt ? (1 << SPA_CTRL_ENCRYPT_IDX) :
(1 << SPA_CTRL_KEY_EXP));
mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT);
writel(ctrl, engine->regs + SPA_CTRL_REG_OFFSET);
return -EINPROGRESS;
}
static int spacc_ablk_do_fallback(struct ablkcipher_request *req,
unsigned alg_type, bool is_encrypt)
{
struct crypto_tfm *old_tfm =
crypto_ablkcipher_tfm(crypto_ablkcipher_reqtfm(req));
struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(old_tfm);
int err;
if (!ctx->sw_cipher)