octaplexsys

Yaroslav Omelchuk octaplexsys

Achievements

6 stars written in Verilog

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Verilog 728 251 Updated Dec 1, 2024

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

Verilog 398 198 Updated Jan 29, 2023

A fully-integrated FT8 protocol receiver on 130nm CMOS

Verilog 58 3 Updated Nov 13, 2022

This Repo has Files related to reverse engineering of IBM 98Y2610 Intel Cyclone IV

Verilog 57 3 Updated Dec 5, 2024

Dual-Mode PSK Transceiver on SDR With FPGA

Verilog 26 13 Updated Oct 9, 2024

Forked from open-sdr/openofdm

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

Verilog 1 Updated Dec 10, 2017