Skip to content

@YosysHQ Yosys Headquarters

Change the repository type filter

All

    Repositories list

    40 repositories

    • apicula

      Public
      Project Apicula 🐝: bitstream documentation for Gowin FPGAs
      Verilog
      •
      MIT License
      •70•510•14•5•Updated Dec 22, 2024Dec 22, 2024

    • oss-cad-suite-build

      Public
      Multi-platform nightly builds of open source digital design and verification tools
      Shell
      •
      ISC License
      •81•889•50•1•Updated Dec 22, 2024Dec 22, 2024

    • nextpnr

      Public
      nextpnr portable FPGA place and route tool
      C++
      •
      ISC License
      •246•1.3k•97•11•Updated Dec 21, 2024Dec 21, 2024

    • prjpeppercorn-test-cases

      Public
      Project Peppercorn GateMate Test Cases
      Verilog
      •
      ISC License
      •0•1•0•0•Updated Dec 20, 2024Dec 20, 2024

    • yosys

      Public
      Yosys Open SYnthesis Suite
      C++
      •
      ISC License
      •895•3.6k•463•120•Updated Dec 20, 2024Dec 20, 2024

    • prjpeppercorn

      Public
      Project Peppercorn - GateMate FPGA Bitstream Documentation
      C++
      •
      ISC License
      •1•8•0•0•Updated Dec 20, 2024Dec 20, 2024

    • icestorm

      Public
      Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
      Python
      •
      ISC License
      •224•1k•39•17•Updated Dec 11, 2024Dec 11, 2024

    • mcy

      Public
      Mutation Cover with Yosys (MCY)
      C++
      •
      ISC License
      •9•77•1•0•Updated Dec 11, 2024Dec 11, 2024

    • eqy

      Public
      Equivalence checking with Yosys
      Python
      •
      Other
      •6•35•10•0•Updated Dec 11, 2024Dec 11, 2024

    • sby

      Public
      SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
      Python
      •
      Other
      •78•413•43•15•Updated Dec 11, 2024Dec 11, 2024

    • abc

      Public
      ABC: System for Sequential Logic Synthesis and Formal Verification
      C
      •
      Other
      •597•27•0•2•Updated Dec 11, 2024Dec 11, 2024

    • prjtrellis

      Public
      Documenting the Lattice ECP5 bit-stream format.
      Python
      •
      Other
      •88•400•33•12•Updated Dec 9, 2024Dec 9, 2024

    • imctk

      Public
      Incremental Model Checking Toolkit
      Rust
      •
      Other
      •2•5•10•1•Updated Nov 29, 2024Nov 29, 2024

    • furo-ys

      Public
      A clean customizable documentation theme for Sphinx
      Sass
      •
      MIT License
      •322•0•0•2•Updated Nov 28, 2024Nov 28, 2024

    • riscv-formal

      Public
      RISC-V Formal Verification Framework
      Verilog
      •
      ISC License
      •25•115•5•4•Updated Oct 16, 2024Oct 16, 2024

    • nerv

      Public
      Naive Educational RISC V processor
      SystemVerilog
      •
      Other
      •12•75•1•2•Updated Oct 13, 2024Oct 13, 2024

    • yosyshq.github.io

      Public
      www.yosyshq.net
      HTML
      •1•4•0•0•Updated Oct 7, 2024Oct 7, 2024

    • yosys-web

      Public
      Yosys Web Page
      HTML
      •6•3•1•0•Updated Oct 7, 2024Oct 7, 2024

    • nextpnr-tests

      Public
      Verilog
      •
      ISC License
      •5•5•0•1•Updated Sep 20, 2024Sep 20, 2024

    • mau

      Public
      Modular Application Utilities
      Python
      •
      ISC License
      •3•5•1•0•Updated Aug 12, 2024Aug 12, 2024

    • picorv32

      Public
      PicoRV32 - A Size-Optimized RISC-V CPU
      Verilog
      •
      ISC License
      •767•3.2k•58•11•Updated Jun 27, 2024Jun 27, 2024

    • VlogHammer

      Public
      A Verilog Synthesis Regression Test
      Shell
      •8•34•0•2•Updated Mar 21, 2024Mar 21, 2024

    • setup-oss-cad-suite

      Public
      Set up your GitHub Actions workflow with a OSS CAD Suite
      TypeScript
      •
      ISC License
      •2•14•3•0•Updated Mar 21, 2024Mar 21, 2024

    • sby-gui

      Public
      GUI for SymbiYosys
      C++
      •
      ISC License
      •4•12•7•0•Updated Mar 21, 2024Mar 21, 2024

    • scy

      Public
      Sequence of Covers with Yosys
      SystemVerilog
      •
      Other
      •1•5•1•0•Updated Jan 29, 2024Jan 29, 2024

    • prjtrellis-db

      Public
      Project Trellis database
      Creative Commons Zero v1.0 Universal
      •10•12•0•1•Updated Oct 4, 2023Oct 4, 2023

    • padring

      Public
      A padring generator for ASICs
      asicedachipvlsiyosys
      C++
      •
      ISC License
      •8•22•2•1•Updated May 17, 2023May 17, 2023

    • .github

      Public
      0•0•0•0•Updated Apr 4, 2023Apr 4, 2023

    • yosys-manual-build

      Public archive
      Yosys manual
      Dockerfile
      •0•0•0•0•Updated Oct 24, 2022Oct 24, 2022

    • yosys-tests

      Public
      Collection of test cases for Yosys
      Verilog
      •7•17•1•1•Updated Jan 4, 2022Jan 4, 2022