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Commits on Jan 10, 2017

• Add an assert for hasLoopInvariantOperands

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  trentxintong

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• Revert the attempt to optimize the constexpr functions. MSVC does not handle this yet

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  rnk

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• Fix MSVC build of AlignedCharArrayUnion

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Commits on Jan 9, 2017

• Lift the 10-type limit for AlignedCharArrayUnion

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  scallanan

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• Commit a test for match-full-lines.

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  jyknight

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• [WebAssembly] Add return type annotations in fast isel.

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  Dan Gohman

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• TarWriter: Fix a bug in Ustar header.

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  rui314

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• [NVPTX] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).

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  EugeneZelenko

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• [X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests

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  RKSimon

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• Refactor inline threshold update code.

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  Easwaran Raman

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• [SimplifyLibCalls] pow(x, -0.5) -> 1.0 / sqrt(x).

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  dcci

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• Support outputting to /dev/null.

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  espindola

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• PeepholeOptimizer: Do not replace SubregToReg(bitcast like)

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  MatzeB

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• Drive by typo fix

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  MatzeB

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• MachineInstr: Print name for subreg index in SUBREG_TO_REG

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  MatzeB

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• TarWriter: Set "00" to Ustar version field.

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  rui314

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• Revert r291092 because it introduces a crash.

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• X86-specific path: Implemented the fusing of MUL+ADDSUB to FMADDSUB.

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  Vyacheslav Klochkov

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• [InstCombine] add test to show missed fold using llvm.assume; NFC

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  rotateright

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• Revert "[ObjectYAML] Support for DWARF line tables"

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  Chris Bieneman

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• [ObjectYAML] Support for DWARF line tables

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  Chris Bieneman

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• [InstCombine] regenerate checks; NFC

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  rotateright

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• [ValueTracking] regenerate checks; NFC

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  rotateright

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• Fix function regex in update_tests so it can handle {}'s in function args

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  dberlin

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• [InstCombine] regenerate checks; NFC

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• [InstCombine] remove unnecessary attribute comments from test files; NFC

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• [LV] Fix-up external IV users after updating dominator tree

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• AMDGPU: Add Assert[SZ]Ext during argument load creation

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• Reapply r291025 ("AMDGPU: Remove unneccessary intermediate vector")

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  arsenm

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• Intrinsic::Bitreverse is safe to speculate

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  trentxintong

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• In the below scenario, we must be able to skip the a DBG_VALUE instruction and

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  Sumanth Gundapaneni

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• [X86][AVX512] Enable v16i8/v32i8 vector shifts to use an extend+shift+truncate pattern.

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  RKSimon

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• fix comment typos; NFC

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  rotateright

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• [X86][AVX512DQ] Enable v16i16 vector shifts to use an extend+shift+truncate pattern.

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  RKSimon

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• [X86][AVX512DQ] Added AVX512DQ to 128/256 bit vector shift tests

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