PicoRV32 - A Size-Optimized RISC-V CPU

A tiny Open POWER ISA softcore written in VHDL 2008

This repository contains small example designs that can be used with the open source icestorm flow.

USB Serial on the TinyFPGA BX

MIPSfpga+ allows loading programs via UART and has a switchable clock

Upduino v2 with the ice40 up5k FPGA demos

A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs

Original FPGA platform

tinyVision.ai Vision & Sensor FPGA System on Module

Wishbone interconnect utilities

A small 32-bit implementation of the RISC-V architecture

Design to connect Lattice Ultraplus FPGA to OV7670 Camera Module

FPGA-based open-source network tester

EtherPIPE: an Ethernet character device for packet processing

original 8bit CPU of ICF3-Z

http://os.cs.tsinghua.edu.cn/research/undergraduate/zwpu2019

Test running Clifford's picorv32 in iverilog simulation and on ICE40 FPGA