From b39ef0bfa6ff11f6011284c684707d195a00d942 Mon Sep 17 00:00:00 2001 From: Nguyen Anh Quynh Date: Wed, 4 Dec 2013 11:52:28 +0800 Subject: [PATCH] arm: added some alias registers --- bindings/java/capstone/Arm_const.java | 3 +++ bindings/python/capstone/arm_const.py | 3 +++ include/arm.h | 5 +++++ 3 files changed, 11 insertions(+) diff --git a/bindings/java/capstone/Arm_const.java b/bindings/java/capstone/Arm_const.java index f22fb90123..8f55e4ca3b 100644 --- a/bindings/java/capstone/Arm_const.java +++ b/bindings/java/capstone/Arm_const.java @@ -119,6 +119,9 @@ public class Arm_const { public static final int ARM_REG_R10 = 76; public static final int ARM_REG_R11 = 77; public static final int ARM_REG_R12 = 78; + public static final int ARM_REG_R13 = ARM_REG_SP; + public static final int ARM_REG_R14 = ARM_REG_LR; + public static final int ARM_REG_R15 = ARM_REG_PC; public static final int ARM_REG_S0 = 79; public static final int ARM_REG_S1 = 80; public static final int ARM_REG_S2 = 81; diff --git a/bindings/python/capstone/arm_const.py b/bindings/python/capstone/arm_const.py index 3651b7a212..af91294e03 100644 --- a/bindings/python/capstone/arm_const.py +++ b/bindings/python/capstone/arm_const.py @@ -116,6 +116,9 @@ ARM_REG_R10 = 76 ARM_REG_R11 = 77 ARM_REG_R12 = 78 +ARM_REG_R13 = ARM_REG_SP +ARM_REG_R14 = ARM_REG_LR +ARM_REG_R15 = ARM_REG_PC ARM_REG_S0 = 79 ARM_REG_S1 = 80 ARM_REG_S2 = 81 diff --git a/include/arm.h b/include/arm.h index 692377f583..765d862e17 100644 --- a/include/arm.h +++ b/include/arm.h @@ -206,7 +206,12 @@ typedef enum arm_reg { ARM_REG_S29, ARM_REG_S30, ARM_REG_S31, + ARM_REG_MAX, + + ARM_REG_R13 = ARM_REG_SP, + ARM_REG_R14 = ARM_REG_LR, + ARM_REG_R15 = ARM_REG_PC, } arm_reg; // ARM instruction