From 892f622d1659af58e119d32b20a0a8bb8fccb635 Mon Sep 17 00:00:00 2001
From: Philipp Diethelm <philipp.diethelm@precisionwave.com>
Date: Wed, 12 Oct 2022 21:23:42 +0200
Subject: [PATCH] Improved compile xvlog compile time and tested with 2022.1

---
 sim/genip_xilinx_mac.tcl | 5 ++++-
 sim/utils/Makefile       | 8 ++------
 2 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/sim/genip_xilinx_mac.tcl b/sim/genip_xilinx_mac.tcl
index c585520..e922877 100644
--- a/sim/genip_xilinx_mac.tcl
+++ b/sim/genip_xilinx_mac.tcl
@@ -29,7 +29,10 @@
 
 set prj_name XilMacPrj
 
-create_project -part xc7vx690tffg1761-3 $prj_name -force
+#set part xc7vx690tffg1761-3 
+set part xc7k70tfbg484-3 
+
+create_project -part $part $prj_name -force
 create_ip -vlnv xilinx.com:ip:ten_gig_eth_mac:* -module_name xilinx_mac
 set_property CONFIG.Management_Interface false [get_ips xilinx_mac]
 #report_property [get_ips xilinx_mac]
diff --git a/sim/utils/Makefile b/sim/utils/Makefile
index 57d5473..c751927 100644
--- a/sim/utils/Makefile
+++ b/sim/utils/Makefile
@@ -69,13 +69,9 @@ siminst:
 	$(foreach ifgi, $(IFGI_VALUES), $(foreach corr_levli, $(CORR_LEVLI_VALUES), $(MAKE) runsim SIMHDL=$(SIMHDL) SRCHDL=$(SRCHDL) PCAP=$(PCAP) TEST=$(TEST) IFG=$(ifgi) CORR_LEVL=$(corr_levli) UNDERRUN=0 LOG=$(LOG) && )) true
 	$(foreach ifgi, $(IFGI_VALUES), $(foreach underruni, $(UNDERRUNI_VALUES), $(MAKE) runsim SIMHDL=$(SIMHDL) SRCHDL=$(SRCHDL) PCAP=$(PCAP) TEST=$(TEST) IFG=$(ifgi) CORR_LEVL=0 UNDERRUN=$(underruni) LOG=$(LOG) && )) true
 
-vpath %.sdb xsim.dir/work
-
-%.sdb: %.v
-	xvlog -sv $(xvflags) $<
-
-runsim: gen_stim $(HDL:.v=.sdb)
+runsim: gen_stim $(HDL)
 	echo "\n\n////\nSim: IFG=$(IFG) CORR_LEVL=$(CORR_LEVL) UNDERRUN=$(UNDERRUN)\n////" >> $(LOG)
+	xvlog -sv $(xvflags) $(HDL)
 	xelab work.$(top_sim_hdl) -s sim_snapshot
 	xsim -R sim_snapshot > simlog
 	grep -i "SIM OK" simlog || (echo "Simulation failed, see reports"; false)