Commits

Branch selector

 master

User selector

All users

Datepicker

All time

Commit History

Commits on Oct 18, 2022

• Removed some wildcards from Makefile

  philippdiethelm

  committed
  30761ac

  Copy full SHA for 30761ac

• Tested and updated to simulate on Linux

  philippdiethelm

  committed
  a4021cf

  Copy full SHA for a4021cf

Commits on Oct 17, 2022

• Added possibility to use VHDL sources for simulation

  philippdiethelm

  committed
  e4f2995

  Copy full SHA for e4f2995

Commits on Oct 12, 2022

• Improved compile xvlog compile time and tested with 2022.1

  philippdiethelm

  committed
  892f622

  Copy full SHA for 892f622

• Fixed Verilog simulation with 2021.1

  philippdiethelm

  committed
  9fad5a5

  Copy full SHA for 9fad5a5

• Reworking simulation scripts (Work in Progress)

  Show description for 8f3ed25
  philippdiethelm

  committed
  8f3ed25

  Copy full SHA for 8f3ed25

Commits on Sep 26, 2022

• Reviewed port and fixed issues

  philippdiethelm

  committed
  cccbc88

  Copy full SHA for cccbc88

Commits on Sep 25, 2022

• Untested port to VHDL

  

  philippdiethelm

  authored and

  bad c0ded

  committed
  1b460bb

  Copy full SHA for 1b460bb

Commits on Sep 21, 2022

• Added demo project for test on hardware

  Show description for ea4e039
  philippdiethelm

  committed
  ea4e039

  Copy full SHA for ea4e039

• Added script to generate IP integrator component

  philippdiethelm

  committed
  d2ba338

  Copy full SHA for d2ba338

Commits on Feb 25, 2016

• Update README at usr_intf section

  forconesi

  committed
  c21bfea

  Copy full SHA for c21bfea

Commits on Feb 23, 2016

• Merge branch 'yansh-readme-patch'

  Show description for b615245
  forconesi

  committed
  b615245

  Copy full SHA for b615245

Commits on Feb 22, 2016

• Update README.md

  Show description for 2ca54a2
  yansh

  committed
  2ca54a2

  Copy full SHA for 2ca54a2

Commits on Feb 21, 2016

• Add README file

  forconesi

  committed
  b638b73

  Copy full SHA for b638b73

• Add wrapper files to integrate the nfmac10g core with Xilinx ten_gig_pcs_pma.

  Show description for 9ddd08c
  forconesi

  committed
  9ddd08c

  Copy full SHA for 9ddd08c

• Update header files with NetFPGA license

  forconesi

  committed
  cf57180

  Copy full SHA for cf57180

Commits on Feb 19, 2016

• User_interface: add module to interface to the user with buffers.

  Show description for ca3e2ff
  forconesi

  committed
  ca3e2ff

  Copy full SHA for ca3e2ff

Commits on Feb 17, 2016

• Sim: fixed a port declaration that was leaving a wire unconnected

  forconesi

  committed
  557e359

  Copy full SHA for 557e359

Commits on Feb 14, 2016

• Add synthesis script, report timing and utilisation for quick dev/opt

  forconesi

  committed
  78c1008

  Copy full SHA for 78c1008

Commits on Feb 12, 2016

• Sim: Extended simulation framework to test against Xilinx MAC

  Show description for 86c669b
  forconesi

  committed
  86c669b

  Copy full SHA for 86c669b

Commits on Feb 5, 2016

• Sim: fix tx_ and rx_conf vector so simulation can be run using xilinx ten_gig_eth_mac core and nfmac10g

  forconesi

  committed
  28fc361

  Copy full SHA for 28fc361

• Sim: add inter-frame gap monitor

  forconesi

  committed
  fcb2bf6

  Copy full SHA for fcb2bf6

Commits on Feb 4, 2016

• Fix Makefile to accept pcap_files from the command line

  forconesi

  committed
  f3a61c2

  Copy full SHA for f3a61c2

Commits on Feb 3, 2016

• Sim: fix error conditions and support for discontinued pkts

  forconesi

  committed
  6592093

  Copy full SHA for 6592093

• Fix to set initial CRC value after frame discontinued

  forconesi

  committed
  b71eddb

  Copy full SHA for b71eddb

Commits on Feb 1, 2016

• Add simulation framework

  forconesi

  committed
  3ae56b0

  Copy full SHA for 3ae56b0

• Add design files

  forconesi

  committed
  f794811

  Copy full SHA for f794811