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Naive Educational RISC V processor

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Name		Name	Last commit message	Last commit date
Latest commit History 51 Commits
examples/icebreaker		examples/icebreaker
.gitignore		.gitignore
COPYING		COPYING
Makefile		Makefile
NERV.png		NERV.png
README.md		README.md
cexdata.sh		cexdata.sh
checks.cfg		checks.cfg
disasm.py		disasm.py
firmware.c		firmware.c
firmware.s		firmware.s
nerv.sv		nerv.sv
nervsoc.sv		nervsoc.sv
sections.lds		sections.lds
testbench.gtkw		testbench.gtkw
testbench.sv		testbench.sv
trace.gtkw		trace.gtkw
wrapper.sv		wrapper.sv

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NERV - Naive Educational RISC-V Processor

NERV is a very simple single-stage RV32I processor.

Running the simulation testbench

git clone https://github.com/SymbioticEDA/nerv.git
cd nerv
make

Running the riscv-formal testbench

git clone https://github.com/SymbioticEDA/riscv-formal.git
cd riscv-formal/cores/
git clone https://github.com/SymbioticEDA/nerv.git
cd nerv
make -j8 check