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Commits on Sep 19, 2023

• Release v0.2.13

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  niwis

  committed
  7968dd6

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Commits on Sep 14, 2023

• tc_sram_xilinx: Fix be assignment (#30)

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  CyrilKoe

  authored
  35174b2

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Commits on Aug 11, 2023

• Release v0.2.12

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  niwis

  committed
  298b729

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• tc_sram_xilinx: Support ByteWidth != 8 (#29)

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  niwis

  authored
  481dedc

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Commits on Dec 12, 2022

• Release v0.2.11

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  niwis

  committed
  a9cae21

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• Add tc_clk_or2 (#27)

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  meggiman

  authored
  23182a3

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Commits on Nov 21, 2022

• Release v0.2.10

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  niwis

  committed
  aef525b

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Commits on Nov 2, 2022

• tc_clk_xilinx.sv: Add IS_FUNCTIONAL parameter (#26)

  creinwar

  authored
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Commits on Oct 25, 2022

• tc_sram: Add implementation key and IO (#17)

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  paulsc96

  authored
  0541317

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Commits on Jul 26, 2022

• tc_sram: Init performance optimization (#24)

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  JeanRochCoulon

  authored
  b2a6811

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Commits on Apr 28, 2022

• tc_sram: Improve simulation performance (#23)

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  meggiman

  authored
  8283d6c

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Commits on Mar 17, 2022

• Release v0.2.9

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  niwis

  committed
  e6226a6

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• Add optional parameter to tc_clk_gating to flag functional gates (#22)

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  meggiman

  authored
  f0be9a4

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Commits on Oct 4, 2021

• Fix bender, add xilinx pads (#16)

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  3 peopleauthored
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Commits on Sep 7, 2021

• Update MAINTAINER

  

  zarubaf

  authored and

  niwis

  committed
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Commits on Feb 23, 2021

• Ensure synthesis uses tc_* cells and not behavioral models (#11)

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  paulsc96

  and

  zarubaf

  authored
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Commits on Feb 4, 2021

• Release v0.2.4

  zarubaf

  committed
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Commits on Feb 3, 2021

• Add missing legacy file for xilinx port of tech_cells (#10)

  meggiman

  authored
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Commits on Jan 28, 2021

• Release v0.2.3

  zarubaf

  committed
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Commits on Dec 18, 2020

• IPApproX: Add tc_sram to src_files.yml (#9)

  micprog

  authored
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Commits on Nov 12, 2020

• tc_sram_xilinx: Remove unsupported string from parameter

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  andreaskurth

  and

  zarubaf

  authored
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Commits on Nov 11, 2020

• Release v0.2.2

  zarubaf

  authored
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• Bender: Add pulp_clock_gating_async for compatibility (#8)

  micprog

  authored
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Commits on Jun 23, 2020

• Release v0.2.1

  zarubaf

  committed
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Commits on Apr 23, 2020

• Bender: Remove target func_sim, is now rtl

  

  Wolfgang Rönninger

  authored and

  zarubaf

  committed
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• tc_clk:tc_clk_delay: Add Synthesis and Verilator guards

  

  Wolfgang Rönninger

  authored and

  zarubaf

  committed
  30b7d0a

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• tc_sram: Drop string from parameter SimInit

  

  Wolfgang Rönninger

  authored and

  zarubaf

  committed
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• Bender: Add func_sim target to explicit compile tc_sram

  

  Wolfgang Rönninger

  authored and

  zarubaf

  committed
  45d0a17

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Commits on Apr 20, 2020

• Bender: Fix typo

  

  Wolfgang Rönninger

  authored and

  zarubaf

  committed
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Commits on Mar 18, 2020

• Release v0.2.0

  zarubaf

  committed
  c333ef0

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• tc_sram: Update CHANGELOG and README

  

  Wolfgang Rönninger

  authored and

  zarubaf

  committed
  baeeee6

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• Vivado xsim: remove add_sources.tcl, now generated from bender

  

  Wolfgang Rönninger

  authored and

  zarubaf

  committed
  743d0c9

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• tb_tc_sram: Add Xsim scripts

  

  Wolfgang Rönninger

  authored and

  zarubaf

  committed
  65965af

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• add SRAM simulation scripts

  

  Wolfgang Rönninger

  authored and

  zarubaf

  committed
  3f451dc

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• Bender: add SRAM

  

  Wolfgang Rönninger

  authored and

  zarubaf

  committed
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