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[X86][SSE] Add SSE_HADDSUB/SSE_PABS/SSE_PALIGN OpndItins
Update multi-classes to take the scheduling OpndItins instead of hard coding it. Will be reused in the AVX512 equivalents. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319209 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/X86/X86InstrSSE.td

+59-45
Original file line numberDiff line numberDiff line change
@@ -4831,137 +4831,146 @@ let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
48314831
// SSE3 Instructions
48324832
//===---------------------------------------------------------------------===//
48334833

4834+
let Sched = WriteFHAdd in
4835+
def SSE_HADDSUB : OpndItins<
4836+
IIC_SSE_HADDSUB_RR, IIC_SSE_HADDSUB_RM
4837+
>;
4838+
48344839
// Horizontal ops
48354840
multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4836-
X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
4837-
bit Is2Addr = 1> {
4841+
X86MemOperand x86memop, SDNode OpNode, OpndItins itins,
4842+
PatFrag ld_frag, bit Is2Addr = 1> {
48384843
def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
48394844
!if(Is2Addr,
48404845
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
48414846
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4842-
[(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
4843-
Sched<[WriteFHAdd]>;
4847+
[(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr>,
4848+
Sched<[itins.Sched]>;
48444849

48454850
def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
48464851
!if(Is2Addr,
48474852
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
48484853
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48494854
[(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
4850-
IIC_SSE_HADDSUB_RM>, Sched<[WriteFHAddLd, ReadAfterLd]>;
4855+
itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
48514856
}
48524857
multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4853-
X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
4854-
bit Is2Addr = 1> {
4858+
X86MemOperand x86memop, SDNode OpNode, OpndItins itins,
4859+
PatFrag ld_frag, bit Is2Addr = 1> {
48554860
def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
48564861
!if(Is2Addr,
48574862
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
48584863
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4859-
[(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
4860-
Sched<[WriteFHAdd]>;
4864+
[(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr>,
4865+
Sched<[itins.Sched]>;
48614866

48624867
def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
48634868
!if(Is2Addr,
48644869
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
48654870
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48664871
[(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
4867-
IIC_SSE_HADDSUB_RM>, Sched<[WriteFHAddLd, ReadAfterLd]>;
4872+
itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
48684873
}
48694874

48704875
let Predicates = [HasAVX] in {
48714876
let ExeDomain = SSEPackedSingle in {
48724877
defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
4873-
X86fhadd, loadv4f32, 0>, VEX_4V, VEX_WIG;
4878+
X86fhadd, SSE_HADDSUB, loadv4f32, 0>, VEX_4V, VEX_WIG;
48744879
defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
4875-
X86fhsub, loadv4f32, 0>, VEX_4V, VEX_WIG;
4880+
X86fhsub, SSE_HADDSUB, loadv4f32, 0>, VEX_4V, VEX_WIG;
48764881
defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
4877-
X86fhadd, loadv8f32, 0>, VEX_4V, VEX_L, VEX_WIG;
4882+
X86fhadd, SSE_HADDSUB, loadv8f32, 0>, VEX_4V, VEX_L, VEX_WIG;
48784883
defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
4879-
X86fhsub, loadv8f32, 0>, VEX_4V, VEX_L, VEX_WIG;
4884+
X86fhsub, SSE_HADDSUB, loadv8f32, 0>, VEX_4V, VEX_L, VEX_WIG;
48804885
}
48814886
let ExeDomain = SSEPackedDouble in {
48824887
defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
4883-
X86fhadd, loadv2f64, 0>, VEX_4V, VEX_WIG;
4888+
X86fhadd, SSE_HADDSUB, loadv2f64, 0>, VEX_4V, VEX_WIG;
48844889
defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
4885-
X86fhsub, loadv2f64, 0>, VEX_4V, VEX_WIG;
4890+
X86fhsub, SSE_HADDSUB, loadv2f64, 0>, VEX_4V, VEX_WIG;
48864891
defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
4887-
X86fhadd, loadv4f64, 0>, VEX_4V, VEX_L, VEX_WIG;
4892+
X86fhadd, SSE_HADDSUB, loadv4f64, 0>, VEX_4V, VEX_L, VEX_WIG;
48884893
defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
4889-
X86fhsub, loadv4f64, 0>, VEX_4V, VEX_L, VEX_WIG;
4894+
X86fhsub, SSE_HADDSUB, loadv4f64, 0>, VEX_4V, VEX_L, VEX_WIG;
48904895
}
48914896
}
48924897

48934898
let Constraints = "$src1 = $dst" in {
48944899
let ExeDomain = SSEPackedSingle in {
48954900
defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd,
4896-
memopv4f32>;
4901+
SSE_HADDSUB, memopv4f32>;
48974902
defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub,
4898-
memopv4f32>;
4903+
SSE_HADDSUB, memopv4f32>;
48994904
}
49004905
let ExeDomain = SSEPackedDouble in {
49014906
defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd,
4902-
memopv2f64>;
4907+
SSE_HADDSUB, memopv2f64>;
49034908
defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub,
4904-
memopv2f64>;
4909+
SSE_HADDSUB, memopv2f64>;
49054910
}
49064911
}
49074912

49084913
//===---------------------------------------------------------------------===//
49094914
// SSSE3 - Packed Absolute Instructions
49104915
//===---------------------------------------------------------------------===//
49114916

4917+
let Sched = WriteVecALU in
4918+
def SSE_PABS : OpndItins<
4919+
IIC_SSE_PABS_RR, IIC_SSE_PABS_RM
4920+
>;
49124921

49134922
/// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
49144923
multiclass SS3I_unop_rm<bits<8> opc, string OpcodeStr, ValueType vt,
4915-
SDNode OpNode, PatFrag ld_frag> {
4924+
SDNode OpNode, OpndItins itins, PatFrag ld_frag> {
49164925
def rr : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
49174926
(ins VR128:$src),
49184927
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
49194928
[(set VR128:$dst, (vt (OpNode VR128:$src)))],
4920-
IIC_SSE_PABS_RR>, Sched<[WriteVecALU]>;
4929+
itins.rr>, Sched<[itins.Sched]>;
49214930

49224931
def rm : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
49234932
(ins i128mem:$src),
49244933
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
49254934
[(set VR128:$dst,
49264935
(vt (OpNode (bitconvert (ld_frag addr:$src)))))],
4927-
IIC_SSE_PABS_RM>, Sched<[WriteVecALULd]>;
4936+
itins.rm>, Sched<[itins.Sched.Folded]>;
49284937
}
49294938

49304939
/// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
49314940
multiclass SS3I_unop_rm_y<bits<8> opc, string OpcodeStr, ValueType vt,
4932-
SDNode OpNode> {
4941+
SDNode OpNode, OpndItins itins> {
49334942
def Yrr : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
49344943
(ins VR256:$src),
49354944
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4936-
[(set VR256:$dst, (vt (OpNode VR256:$src)))]>,
4937-
Sched<[WriteVecALU]>;
4945+
[(set VR256:$dst, (vt (OpNode VR256:$src)))], itins.rr>,
4946+
Sched<[itins.Sched]>;
49384947

49394948
def Yrm : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
49404949
(ins i256mem:$src),
49414950
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
49424951
[(set VR256:$dst,
4943-
(vt (OpNode (bitconvert (loadv4i64 addr:$src)))))]>,
4944-
Sched<[WriteVecALULd]>;
4952+
(vt (OpNode (bitconvert (loadv4i64 addr:$src)))))], itins.rm>,
4953+
Sched<[itins.Sched.Folded]>;
49454954
}
49464955

49474956
let Predicates = [HasAVX, NoVLX_Or_NoBWI] in {
4948-
defm VPABSB : SS3I_unop_rm<0x1C, "vpabsb", v16i8, abs, loadv2i64>, VEX, VEX_WIG;
4949-
defm VPABSW : SS3I_unop_rm<0x1D, "vpabsw", v8i16, abs, loadv2i64>, VEX, VEX_WIG;
4957+
defm VPABSB : SS3I_unop_rm<0x1C, "vpabsb", v16i8, abs, SSE_PABS, loadv2i64>, VEX, VEX_WIG;
4958+
defm VPABSW : SS3I_unop_rm<0x1D, "vpabsw", v8i16, abs, SSE_PABS, loadv2i64>, VEX, VEX_WIG;
49504959
}
49514960
let Predicates = [HasAVX, NoVLX] in {
4952-
defm VPABSD : SS3I_unop_rm<0x1E, "vpabsd", v4i32, abs, loadv2i64>, VEX, VEX_WIG;
4961+
defm VPABSD : SS3I_unop_rm<0x1E, "vpabsd", v4i32, abs, SSE_PABS, loadv2i64>, VEX, VEX_WIG;
49534962
}
49544963
let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in {
4955-
defm VPABSB : SS3I_unop_rm_y<0x1C, "vpabsb", v32i8, abs>, VEX, VEX_L, VEX_WIG;
4956-
defm VPABSW : SS3I_unop_rm_y<0x1D, "vpabsw", v16i16, abs>, VEX, VEX_L, VEX_WIG;
4964+
defm VPABSB : SS3I_unop_rm_y<0x1C, "vpabsb", v32i8, abs, SSE_PABS>, VEX, VEX_L, VEX_WIG;
4965+
defm VPABSW : SS3I_unop_rm_y<0x1D, "vpabsw", v16i16, abs, SSE_PABS>, VEX, VEX_L, VEX_WIG;
49574966
}
49584967
let Predicates = [HasAVX2, NoVLX] in {
4959-
defm VPABSD : SS3I_unop_rm_y<0x1E, "vpabsd", v8i32, abs>, VEX, VEX_L, VEX_WIG;
4968+
defm VPABSD : SS3I_unop_rm_y<0x1E, "vpabsd", v8i32, abs, SSE_PABS>, VEX, VEX_L, VEX_WIG;
49604969
}
49614970

4962-
defm PABSB : SS3I_unop_rm<0x1C, "pabsb", v16i8, abs, memopv2i64>;
4963-
defm PABSW : SS3I_unop_rm<0x1D, "pabsw", v8i16, abs, memopv2i64>;
4964-
defm PABSD : SS3I_unop_rm<0x1E, "pabsd", v4i32, abs, memopv2i64>;
4971+
defm PABSB : SS3I_unop_rm<0x1C, "pabsb", v16i8, abs, SSE_PABS, memopv2i64>;
4972+
defm PABSW : SS3I_unop_rm<0x1D, "pabsw", v8i16, abs, SSE_PABS, memopv2i64>;
4973+
defm PABSD : SS3I_unop_rm<0x1E, "pabsd", v4i32, abs, SSE_PABS, memopv2i64>;
49654974

49664975
//===---------------------------------------------------------------------===//
49674976
// SSSE3 - Packed Binary Operator Instructions
@@ -5181,9 +5190,14 @@ defm PMULHRSW : SS3I_binop_rm<0x0B, "pmulhrsw", X86mulhrs, v8i16, v8i16,
51815190
// SSSE3 - Packed Align Instruction Patterns
51825191
//===---------------------------------------------------------------------===//
51835192

5193+
let Sched = WriteShuffle in
5194+
def SSE_PALIGN : OpndItins<
5195+
IIC_SSE_PALIGNRR, IIC_SSE_PALIGNRM
5196+
>;
5197+
51845198
multiclass ssse3_palignr<string asm, ValueType VT, RegisterClass RC,
51855199
PatFrag memop_frag, X86MemOperand x86memop,
5186-
bit Is2Addr = 1> {
5200+
OpndItins itins, bit Is2Addr = 1> {
51875201
let hasSideEffects = 0 in {
51885202
def rri : SS3AI<0x0F, MRMSrcReg, (outs RC:$dst),
51895203
(ins RC:$src1, RC:$src2, u8imm:$src3),
@@ -5192,7 +5206,7 @@ multiclass ssse3_palignr<string asm, ValueType VT, RegisterClass RC,
51925206
!strconcat(asm,
51935207
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
51945208
[(set RC:$dst, (VT (X86PAlignr RC:$src1, RC:$src2, (i8 imm:$src3))))],
5195-
IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5209+
itins.rr>, Sched<[itins.Sched]>;
51965210
let mayLoad = 1 in
51975211
def rmi : SS3AI<0x0F, MRMSrcMem, (outs RC:$dst),
51985212
(ins RC:$src1, x86memop:$src2, u8imm:$src3),
@@ -5203,19 +5217,19 @@ multiclass ssse3_palignr<string asm, ValueType VT, RegisterClass RC,
52035217
[(set RC:$dst, (VT (X86PAlignr RC:$src1,
52045218
(bitconvert (memop_frag addr:$src2)),
52055219
(i8 imm:$src3))))],
5206-
IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5220+
itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
52075221
}
52085222
}
52095223

52105224
let Predicates = [HasAVX, NoVLX_Or_NoBWI] in
52115225
defm VPALIGNR : ssse3_palignr<"vpalignr", v16i8, VR128, loadv2i64,
5212-
i128mem, 0>, VEX_4V, VEX_WIG;
5226+
i128mem, SSE_PALIGN, 0>, VEX_4V, VEX_WIG;
52135227
let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in
52145228
defm VPALIGNRY : ssse3_palignr<"vpalignr", v32i8, VR256, loadv4i64,
5215-
i256mem, 0>, VEX_4V, VEX_L, VEX_WIG;
5229+
i256mem, SSE_PALIGN, 0>, VEX_4V, VEX_L, VEX_WIG;
52165230
let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
52175231
defm PALIGNR : ssse3_palignr<"palignr", v16i8, VR128, memopv2i64,
5218-
i128mem>;
5232+
i128mem, SSE_PALIGN>;
52195233

52205234
//===---------------------------------------------------------------------===//
52215235
// SSSE3 - Thread synchronization

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