From 2062372d203b372849d573f252cf7c6dc2800c0a Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Mon, 1 Nov 2021 14:20:54 -0500
Subject: [PATCH 01/51] SDK 1.3.0 release

See release notes for details

Co-authored-by: Brian Cooke <bdscooke@gmail.com>
Co-authored-by: Luke Wren <wren6991@gmail.com>
Co-authored-by: Uri Shaked <uri@urishaked.com>
Co-authored-by: Zapta <zapta@users.noreply.github.com>
Co-authored-by: Andrew Scheller <andrew.scheller@raspberrypi.com>
Co-authored-by: Liam Fraser <liam@raspberrypi.com>
Co-authored-by: Gabriel Wang <embedded_zhuoran@Hotmail.com>
Co-authored-by: Matias Silva <matita.martins@gmail.com>
Co-authored-by: dp111 <19616418+dp111@users.noreply.github.com>
Co-authored-by: Leonardo La Rocca <46094699+leoli51@users.noreply.github.com>
Co-authored-by: Mahyar Koshkouei <mk@deltabeard.com>
Co-authored-by: Brian Starkey <stark3y@gmail.com>
Co-authored-by: Philip Howard <github@gadgetoid.com>
Co-authored-by: Mike Causer <mcauser@gmail.com>
Co-authored-by: Martino Facchin <m.facchin@arduino.cc>
Co-authored-by: ZodiusInfuser <christopher.parrott2@gmail.com>
Co-authored-by: Manuel Wick <manuel@matronix.de>
Co-authored-by: Matias Silva <git@matiasilva.com>
Co-authored-by: Robert Pafford <19439938+rjp5th@users.noreply.github.com>
Co-authored-by: Alasdair Allan <alasdair@raspberrypi.com>
Co-authored-by: Engineer_Will <646689853@qq.com>
Co-authored-by: Garatronic <31109090+garatronic@users.noreply.github.com>
---
 .github/pull_request_template.md              |   4 +
 CMakeLists.txt                                |   2 -
 CONTRIBUTING.md                               |  25 +
 docs/DoxygenLayout.xml                        |   4 +-
 docs/header.html                              |   2 +-
 docs/weblinks_page.md                         |   4 +-
 lib/tinyusb                                   |   2 +-
 pico_sdk_version.cmake                        |   3 +-
 src/CMakeLists.txt                            |   4 +-
 src/board_setup.cmake                         |   2 +-
 .../include/boards/adafruit_feather_rp2040.h  |  10 +-
 .../boards/adafruit_itsybitsy_rp2040.h        |   8 +-
 .../include/boards/adafruit_qtpy_rp2040.h     |   8 +-
 .../include/boards/adafruit_trinkey_qt2040.h  |  73 ++
 .../boards/arduino_nano_rp2040_connect.h      |  10 +-
 .../include/boards/melopero_shake_rp2040.h    |  91 +++
 src/boards/include/boards/pico.h              |   8 +-
 .../include/boards/pimoroni_interstate75.h    | 181 +++++
 .../include/boards/pimoroni_keybow2040.h      |   8 +-
 src/boards/include/boards/pimoroni_pga2040.h  |   8 +-
 .../include/boards/pimoroni_picolipo_16mb.h   |   8 +-
 .../include/boards/pimoroni_picolipo_4mb.h    |   8 +-
 .../include/boards/pimoroni_picosystem.h      |   8 +-
 .../include/boards/pimoroni_plasma2040.h      | 137 ++++
 src/boards/include/boards/pimoroni_tiny2040.h |   8 +-
 src/boards/include/boards/pybstick26_rp2040.h |  85 +++
 src/boards/include/boards/sparkfun_micromod.h |   8 +-
 src/boards/include/boards/sparkfun_promicro.h |   8 +-
 .../include/boards/sparkfun_thingplus.h       |   8 +-
 .../boards/waveshare_rp2040_lcd_0.96.h        | 104 +++
 .../boards/waveshare_rp2040_plus_16mb.h       |  84 +++
 .../boards/waveshare_rp2040_plus_4mb.h        |  84 +++
 .../include/boards/waveshare_rp2040_zero.h    |  79 +++
 src/common/CMakeLists.txt                     |   1 +
 src/common/pico_base/include/pico.h           |   9 +-
 src/common/pico_base/include/pico/config.h    |   2 +-
 src/common/pico_base/include/pico/error.h     |   4 +
 src/common/pico_base/include/pico/types.h     |   3 +
 src/common/pico_sync/include/pico/lock_core.h |   7 +
 src/common/pico_sync/include/pico/mutex.h     | 191 ++++--
 src/common/pico_sync/mutex.c                  | 157 +++--
 src/common/pico_time/include/pico/time.h      |  44 +-
 src/common/pico_time/time.c                   |  18 +-
 .../pico_usb_reset_interface/CMakeLists.txt   |   2 +
 .../include/pico/usb_reset_interface.h        |  28 +
 .../pico_util/include/pico/util/datetime.h    |   7 +
 .../hardware_gpio/include/hardware/gpio.h     |   2 +
 src/host/hardware_timer/timer.c               |   6 +-
 .../pico_platform/include/pico/platform.h     |  10 +-
 src/host/pico_stdio/include/pico/stdio.h      |   3 +
 .../include/hardware/platform_defs.h          |  22 +-
 .../hardware_regs/include/hardware/regs/dma.h | 312 ++++-----
 .../hardware_regs/include/hardware/regs/i2c.h |  74 ++
 .../hardware_regs/include/hardware/regs/pio.h |   6 +-
 .../hardware_regs/include/hardware/regs/sio.h |  88 +--
 .../hardware_regs/include/hardware/regs/usb.h |  14 +-
 .../include/hardware/regs/usb_device_dpram.h  |  64 +-
 .../include/hardware/regs/xosc.h              |  11 +-
 src/rp2040/hardware_regs/rp2040.svd           | 642 ++++++++++--------
 .../include/hardware/structs/adc.h            |  77 ++-
 .../include/hardware/structs/bus_ctrl.h       |  43 +-
 .../include/hardware/structs/clocks.h         | 278 +++++++-
 .../include/hardware/structs/dma.h            | 161 ++++-
 .../include/hardware/structs/i2c.h            | 385 ++++++++---
 .../include/hardware/structs/interp.h         |  58 +-
 .../include/hardware/structs/iobank0.h        | 197 +++++-
 .../include/hardware/structs/ioqspi.h         | 163 ++++-
 .../include/hardware/structs/mpu.h            |  40 +-
 .../include/hardware/structs/pads_qspi.h      |  32 +-
 .../include/hardware/structs/padsbank0.h      |  34 +-
 .../include/hardware/structs/pio.h            | 270 +++++++-
 .../include/hardware/structs/pll.h            |  33 +-
 .../include/hardware/structs/psm.h            |  94 ++-
 .../include/hardware/structs/pwm.h            | 101 ++-
 .../include/hardware/structs/resets.h         |  98 ++-
 .../include/hardware/structs/rosc.h           |  65 +-
 .../include/hardware/structs/rtc.h            |  95 ++-
 .../include/hardware/structs/scb.h            |  51 +-
 .../include/hardware/structs/sio.h            | 131 +++-
 .../include/hardware/structs/spi.h            |  79 ++-
 .../include/hardware/structs/ssi.h            | 193 +++++-
 .../include/hardware/structs/syscfg.h         |  55 +-
 .../include/hardware/structs/systick.h        |  32 +-
 .../include/hardware/structs/timer.h          |  80 ++-
 .../include/hardware/structs/uart.h           | 150 +++-
 .../include/hardware/structs/usb.h            | 455 ++++++++++++-
 .../hardware/structs/vreg_and_chip_reset.h    |  31 +-
 .../include/hardware/structs/watchdog.h       |  42 +-
 .../include/hardware/structs/xip_ctrl.h       |  57 +-
 .../include/hardware/structs/xosc.h           |  39 +-
 src/rp2_common.cmake                          |  12 +-
 src/rp2_common/CMakeLists.txt                 |   1 +
 src/rp2_common/boot_stage2/CMakeLists.txt     |   9 +-
 .../hardware_adc/include/hardware/adc.h       |  12 +-
 .../include/hardware/address_mapped.h         |  40 +-
 src/rp2_common/hardware_dma/dma.c             |  20 +
 .../hardware_dma/include/hardware/dma.h       |  69 ++
 .../include/hardware/exception.h              |   6 +-
 src/rp2_common/hardware_flash/flash.c         |  26 +-
 src/rp2_common/hardware_gpio/gpio.c           |   2 +-
 .../hardware_gpio/include/hardware/gpio.h     |  10 +-
 src/rp2_common/hardware_i2c/i2c.c             |  14 +-
 .../hardware_i2c/include/hardware/i2c.h       |  34 +-
 .../hardware_irq/include/hardware/irq.h       |  33 +-
 src/rp2_common/hardware_irq/irq.c             |  51 +-
 .../hardware_irq/irq_handler_chain.S          |   2 +-
 .../hardware_pio/include/hardware/pio.h       |  11 +-
 .../include/hardware/pio_instructions.h       | 357 +++++++++-
 .../hardware_pwm/include/hardware/pwm.h       |  61 +-
 .../hardware_spi/include/hardware/spi.h       |  14 +
 .../hardware_uart/include/hardware/uart.h     |  27 +-
 .../include/hardware/watchdog.h               |  29 +-
 src/rp2_common/hardware_watchdog/watchdog.c   |  31 +-
 src/rp2_common/hardware_xosc/xosc.c           |   4 +-
 src/rp2_common/pico_bit_ops/bit_ops_aeabi.S   |  10 +-
 src/rp2_common/pico_bootrom/bootrom.c         |   4 +-
 .../pico_bootrom/include/pico/bootrom.h       |  78 ++-
 .../pico_bootsel_via_double_reset.c           |   3 +-
 src/rp2_common/pico_divider/CMakeLists.txt    |   1 +
 src/rp2_common/pico_divider/divider.S         |   2 +
 src/rp2_common/pico_double/double_aeabi.S     |   8 +-
 src/rp2_common/pico_double/double_init_rom.c  |   8 +-
 src/rp2_common/pico_double/double_math.c      |  77 ++-
 .../pico_double/double_v1_rom_shim.S          |  18 +-
 .../rp2040_usb_device_enumeration.c           |  25 +-
 src/rp2_common/pico_float/float_aeabi.S       |  10 +-
 src/rp2_common/pico_float/float_init_rom.c    |   8 +-
 src/rp2_common/pico_float/float_math.c        |  77 ++-
 src/rp2_common/pico_float/float_v1_rom_shim.S |   2 +-
 src/rp2_common/pico_mem_ops/mem_ops_aeabi.S   |  25 +-
 .../pico_multicore/include/pico/multicore.h   | 185 ++++-
 src/rp2_common/pico_multicore/multicore.c     |  24 +-
 .../pico_platform/include/pico/asm_helper.S   |   8 +-
 .../pico_platform/include/pico/platform.h     | 331 +++++++--
 src/rp2_common/pico_runtime/runtime.c         |  38 +-
 .../pico_standard_link/CMakeLists.txt         |   4 +
 src/rp2_common/pico_standard_link/crt0.S      |   3 +-
 .../pico_stdio/include/pico/stdio.h           |  15 +-
 src/rp2_common/pico_stdio/stdio.c             |  37 +-
 .../stdio_semihosting.c                       |   6 +-
 src/rp2_common/pico_stdio_usb/CMakeLists.txt  |   1 +
 .../pico_stdio_usb/include/pico/stdio_usb.h   |  24 +-
 .../include/pico/stdio_usb/reset_interface.h  |  14 +-
 .../pico_stdio_usb/reset_interface.c          |   2 +-
 src/rp2_common/pico_stdio_usb/stdio_usb.c     |  26 +-
 .../pico_stdio_usb/stdio_usb_descriptors.c    |   2 +-
 .../pico_unique_id/include/pico/unique_id.h   |   2 +
 src/rp2_common/tinyusb/CMakeLists.txt         |   5 +-
 test/kitchen_sink/CMakeLists.txt              |   9 +-
 test/kitchen_sink/kitchen_sink.c              |  37 +-
 .../pico_divider_nesting_test.c               |  17 +
 tools/CMakeLists.txt                          |   8 +-
 tools/elf2uf2/main.cpp                        |   3 +
 tools/pioasm/gen/parser.cpp                   |  18 +-
 tools/pioasm/main.cpp                         |   4 +-
 tools/pioasm/parser.yy                        |   2 +-
 tools/pioasm/pio_assembler.cpp                |   2 +-
 tools/pioasm/python_output.cpp                |  24 +-
 158 files changed, 7078 insertions(+), 1436 deletions(-)
 create mode 100644 .github/pull_request_template.md
 create mode 100644 CONTRIBUTING.md
 create mode 100644 src/boards/include/boards/adafruit_trinkey_qt2040.h
 create mode 100644 src/boards/include/boards/melopero_shake_rp2040.h
 create mode 100644 src/boards/include/boards/pimoroni_interstate75.h
 create mode 100644 src/boards/include/boards/pimoroni_plasma2040.h
 create mode 100644 src/boards/include/boards/pybstick26_rp2040.h
 create mode 100644 src/boards/include/boards/waveshare_rp2040_lcd_0.96.h
 create mode 100644 src/boards/include/boards/waveshare_rp2040_plus_16mb.h
 create mode 100644 src/boards/include/boards/waveshare_rp2040_plus_4mb.h
 create mode 100644 src/boards/include/boards/waveshare_rp2040_zero.h
 create mode 100644 src/common/pico_usb_reset_interface/CMakeLists.txt
 create mode 100644 src/common/pico_usb_reset_interface/include/pico/usb_reset_interface.h

diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md
new file mode 100644
index 000000000..e3617774b
--- /dev/null
+++ b/.github/pull_request_template.md
@@ -0,0 +1,4 @@
+_Instructions: (please delete)_
+ - _please do not submit against `master`, use `develop` instead_
+ - _please make sure there is an associated issue for your PR, and reference it via "Fixes #num" in the description_
+ - _please enter a detailed description_
diff --git a/CMakeLists.txt b/CMakeLists.txt
index c270649c2..0ab4c317d 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -33,8 +33,6 @@ if (NOT TARGET _pico_sdk_inclusion_marker)
     add_subdirectory(tools)
     add_subdirectory(src)
 
-    add_compile_options(-Winline)
-
     # allow customization
     add_sub_list_dirs(PICO_SDK_POST_LIST_DIRS)
     add_sub_list_files(PICO_SDK_POST_LIST_FILES)
diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
new file mode 100644
index 000000000..dc69b2611
--- /dev/null
+++ b/CONTRIBUTING.md
@@ -0,0 +1,25 @@
+# Contributing to Raspberry Pi Pico C/C++ SDK
+
+## How to Report a Bug
+
+We use GitHub to host code, track [issues](https://github.com/raspberrypi/pico-sdk/issues) and feature requests, and to accept [pull requests](https://github.com/raspberrypi/pico-sdk/pulls). If you find think you have found a bug in the SDK please report it by [opening a new issue](https://github.com/raspberrypi/pico-sdk/issues/new). Please include as much detail as possible, and ideally some code to reproduce the problem.
+
+## How to Contribute Code
+
+In order to contribute new or updated code, you must first create a GitHub account and fork the original repository to your own account. You can make changes, save them in your repository, then [make a pull request](https://docs.github.com/en/github/collaborating-with-pull-requests/proposing-changes-to-your-work-with-pull-requests/creating-a-pull-request-from-a-fork) against this repository. The pull request will appear [in the repository](https://github.com/raspberrypi/pico-sdk/pulls) where it can be assessed by the maintainers, and if appropriate, merged with the official repository.
+
+**NOTE:** Development takes place on the `develop` branch in this repository. Please open your https://github.com/raspberrypi/pico-sdk/pulls[pull request] (PR) against the [`develop`](https://github.com/raspberrypi/pico-sdk/tree/develop) branch, pull requests against the `master` branch will automatically CI fail checks and will not be accepted. You will be asked to rebase your PR against `develop` and if you do not do so, your PR will be closed.
+
+While we are happy to take contributions, big or small, changes in the SDK may have knock-on effects in other places so it is possible that apparently benign pull requests that make seemingly small changes could be refused. 
+
+### Code Style
+
+If you are contributing new or updated code please match the existing code style, particularly:
+
+* Use 4 spaces for indentation rather than tabs.
+* Braces are required for everything except single line `if` statements.
+* Opening braces should not be placed on a new line.
+
+### Licensing 
+
+Code in this repository is lisensed under the [BSD-3 License](LICENSE.TXT). By contributing content to this repository you are agreeing to place your contributions under this licence.
diff --git a/docs/DoxygenLayout.xml b/docs/DoxygenLayout.xml
index e0fd3960a..6ba5dfcd6 100644
--- a/docs/DoxygenLayout.xml
+++ b/docs/DoxygenLayout.xml
@@ -15,9 +15,9 @@
       <tab type="user" url="https://rptl.io/pico-faq" visible="yes" title="Raspberry Pi Pico FAQ" intro=""/>
     </tab>
     <tab type="usergroup" url="@ref weblinks_page" visible="yes" title="Web" intro="useful weblinks">
-      <tab type="user" url="https://www.raspberrypi.org/" visible="yes" title="Raspberry Pi Site" intro=""/>
+      <tab type="user" url="https://www.raspberrypi.com/" visible="yes" title="Raspberry Pi Site" intro=""/>
       <tab type="user" url="https://rptl.io/rp2040-get-started" visible="yes" title="Raspberry Pi Pico Page" intro=""/>
-      <tab type="user" url="https://www.raspberrypi.org/forums" visible="yes" title="Raspberry Pi Forums" intro=""/>
+      <tab type="user" url="https://forums.raspberrypi.com/" visible="yes" title="Raspberry Pi Forums" intro=""/>
       <tab type="user" url="https://github.com/raspberrypi/pico-sdk" visible="yes" title="Raspberry Pi Pico SDK on GitHub" intro=""/>
       <tab type="user" url="https://github.com/raspberrypi/pico-examples" visible="yes" title="Pico Examples on GitHub" intro=""/>
       <tab type="user" url="https://github.com/raspberrypi/pico-extras" visible="yes" title="Pico Extras on GitHub" intro=""/>
diff --git a/docs/header.html b/docs/header.html
index da3cd81a2..32bb7eb7e 100644
--- a/docs/header.html
+++ b/docs/header.html
@@ -54,7 +54,7 @@
 
 		<div class="navigation-footer">
 			<img src="logo-mobile.svg" alt="Raspberry Pi">
-			<a href="https://www.raspberrypi.org/" target="_blank">By Raspberry Pi (Trading) Ltd</a>
+			<a href="https://www.raspberrypi.com/" target="_blank">By Raspberry Pi (Trading) Ltd</a>
 		</div>
 <!-- 		<div class="search">
 			<form>
diff --git a/docs/weblinks_page.md b/docs/weblinks_page.md
index d4b0e9cfa..e57936281 100644
--- a/docs/weblinks_page.md
+++ b/docs/weblinks_page.md
@@ -14,9 +14,9 @@ The full documentation for the RP2040 and Raspberry Pi Pico board can be found a
 
 At Raspberry Pi we have a very community-based attitude to help. We run a very popular and busy forum where you can ask questions about any aspect of the Raspberry Pi ecosystem, including the Raspberry Pi Pico.
 
-You can find our forums at the [following link](https://www.raspberrypi.org/forums).
+You can find our forums at the [following link](https://forums.raspberrypi.com/).
 
-For the main Raspberry Pi website, [see here](https://www.raspberrypi.org)
+For the main Raspberry Pi website, [see here](https://www.raspberrypi.com)
 
 For the Raspberry Pi Pico page, [see here](https://rptl.io/rp2040-get-started)
 
diff --git a/lib/tinyusb b/lib/tinyusb
index d49938d0f..4bfab30c0 160000
--- a/lib/tinyusb
+++ b/lib/tinyusb
@@ -1 +1 @@
-Subproject commit d49938d0f5052bce70e55c652b657c0a6a7e84fe
+Subproject commit 4bfab30c02279a0530e1a56f4a7c539f2d35a293
diff --git a/pico_sdk_version.cmake b/pico_sdk_version.cmake
index a2d844462..1605f5658 100644
--- a/pico_sdk_version.cmake
+++ b/pico_sdk_version.cmake
@@ -3,12 +3,13 @@
 set(PICO_SDK_VERSION_MAJOR 1)
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, group=pico_base
 # PICO_CONFIG: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, group=pico_base
-set(PICO_SDK_VERSION_MINOR 2)
+set(PICO_SDK_VERSION_MINOR 3)
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, group=pico_base
 # PICO_CONFIG: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, group=pico_base
 set(PICO_SDK_VERSION_REVISION 0)
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base
 # PICO_CONFIG: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base
+#set(PICO_SDK_VERSION_PRE_RELEASE_ID develop)
 
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base
 # PICO_CONFIG: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index 59f293366..f800c2f86 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -36,9 +36,9 @@ endfunction()
 function(pico_add_map_output TARGET)
     get_target_property(target_type ${TARGET} TYPE)
     if ("EXECUTABLE" STREQUAL "${target_type}")
-        target_link_options(${TARGET} PRIVATE "LINKER:-Map=$<TARGET_PROPERTY:NAME>${CMAKE_EXECUTABLE_SUFFIX}.map")
+        target_link_options(${TARGET} PRIVATE "LINKER:-Map=$<IF:$<BOOL:$<TARGET_PROPERTY:OUTPUT_NAME>>,$<TARGET_PROPERTY:OUTPUT_NAME>,$<TARGET_PROPERTY:NAME>>${CMAKE_EXECUTABLE_SUFFIX}.map")
     else ()
-        target_link_options(${TARGET} INTERFACE "LINKER:-Map=$<TARGET_PROPERTY:NAME>${CMAKE_EXECUTABLE_SUFFIX}.map")
+        target_link_options(${TARGET} INTERFACE "LINKER:-Map=$<IF:$<BOOL:$<TARGET_PROPERTY:OUTPUT_NAME>>,$<TARGET_PROPERTY:OUTPUT_NAME>,$<TARGET_PROPERTY:NAME>>${CMAKE_EXECUTABLE_SUFFIX}.map")
     endif ()
 endfunction()
 
diff --git a/src/board_setup.cmake b/src/board_setup.cmake
index 86b80f9e0..405d78485 100644
--- a/src/board_setup.cmake
+++ b/src/board_setup.cmake
@@ -1,4 +1,4 @@
-# PICO_CMAKE_CONFIG: PICO_BOARD, The board name being built for. This is overridable from the user environment, type=string, default=rp2040, group=build
+# PICO_CMAKE_CONFIG: PICO_BOARD, The board name being built for. This is overridable from the user environment, type=string, default=pico, group=build
 if (DEFINED ENV{PICO_BOARD})
     set(PICO_BOARD $ENV{PICO_BOARD})
     message("Using PICO_BOARD from environment ('${PICO_BOARD}')")
diff --git a/src/boards/include/boards/adafruit_feather_rp2040.h b/src/boards/include/boards/adafruit_feather_rp2040.h
index 5049f6b71..2da8e7009 100644
--- a/src/boards/include/boards/adafruit_feather_rp2040.h
+++ b/src/boards/include/boards/adafruit_feather_rp2040.h
@@ -44,7 +44,7 @@
 
 //------------- I2C -------------//
 #ifndef PICO_DEFAULT_I2C
-#define PICO_DEFAULT_I2C 0
+#define PICO_DEFAULT_I2C 1
 #endif
 
 #ifndef PICO_DEFAULT_I2C_SDA_PIN
@@ -86,12 +86,8 @@
 #endif
 
 // All boards have B1 RP2040
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
 #endif
 
 #endif
diff --git a/src/boards/include/boards/adafruit_itsybitsy_rp2040.h b/src/boards/include/boards/adafruit_itsybitsy_rp2040.h
index 26cde1dbd..f9d27e919 100644
--- a/src/boards/include/boards/adafruit_itsybitsy_rp2040.h
+++ b/src/boards/include/boards/adafruit_itsybitsy_rp2040.h
@@ -89,12 +89,8 @@
 #endif
 
 // All boards have B1 RP2040
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
 #endif
 
 #endif
diff --git a/src/boards/include/boards/adafruit_qtpy_rp2040.h b/src/boards/include/boards/adafruit_qtpy_rp2040.h
index 299249de8..24184c27f 100644
--- a/src/boards/include/boards/adafruit_qtpy_rp2040.h
+++ b/src/boards/include/boards/adafruit_qtpy_rp2040.h
@@ -88,12 +88,8 @@
 #endif
 
 // All boards have B1 RP2040
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
 #endif
 
 #endif
diff --git a/src/boards/include/boards/adafruit_trinkey_qt2040.h b/src/boards/include/boards/adafruit_trinkey_qt2040.h
new file mode 100644
index 000000000..f9b49df74
--- /dev/null
+++ b/src/boards/include/boards/adafruit_trinkey_qt2040.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_ADAFRUIT_TRINKEY_QT2040_H
+#define _BOARDS_ADAFRUIT_TRINKEY_QT2040_H
+
+// For board detection
+#define ADAFRUIT_TRINKEY_QT2040
+
+// On some samples, the xosc can take longer to stabilize than is usual
+#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER
+#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64
+#endif
+
+//------------- UART -------------//
+// no PICO_DEFAULT_UART
+// no PICO_DEFAULT_UART_TX_PIN
+// no PICO_DEFAULT_UART_RX_PIN
+
+//------------- LED -------------//
+// No normal LED
+// #define PICO_DEFAULT_LED_PIN 13
+
+#ifndef PICO_DEFAULT_WS2812_PIN
+#define PICO_DEFAULT_WS2812_PIN 27
+#endif
+
+//------------- I2C -------------//
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 16
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 17
+#endif
+
+//------------- SPI -------------//
+// no PICO_DEFAULT_SPI
+// no PICO_DEFAULT_SPI_SCK_PIN
+// no PICO_DEFAULT_SPI_TX_PIN
+// no PICO_DEFAULT_SPI_RX_PIN
+// no PICO_DEFAULT_SPI_CSN_PIN
+
+//------------- FLASH -------------//
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/arduino_nano_rp2040_connect.h b/src/boards/include/boards/arduino_nano_rp2040_connect.h
index 9725cb792..39c6564fb 100644
--- a/src/boards/include/boards/arduino_nano_rp2040_connect.h
+++ b/src/boards/include/boards/arduino_nano_rp2040_connect.h
@@ -66,7 +66,7 @@
 
 //------------- FLASH -------------//
 
-#define PICO_BOOT_STAGE2_CHOOSE_AT25SF128A 1
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
 
 #ifndef PICO_FLASH_SPI_CLKDIV
 #define PICO_FLASH_SPI_CLKDIV 2
@@ -77,12 +77,8 @@
 #endif
 
 // All boards have B1 RP2040
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
 #endif
 
 #endif
diff --git a/src/boards/include/boards/melopero_shake_rp2040.h b/src/boards/include/boards/melopero_shake_rp2040.h
new file mode 100644
index 000000000..d07ca6123
--- /dev/null
+++ b/src/boards/include/boards/melopero_shake_rp2040.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_MELOPERO_SHAKE_RP2040_H
+#define _BOARDS_MELOPERO_SHAKE_RP2040_H
+
+// For board detection
+#define MELOPERO_SHAKE_RP2040
+
+//------------- UART -------------//
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 1
+#endif
+
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 8
+#endif
+
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 9
+#endif
+
+//------------- LED -------------//
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 13
+#endif
+
+#ifndef PICO_DEFAULT_WS2812_PIN
+#define PICO_DEFAULT_WS2812_PIN 16
+#endif
+
+//------------- I2C -------------//
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 1
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 2
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 3
+#endif
+
+//------------- SPI -------------//
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 20
+#endif
+
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 1
+#endif
+
+//------------- FLASH -------------//
+
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
+#endif
+
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/pico.h b/src/boards/include/boards/pico.h
index 313d08512..9e7f53752 100644
--- a/src/boards/include/boards/pico.h
+++ b/src/boards/include/boards/pico.h
@@ -77,12 +77,8 @@
 // Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads)
 #define PICO_SMPS_MODE_PIN 23
 
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
-#define PICO_FLOAT_SUPPORT_ROM_V1 1
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 1
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 1
 #endif
 
 #endif
diff --git a/src/boards/include/boards/pimoroni_interstate75.h b/src/boards/include/boards/pimoroni_interstate75.h
new file mode 100644
index 000000000..e2621b0bf
--- /dev/null
+++ b/src/boards/include/boards/pimoroni_interstate75.h
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_PIMORONI_INTERSTATE75_H
+#define _BOARDS_PIMORONI_INTERSTATE75_H
+
+// For board detection
+#define PIMORONI_INTERSTATE75
+
+// --- BOARD SPECIFIC ---
+#ifndef INTERSTATE75_R0_PIN
+#define INTERSTATE75_R0_PIN 0
+#endif
+
+#ifndef INTERSTATE75_G0_PIN
+#define INTERSTATE75_G0_PIN 1
+#endif
+
+#ifndef INTERSTATE75_B0_PIN
+#define INTERSTATE75_B0_PIN 2
+#endif
+
+#ifndef INTERSTATE75_R1_PIN
+#define INTERSTATE75_R1_PIN 3
+#endif
+
+#ifndef INTERSTATE75_G1_PIN
+#define INTERSTATE75_G1_PIN 4
+#endif
+
+#ifndef INTERSTATE75_B1_PIN
+#define INTERSTATE75_B1_PIN 5
+#endif
+
+#ifndef INTERSTATE75_ROW_A_PIN
+#define INTERSTATE75_ROW_A_PIN 6
+#endif
+
+#ifndef INTERSTATE75_ROW_B_PIN
+#define INTERSTATE75_ROW_B_PIN 7
+#endif
+
+#ifndef INTERSTATE75_ROW_C_PIN
+#define INTERSTATE75_ROW_C_PIN 8
+#endif
+
+#ifndef INTERSTATE75_ROW_D_PIN
+#define INTERSTATE75_ROW_D_PIN 9
+#endif
+
+#ifndef INTERSTATE75_ROW_E_PIN
+#define INTERSTATE75_ROW_E_PIN 10
+#endif
+
+#ifndef INTERSTATE75_CLK_PIN
+#define INTERSTATE75_CLK_PIN 11
+#endif
+
+#ifndef INTERSTATE75_LAT_PIN
+#define INTERSTATE75_LAT_PIN 12
+#endif
+
+#ifndef INTERSTATE75_OE_PIN
+#define INTERSTATE75_OE_PIN 13
+#endif
+
+#ifndef INTERSTATE75_SW_A_PIN
+#define INTERSTATE75_SW_A_PIN 14
+#endif
+
+#ifndef INTERSTATE75_LED_R_PIN
+#define INTERSTATE75_LED_R_PIN 16
+#endif
+
+#ifndef INTERSTATE75_LED_G_PIN
+#define INTERSTATE75_LED_G_PIN 17
+#endif
+
+#ifndef INTERSTATE75_LED_B_PIN
+#define INTERSTATE75_LED_B_PIN 18
+#endif
+
+#ifndef INTERSTATE75_I2C
+#define INTERSTATE75_I2C 0
+#endif
+
+#ifndef INTERSTATE75_INT_PIN
+#define INTERSTATE75_INT_PIN 19
+#endif
+
+#ifndef INTERSTATE75_SDA_PIN
+#define INTERSTATE75_SDA_PIN 20
+#endif
+
+#ifndef INTERSTATE75_SCL_PIN
+#define INTERSTATE75_SCL_PIN 21
+#endif
+
+#ifndef INTERSTATE75_USER_SW_PIN
+#define INTERSTATE75_USER_SW_PIN 23
+#endif
+
+#ifndef INTERSTATE75_A0_PIN
+#define INTERSTATE75_A0_PIN 26
+#endif
+
+#ifndef INTERSTATE75_A1_PIN
+#define INTERSTATE75_A1_PIN 27
+#endif
+
+#ifndef INTERSTATE75_A2_PIN
+#define INTERSTATE75_A2_PIN 28
+#endif
+
+#ifndef INTERSTATE75_NUM_ADC_PINS
+#define INTERSTATE75_NUM_ADC_PINS 3
+#endif
+
+#ifndef INTERSTATE75_CURRENT_SENSE_PIN
+#define INTERSTATE75_CURRENT_SENSE_PIN 29
+#endif
+
+// --- UART ---
+// no PICO_DEFAULT_UART
+// no PICO_DEFAULT_UART_TX_PIN
+// no PICO_DEFAULT_UART_RX_PIN
+
+// --- LED ---
+// Included so basic examples will work, and set it to the green LED
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN INTERSTATE75_LED_G_PIN
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+#ifndef PICO_DEFAULT_LED_PIN_INVERTED
+#define PICO_DEFAULT_LED_PIN_INVERTED 1
+#endif
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C INTERSTATE75_I2C
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN INTERSTATE75_SDA_PIN
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN INTERSTATE75_SCL_PIN
+#endif
+
+// --- SPI ---
+// no PICO_DEFAULT_SPI
+// no PICO_DEFAULT_SPI_SCK_PIN
+// no PICO_DEFAULT_SPI_TX_PIN
+// no PICO_DEFAULT_SPI_RX_PIN
+// no PICO_DEFAULT_SPI_CSN_PIN
+
+// --- FLASH ---
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/pimoroni_keybow2040.h b/src/boards/include/boards/pimoroni_keybow2040.h
index 8cd6c1bef..43772e840 100644
--- a/src/boards/include/boards/pimoroni_keybow2040.h
+++ b/src/boards/include/boards/pimoroni_keybow2040.h
@@ -147,12 +147,8 @@
 #endif
 
 // All boards have B1 RP2040
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
 #endif
 
 #endif
diff --git a/src/boards/include/boards/pimoroni_pga2040.h b/src/boards/include/boards/pimoroni_pga2040.h
index 90340fae9..980f16800 100644
--- a/src/boards/include/boards/pimoroni_pga2040.h
+++ b/src/boards/include/boards/pimoroni_pga2040.h
@@ -72,12 +72,8 @@
 #endif
 
 // All boards have B1 RP2040
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
 #endif
 
 #endif
diff --git a/src/boards/include/boards/pimoroni_picolipo_16mb.h b/src/boards/include/boards/pimoroni_picolipo_16mb.h
index a0310fb77..338977b44 100644
--- a/src/boards/include/boards/pimoroni_picolipo_16mb.h
+++ b/src/boards/include/boards/pimoroni_picolipo_16mb.h
@@ -85,12 +85,8 @@
 #endif
 
 // All boards have B1 RP2040
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
 #endif
 
 #endif
diff --git a/src/boards/include/boards/pimoroni_picolipo_4mb.h b/src/boards/include/boards/pimoroni_picolipo_4mb.h
index 9374f4117..871ed8368 100644
--- a/src/boards/include/boards/pimoroni_picolipo_4mb.h
+++ b/src/boards/include/boards/pimoroni_picolipo_4mb.h
@@ -85,12 +85,8 @@
 #endif
 
 // All boards have B1 RP2040
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
 #endif
 
 #endif
diff --git a/src/boards/include/boards/pimoroni_picosystem.h b/src/boards/include/boards/pimoroni_picosystem.h
index 34eb6436e..1e7c80e82 100644
--- a/src/boards/include/boards/pimoroni_picosystem.h
+++ b/src/boards/include/boards/pimoroni_picosystem.h
@@ -156,12 +156,8 @@
 #endif
 
 // All boards have B1 RP2040
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
 #endif
 
 #endif
diff --git a/src/boards/include/boards/pimoroni_plasma2040.h b/src/boards/include/boards/pimoroni_plasma2040.h
new file mode 100644
index 000000000..226aaf538
--- /dev/null
+++ b/src/boards/include/boards/pimoroni_plasma2040.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_PIMORONI_PLASMA2040_H
+#define _BOARDS_PIMORONI_PLASMA2040_H
+
+// For board detection
+#define PIMORONI_PLASMA2040
+
+// --- BOARD SPECIFIC ---
+#ifndef PLASMA2040_SW_A_PIN
+#define PLASMA2040_SW_A_PIN 12
+#endif
+
+#ifndef PLASMA2040_SW_B_PIN
+#define PLASMA2040_SW_B_PIN 13
+#endif
+
+#ifndef PLASMA2040_CLK_PIN
+#define PLASMA2040_CLK_PIN 14
+#endif
+
+#ifndef PLASMA2040_DATA_PIN
+#define PLASMA2040_DATA_PIN 15
+#endif
+
+#ifndef PLASMA2040_LED_R_PIN
+#define PLASMA2040_LED_R_PIN 16
+#endif
+
+#ifndef PLASMA2040_LED_G_PIN
+#define PLASMA2040_LED_G_PIN 17
+#endif
+
+#ifndef PLASMA2040_LED_B_PIN
+#define PLASMA2040_LED_B_PIN 18
+#endif
+
+#ifndef PLASMA2040_I2C
+#define PLASMA2040_I2C 0
+#endif
+
+#ifndef PLASMA2040_INT_PIN
+#define PLASMA2040_INT_PIN 19
+#endif
+
+#ifndef PLASMA2040_SDA_PIN
+#define PLASMA2040_SDA_PIN 20
+#endif
+
+#ifndef PLASMA2040_SCL_PIN
+#define PLASMA2040_SCL_PIN 21
+#endif
+
+#ifndef PLASMA2040_USER_SW_PIN
+#define PLASMA2040_USER_SW_PIN 23
+#endif
+
+#ifndef PLASMA2040_A0_PIN
+#define PLASMA2040_A0_PIN 26
+#endif
+
+#ifndef PLASMA2040_A1_PIN
+#define PLASMA2040_A1_PIN 27
+#endif
+
+#ifndef PLASMA2040_A2_PIN
+#define PLASMA2040_A2_PIN 28
+#endif
+
+#ifndef PLASMA2040_NUM_ADC_PINS
+#define PLASMA2040_NUM_ADC_PINS 3
+#endif
+
+#ifndef PLASMA2040_CURRENT_SENSE_PIN
+#define PLASMA2040_CURRENT_SENSE_PIN 29
+#endif
+
+// --- UART ---
+// no PICO_DEFAULT_UART
+// no PICO_DEFAULT_UART_TX_PIN
+// no PICO_DEFAULT_UART_RX_PIN
+
+// --- LED ---
+// Included so basic examples will work, and set it to the green LED
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN PLASMA2040_LED_G_PIN
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+#ifndef PICO_DEFAULT_LED_PIN_INVERTED
+#define PICO_DEFAULT_LED_PIN_INVERTED 1
+#endif
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C PLASMA2040_I2C
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN PLASMA2040_SDA_PIN
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN PLASMA2040_SCL_PIN
+#endif
+
+// --- SPI ---
+// no PICO_DEFAULT_SPI
+// no PICO_DEFAULT_SPI_SCK_PIN
+// no PICO_DEFAULT_SPI_TX_PIN
+// no PICO_DEFAULT_SPI_RX_PIN
+// no PICO_DEFAULT_SPI_CSN_PIN
+
+// --- FLASH ---
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/pimoroni_tiny2040.h b/src/boards/include/boards/pimoroni_tiny2040.h
index 81605b37b..51d17f66a 100644
--- a/src/boards/include/boards/pimoroni_tiny2040.h
+++ b/src/boards/include/boards/pimoroni_tiny2040.h
@@ -120,12 +120,8 @@
 #endif
 
 // All boards have B1 RP2040
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
 #endif
 
 #endif
diff --git a/src/boards/include/boards/pybstick26_rp2040.h b/src/boards/include/boards/pybstick26_rp2040.h
new file mode 100644
index 000000000..8a9ca4156
--- /dev/null
+++ b/src/boards/include/boards/pybstick26_rp2040.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_PYBSTICK26_RP2040_H
+#define _BOARDS_PYBSTICK26_RP2040_H
+
+// For board detection
+#define PYBSTICK26_RP2040
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 23
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 1 
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 6
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 7 
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 1
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 10
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 11
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 8
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 9
+#endif
+
+// --- FLASH ---
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2 
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (1 * 1024 * 1024)
+#endif
+
+// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads)
+// Linear regulator on Pybstick26
+//#define PICO_SMPS_MODE_PIN 23
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED 
+#define PICO_RP2040_B0_SUPPORTED  0
+#endif
+
+#endif
+// of #define _BOARDS_PYBSTICK26_RP2040_H
diff --git a/src/boards/include/boards/sparkfun_micromod.h b/src/boards/include/boards/sparkfun_micromod.h
index e6ef44fee..0c6e5687c 100644
--- a/src/boards/include/boards/sparkfun_micromod.h
+++ b/src/boards/include/boards/sparkfun_micromod.h
@@ -79,12 +79,8 @@
 
 // All boards have B1 RP2040
 
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
 #endif
 
 #endif
diff --git a/src/boards/include/boards/sparkfun_promicro.h b/src/boards/include/boards/sparkfun_promicro.h
index 82e96cf06..45bb4a244 100644
--- a/src/boards/include/boards/sparkfun_promicro.h
+++ b/src/boards/include/boards/sparkfun_promicro.h
@@ -79,12 +79,8 @@
 
 // All boards have B1 RP2040
 
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
 #endif
 
 #endif
diff --git a/src/boards/include/boards/sparkfun_thingplus.h b/src/boards/include/boards/sparkfun_thingplus.h
index b2e493204..d1e69d566 100644
--- a/src/boards/include/boards/sparkfun_thingplus.h
+++ b/src/boards/include/boards/sparkfun_thingplus.h
@@ -85,12 +85,8 @@
 
 // All boards have B1 RP2040
 
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
 #endif
 
 #endif
diff --git a/src/boards/include/boards/waveshare_rp2040_lcd_0.96.h b/src/boards/include/boards/waveshare_rp2040_lcd_0.96.h
new file mode 100644
index 000000000..8c59c5c49
--- /dev/null
+++ b/src/boards/include/boards/waveshare_rp2040_lcd_0.96.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+
+#ifndef _BOARDS_WAVESHARE_RP2040_LCD_0_96_H
+#define _BOARDS_WAVESHARE_RP2040_LCD_0_96_H
+
+// For board detection
+#define WAVESHARE_RP2040_LCD_0_96
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 4
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 5
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 16
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 17
+#endif
+
+// --- LCD ---
+#ifndef WAVESHARE_RP2040_LCD_SPI
+#define WAVESHARE_RP2040_LCD_SPI 1
+#endif
+#ifndef WAVESHARE_RP2040_LCD_DC_PIN
+#define WAVESHARE_RP2040_LCD_DC_PIN 8
+#endif
+#ifndef WAVESHARE_RP2040_LCD_CS_PIN
+#define WAVESHARE_RP2040_LCD_CS_PIN 9
+#endif
+#ifndef WAVESHARE_RP2040_LCD_SCLK_PIN
+#define WAVESHARE_RP2040_LCD_SCLK_PIN 10
+#endif
+#ifndef WAVESHARE_RP2040_LCD_TX_PIN
+#define WAVESHARE_RP2040_LCD_TX_PIN 11
+#endif
+#ifndef WAVESHARE_RP2040_LCD_RST_PIN
+#define WAVESHARE_RP2040_LCD_RST_PIN 12
+#endif
+#ifndef WAVESHARE_RP2040_LCD_BL_PIN
+#define WAVESHARE_RP2040_LCD_BL_PIN 25
+#endif
+
+// --- FLASH ---
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024)
+#endif
+
+// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads)
+#define PICO_SMPS_MODE_PIN 23
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED 
+#define PICO_RP2040_B0_SUPPORTED  0
+#endif
+
+#endif
+
diff --git a/src/boards/include/boards/waveshare_rp2040_plus_16mb.h b/src/boards/include/boards/waveshare_rp2040_plus_16mb.h
new file mode 100644
index 000000000..6f5e1441c
--- /dev/null
+++ b/src/boards/include/boards/waveshare_rp2040_plus_16mb.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+
+#ifndef _BOARDS_WAVESHARE_RP2040_PLUS_16MB_H
+#define _BOARDS_WAVESHARE_RP2040_PLUS_16MB_H
+
+// For board detection
+#define WAVESHARE_RP2040_PLUS_16MB
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 25
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 1
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 6
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 7
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 16
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 17
+#endif
+
+// --- FLASH ---
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
+#endif
+
+// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads)
+#define PICO_SMPS_MODE_PIN 23
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED 
+#define PICO_RP2040_B0_SUPPORTED  0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/waveshare_rp2040_plus_4mb.h b/src/boards/include/boards/waveshare_rp2040_plus_4mb.h
new file mode 100644
index 000000000..d8dd8f6b3
--- /dev/null
+++ b/src/boards/include/boards/waveshare_rp2040_plus_4mb.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+
+#ifndef _BOARDS_WAVESHARE_RP2040_PLUS_4MB_H
+#define _BOARDS_WAVESHARE_RP2040_PLUS_4MB_H
+
+// For board detection
+#define WAVESHARE_RP2040_PLUS_4MB
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 25
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 1
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 6
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 7
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 16
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 17
+#endif
+
+// --- FLASH ---
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024)
+#endif
+
+// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads)
+#define PICO_SMPS_MODE_PIN 23
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED 
+#define PICO_RP2040_B0_SUPPORTED  0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/waveshare_rp2040_zero.h b/src/boards/include/boards/waveshare_rp2040_zero.h
new file mode 100644
index 000000000..281b4dc8b
--- /dev/null
+++ b/src/boards/include/boards/waveshare_rp2040_zero.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+
+#ifndef _BOARDS_WAVESHARE_RP2040_ZERO_H
+#define _BOARDS_WAVESHARE_RP2040_ZERO_H
+
+// For board detection
+#define WAVESHARE_RP2040_ZERO
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- WS2812 ---
+#ifndef PICO_DEFAULT_WS2812_PIN
+#define PICO_DEFAULT_WS2812_PIN 16
+#endif
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 1
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 6
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 7
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 1
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 10
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 11
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 12
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 13
+#endif
+
+// --- FLASH ---
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED 
+#define PICO_RP2040_B0_SUPPORTED  0
+#endif
+
+#endif
diff --git a/src/common/CMakeLists.txt b/src/common/CMakeLists.txt
index 9948db0ab..38cf23818 100644
--- a/src/common/CMakeLists.txt
+++ b/src/common/CMakeLists.txt
@@ -1,6 +1,7 @@
 pico_add_subdirectory(boot_picoboot)
 pico_add_subdirectory(boot_uf2)
 pico_add_subdirectory(pico_base)
+pico_add_subdirectory(pico_usb_reset_interface)
 
 # PICO_CMAKE_CONFIG: PICO_BARE_METAL, Flag to exclude anything except base headers from the build, type=bool, default=0, group=build
 if (NOT PICO_BARE_METAL)
diff --git a/src/common/pico_base/include/pico.h b/src/common/pico_base/include/pico.h
index c7537b112..1b7365120 100644
--- a/src/common/pico_base/include/pico.h
+++ b/src/common/pico_base/include/pico.h
@@ -8,9 +8,12 @@
 #define PICO_H_
 
 /** \file pico.h
-*  \defgroup pico_base pico_base
-*
-* Core types and macros for the Raspberry Pi Pico SDK. This header is intended to be included by all source code
+ *  \defgroup pico_base pico_base
+ *
+ * Core types and macros for the Raspberry Pi Pico SDK. This header is intended to be included by all source code
+ * as it includes configuration headers and overrides in the correct order
+ *
+ * This header may be included by assembly code
 */
 
 #include "pico/types.h"
diff --git a/src/common/pico_base/include/pico/config.h b/src/common/pico_base/include/pico/config.h
index 20f32cb90..8d6926941 100644
--- a/src/common/pico_base/include/pico/config.h
+++ b/src/common/pico_base/include/pico/config.h
@@ -8,7 +8,7 @@
 #define PICO_CONFIG_H_
 
 // -----------------------------------------------------
-// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLY CODE SO
 //       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
 //       OR USE #ifndef __ASSEMBLER__ guards
 // -------------
diff --git a/src/common/pico_base/include/pico/error.h b/src/common/pico_base/include/pico/error.h
index 722a696f5..fadb45ec0 100644
--- a/src/common/pico_base/include/pico/error.h
+++ b/src/common/pico_base/include/pico/error.h
@@ -7,6 +7,8 @@
 #ifndef _PICO_ERROR_H
 #define _PICO_ERROR_H
 
+#ifndef __ASSEMBLER__
+
 /*!
  * Common return codes from pico_sdk methods that return a status
  */
@@ -18,4 +20,6 @@ enum {
     PICO_ERROR_NO_DATA = -3,
 };
 
+#endif // !__ASSEMBLER__
+
 #endif
\ No newline at end of file
diff --git a/src/common/pico_base/include/pico/types.h b/src/common/pico_base/include/pico/types.h
index 6b8e66f62..8e1627ca8 100644
--- a/src/common/pico_base/include/pico/types.h
+++ b/src/common/pico_base/include/pico/types.h
@@ -7,6 +7,8 @@
 #ifndef _PICO_TYPES_H
 #define _PICO_TYPES_H
 
+#ifndef __ASSEMBLER__
+
 #include "pico/assert.h"
 
 #include <stdint.h>
@@ -89,3 +91,4 @@ typedef struct {
 #define bool_to_bit(x) ((uint)!!(x))
 
 #endif
+#endif
diff --git a/src/common/pico_sync/include/pico/lock_core.h b/src/common/pico_sync/include/pico/lock_core.h
index fc676cc71..bf8bee793 100644
--- a/src/common/pico_sync/include/pico/lock_core.h
+++ b/src/common/pico_sync/include/pico/lock_core.h
@@ -93,6 +93,13 @@ void lock_init(lock_core_t *core, uint lock_num);
  * By default this returns the calling core number, but may be overridden (e.g. to return an RTOS task id)
  */
 #define lock_get_caller_owner_id() ((lock_owner_id_t)get_core_num())
+#ifndef lock_is_owner_id_valid
+#define lock_is_owner_id_valid(id) ((id)>=0)
+#endif
+#endif
+
+#ifndef lock_is_owner_id_valid
+#define lock_is_owner_id_valid(id) ((id) != LOCK_INVALID_OWNER_ID)
 #endif
 
 #ifndef lock_internal_spin_unlock_with_wait
diff --git a/src/common/pico_sync/include/pico/mutex.h b/src/common/pico_sync/include/pico/mutex.h
index 22dd19d8b..e834dc513 100644
--- a/src/common/pico_sync/include/pico/mutex.h
+++ b/src/common/pico_sync/include/pico/mutex.h
@@ -19,25 +19,51 @@ extern "C" {
  * \brief Mutex API for non IRQ mutual exclusion between cores
  *
  * Mutexes are application level locks usually used protecting data structures that might be used by
- * multiple cores. Unlike critical sections, the mutex protected code is not necessarily
- * required/expected to complete quickly, as no other sytemwide locks are held on account of a locked mutex.
+ * multiple threads of execution. Unlike critical sections, the mutex protected code is not necessarily
+ * required/expected to complete quickly, as no other sytem wide locks are held on account of an acquired mutex.
  *
- * Because they are not re-entrant on the same core, blocking on a mutex should never be done in an IRQ
- * handler. It is valid to call \ref mutex_try_enter from within an IRQ handler, if the operation
- * that would be conducted under lock can be skipped if the mutex is locked (at least by the same core).
+ * When acquired, the mutex has an owner (see \ref lock_get_caller_owner_id) which with the plain SDK is just
+ * the acquiring core, but in an RTOS it could be a task, or an IRQ handler context.
+ *
+ * Two variants of mutex are provided; \ref mutex_t (and associated mutex_ functions) is a regular mutex that cannot
+ * be acquired recursively by the same owner (a deadlock will occur if you try). \ref recursive_mutex_t
+ * (and associated recursive_mutex_ functions) is a recursive mutex that can be recursively obtained by
+ * the same caller, at the expense of some more overhead when acquiring and releasing.
+ *
+ * It is generally a bad idea to call blocking mutex_ or recursive_mutex_ functions from within an IRQ handler.
+ * It is valid to call \ref mutex_try_enter or \ref recursive_mutex_try_enter from within an IRQ handler, if the operation
+ * that would be conducted under lock can be skipped if the mutex is locked (at least by the same owner).
+ *
+ * NOTE: For backwards compatibility with version 1.2.0 of the SDK, if the define
+ * PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY is set to 1, then the the regular mutex_ functions
+ * may also be used for recursive mutexes. This flag will be removed in a future version of the SDK.
  *
  * See \ref critical_section.h for protecting access between multiple cores AND IRQ handlers
  */
+
+/*! \brief recursive mutex instance
+ * \ingroup mutex
+ */
+typedef struct __packed_aligned  {
+    lock_core_t core;
+    lock_owner_id_t owner;      //! owner id LOCK_INVALID_OWNER_ID for unowned
+    uint8_t enter_count;        //! ownership count
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+    bool recursive;
+#endif
+} recursive_mutex_t;
+
+/*! \brief regular (non recursive) mutex instance
+ * \ingroup mutex
+ */
+#if !PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
 typedef struct __packed_aligned mutex {
     lock_core_t core;
     lock_owner_id_t owner;      //! owner id LOCK_INVALID_OWNER_ID for unowned
-    uint8_t recursion_state;    //! 0 means non recursive (owner or unowned)
-                                //! 1 is a maxed out recursive lock
-                                //! 2-254 is an owned lock
-                                //! 255 is an un-owned lock
 } mutex_t;
-
-#define MAX_RECURSION_STATE ((uint8_t)255)
+#else
+typedef recursive_mutex_t mutex_t; // they are one and the same when backwards compatible with SDK1.2.0
+#endif
 
 /*! \brief  Initialise a mutex structure
  *  \ingroup mutex
@@ -51,74 +77,140 @@ void mutex_init(mutex_t *mtx);
  *
  * A recursive mutex may be entered in a nested fashion by the same owner
  *
- * \param mtx Pointer to mutex structure
+ * \param mtx Pointer to recursive mutex structure
  */
-void recursive_mutex_init(mutex_t *mtx);
+void recursive_mutex_init(recursive_mutex_t *mtx);
 
 /*! \brief  Take ownership of a mutex
  *  \ingroup mutex
  *
- * This function will block until the calling core can claim ownership of the mutex.
- * On return the caller core owns the mutex
+ * This function will block until the caller can be granted ownership of the mutex.
+ * On return the caller owns the mutex
  *
  * \param mtx Pointer to mutex structure
  */
 void mutex_enter_blocking(mutex_t *mtx);
 
+/*! \brief  Take ownership of a recursive mutex
+ *  \ingroup mutex
+ *
+ * This function will block until the caller can be granted ownership of the mutex.
+ * On return the caller owns the mutex
+ *
+ * \param mtx Pointer to recursive mutex structure
+ */
+void recursive_mutex_enter_blocking(recursive_mutex_t *mtx);
+
 /*! \brief Attempt to take ownership of a mutex
  *  \ingroup mutex
  *
- * If the mutex wasn't owned, this will claim the mutex and return true.
+ * If the mutex wasn't owned, this will claim the mutex for the caller and return true.
  * Otherwise (if the mutex was already owned) this will return false and the
- * calling core will *NOT* own the mutex.
+ * caller will NOT own the mutex.
  *
  * \param mtx Pointer to mutex structure
- * \param owner_out If mutex was already owned, and this pointer is non-zero, it will be filled in with the core number of the current owner of the mutex
+ * \param owner_out If mutex was already owned, and this pointer is non-zero, it will be filled in with the owner id of the current owner of the mutex
+ * \return true if mutex now owned, false otherwise
  */
 bool mutex_try_enter(mutex_t *mtx, uint32_t *owner_out);
 
+/*! \brief Attempt to take ownership of a recursive mutex
+ *  \ingroup mutex
+ *
+ * If the mutex wasn't owned or was owned by the caller, this will claim the mutex and return true.
+ * Otherwise (if the mutex was already owned by another owner) this will return false and the
+ * caller will NOT own the mutex.
+ *
+ * \param mtx Pointer to recursive mutex structure
+ * \param owner_out If mutex was already owned by another owner, and this pointer is non-zero,
+ *                  it will be filled in with the owner id of the current owner of the mutex
+ * \return true if the recursive mutex (now) owned, false otherwise
+ */
+bool recursive_mutex_try_enter(recursive_mutex_t *mtx, uint32_t *owner_out);
+
 /*! \brief Wait for mutex with timeout
  *  \ingroup mutex
  *
- * Wait for up to the specific time to take ownership of the mutex. If the calling
- * core can take ownership of the mutex before the timeout expires, then true will be returned
- * and the calling core will own the mutex, otherwise false will be returned and the calling
- * core will *NOT* own the mutex.
+ * Wait for up to the specific time to take ownership of the mutex. If the caller
+ * can be granted ownership of the mutex before the timeout expires, then true will be returned
+ * and the caller will own the mutex, otherwise false will be returned and the caller will NOT own the mutex.
  *
  * \param mtx Pointer to mutex structure
  * \param timeout_ms The timeout in milliseconds.
- * \return true if mutex now owned, false if timeout occurred before mutex became available
+ * \return true if mutex now owned, false if timeout occurred before ownership could be granted
  */
 bool mutex_enter_timeout_ms(mutex_t *mtx, uint32_t timeout_ms);
 
+/*! \brief Wait for recursive mutex with timeout
+ *  \ingroup mutex
+ *
+ * Wait for up to the specific time to take ownership of the recursive mutex. If the caller
+ * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires,
+ * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller
+ * will NOT own the mutex.
+ *
+ * \param mtx Pointer to recursive mutex structure
+ * \param timeout_ms The timeout in milliseconds.
+ * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted
+ */
+bool recursive_mutex_enter_timeout_ms(recursive_mutex_t *mtx, uint32_t timeout_ms);
+
 /*! \brief Wait for mutex with timeout
  *  \ingroup mutex
  *
- * Wait for up to the specific time to take ownership of the mutex. If the calling
- * core can take ownership of the mutex before the timeout expires, then true will be returned
- * and the calling core will own the mutex, otherwise false will be returned and the calling
- * core will *NOT* own the mutex.
+ * Wait for up to the specific time to take ownership of the mutex. If the caller
+ * can be granted ownership of the mutex before the timeout expires, then true will be returned
+ * and the caller will own the mutex, otherwise false will be returned and the caller
+ * will NOT own the mutex.
  *
  * \param mtx Pointer to mutex structure
  * \param timeout_us The timeout in microseconds.
- * \return true if mutex now owned, false if timeout occurred before mutex became available
+ * \return true if mutex now owned, false if timeout occurred before ownership could be granted
  */
 bool mutex_enter_timeout_us(mutex_t *mtx, uint32_t timeout_us);
 
+/*! \brief Wait for recursive mutex with timeout
+ *  \ingroup mutex
+ *
+ * Wait for up to the specific time to take ownership of the recursive mutex. If the caller
+ * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires,
+ * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller
+ * will NOT own the mutex.
+ *
+ * \param mtx Pointer to mutex structure
+ * \param timeout_us The timeout in microseconds.
+ * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted
+ */
+bool recursive_mutex_enter_timeout_us(recursive_mutex_t *mtx, uint32_t timeout_us);
+
 /*! \brief Wait for mutex until a specific time
  *  \ingroup mutex
  *
- * Wait until the specific time to take ownership of the mutex. If the calling
- * core can take ownership of the mutex before the timeout expires, then true will be returned
- * and the calling core will own the mutex, otherwise false will be returned and the calling
- * core will *NOT* own the mutex.
+ * Wait until the specific time to take ownership of the mutex. If the caller
+ * can be granted ownership of the mutex before the timeout expires, then true will be returned
+ * and the caller will own the mutex, otherwise false will be returned and the caller
+ * will NOT own the mutex.
  *
  * \param mtx Pointer to mutex structure
- * \param until The time after which to return if the core cannot take ownership of the mutex
- * \return true if mutex now owned, false if timeout occurred before mutex became available
+ * \param until The time after which to return if the caller cannot be granted ownership of the mutex
+ * \return true if mutex now owned, false if timeout occurred before ownership could be granted
  */
 bool mutex_enter_block_until(mutex_t *mtx, absolute_time_t until);
 
+/*! \brief Wait for mutex until a specific time
+ *  \ingroup mutex
+ *
+ * Wait until the specific time to take ownership of the mutex. If the caller
+ * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires,
+ * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller
+ * will NOT own the mutex.
+ *
+ * \param mtx Pointer to recursive mutex structure
+ * \param until The time after which to return if the caller cannot be granted ownership of the mutex
+ * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted
+ */
+bool recursive_mutex_enter_block_until(recursive_mutex_t *mtx, absolute_time_t until);
+
 /*! \brief  Release ownership of a mutex
  *  \ingroup mutex
  *
@@ -126,13 +218,30 @@ bool mutex_enter_block_until(mutex_t *mtx, absolute_time_t until);
  */
 void mutex_exit(mutex_t *mtx);
 
-/*! \brief Test for mutex initialised state
+/*! \brief  Release ownership of a recursive mutex
+ *  \ingroup mutex
+ *
+ * \param mtx Pointer to recursive mutex structure
+ */
+void recursive_mutex_exit(recursive_mutex_t *mtx);
+
+/*! \brief Test for mutex initialized state
  *  \ingroup mutex
  *
  * \param mtx Pointer to mutex structure
- * \return true if the mutex is initialised, false otherwise
+ * \return true if the mutex is initialized, false otherwise
  */
-static inline bool mutex_is_initialzed(mutex_t *mtx) {
+static inline bool mutex_is_initialized(mutex_t *mtx) {
+    return mtx->core.spin_lock != 0;
+}
+
+/*! \brief Test for recursive mutex initialized state
+ *  \ingroup mutex
+ *
+ * \param mtx Pointer to recursive mutex structure
+ * \return true if the recursive mutex is initialized, false otherwise
+ */
+static inline bool recursive_mutex_is_initialized(recursive_mutex_t *mtx) {
     return mtx->core.spin_lock != 0;
 }
 
@@ -165,22 +274,22 @@ static inline bool mutex_is_initialzed(mutex_t *mtx) {
  * A recursive mutex defined as follows:
  *
  * ```c
- * auto_init_recursive_mutex(my_mutex);
+ * auto_init_recursive_mutex(my_recursive_mutex);
  * ```
  *
  * Is equivalent to doing
  *
  * ```c
- * static mutex_t my_mutex;
+ * static recursive_mutex_t my_recursive_mutex;
  *
  * void my_init_function() {
- *    recursive_mutex_init(&my_mutex);
+ *    recursive_mutex_init(&my_recursive_mutex);
  * }
  * ```
  *
  * But the initialization of the mutex is performed automatically during runtime initialization
  */
-#define auto_init_recursive_mutex(name) static __attribute__((section(".mutex_array"))) mutex_t name = { .recursion_state = MAX_RECURSION_STATE }
+#define auto_init_recursive_mutex(name) static __attribute__((section(".mutex_array"))) recursive_mutex_t name = { .core.spin_lock = (spin_lock_t *)1 /* marker for runtime_init */ }
 
 #ifdef __cplusplus
 }
diff --git a/src/common/pico_sync/mutex.c b/src/common/pico_sync/mutex.c
index 45ede4dc8..3ea81c752 100644
--- a/src/common/pico_sync/mutex.c
+++ b/src/common/pico_sync/mutex.c
@@ -7,53 +7,87 @@
 #include "pico/mutex.h"
 #include "pico/time.h"
 
-static void mutex_init_internal(mutex_t *mtx, uint8_t recursion_state) {
+void mutex_init(mutex_t *mtx) {
     lock_init(&mtx->core, next_striped_spin_lock_num());
     mtx->owner = LOCK_INVALID_OWNER_ID;
-    mtx->recursion_state = recursion_state;
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+    mtx->recursive = false;
+#endif
     __mem_fence_release();
 }
 
-void mutex_init(mutex_t *mtx) {
-    mutex_init_internal(mtx, 0);
+void recursive_mutex_init(recursive_mutex_t *mtx) {
+    lock_init(&mtx->core, next_striped_spin_lock_num());
+    mtx->owner = LOCK_INVALID_OWNER_ID;
+    mtx->enter_count = 0;
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+    mtx->recursive = true;
+#endif
+    __mem_fence_release();
 }
 
-void recursive_mutex_init(mutex_t *mtx) {
-    mutex_init_internal(mtx, MAX_RECURSION_STATE);
+void __time_critical_func(mutex_enter_blocking)(mutex_t *mtx) {
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+    if (mtx->recursive) {
+        recursive_mutex_enter_blocking(mtx);
+        return;
+    }
+#endif
+    lock_owner_id_t caller = lock_get_caller_owner_id();
+    do {
+        uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+        if (!lock_is_owner_id_valid(mtx->owner)) {
+            mtx->owner = caller;
+            spin_unlock(mtx->core.spin_lock, save);
+            break;
+        }
+        lock_internal_spin_unlock_with_wait(&mtx->core, save);
+    } while (true);
 }
 
-void __time_critical_func(mutex_enter_blocking)(mutex_t *mtx) {
-    assert(mtx->core.spin_lock);
+void __time_critical_func(recursive_mutex_enter_blocking)(recursive_mutex_t *mtx) {
+    lock_owner_id_t caller = lock_get_caller_owner_id();
     do {
         uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
-        lock_owner_id_t caller = lock_get_caller_owner_id();
-        if (mtx->owner == LOCK_INVALID_OWNER_ID) {
+        if (mtx->owner == caller || !lock_is_owner_id_valid(mtx->owner)) {
             mtx->owner = caller;
-            if (mtx->recursion_state) {
-                assert(mtx->recursion_state == MAX_RECURSION_STATE);
-                mtx->recursion_state--;
-            }
-        } else if (mtx->owner == caller && mtx->recursion_state > 1) {
-            mtx->recursion_state--;
+            uint __unused total = ++mtx->enter_count;
+            spin_unlock(mtx->core.spin_lock, save);
+            assert(total); // check for overflow
+            return;
         } else {
             lock_internal_spin_unlock_with_wait(&mtx->core, save);
-            // spin lock already unlocked, so loop again
-            continue;
         }
-        spin_unlock(mtx->core.spin_lock, save);
-        break;
     } while (true);
 }
 
 bool __time_critical_func(mutex_try_enter)(mutex_t *mtx, uint32_t *owner_out) {
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+    if (mtx->recursive) {
+        return recursive_mutex_try_enter(mtx, owner_out);
+    }
+#endif
     bool entered;
     uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
-    lock_owner_id_t caller = lock_get_caller_owner_id();
-    if (mtx->owner == LOCK_INVALID_OWNER_ID) {
+    if (!lock_is_owner_id_valid(mtx->owner)) {
         mtx->owner = lock_get_caller_owner_id();
         entered = true;
-    } else if (mtx->owner == caller && mtx->recursion_state > 1) {
-        mtx->recursion_state--;
+    } else {
+        if (owner_out) *owner_out = (uint32_t) mtx->owner;
+        entered = false;
+    }
+    spin_unlock(mtx->core.spin_lock, save);
+    return entered;
+}
+
+bool __time_critical_func(recursive_mutex_try_enter)(recursive_mutex_t *mtx, uint32_t *owner_out) {
+    bool entered;
+    lock_owner_id_t caller = lock_get_caller_owner_id();
+    uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+    if (!lock_is_owner_id_valid(mtx->owner) || mtx->owner == caller) {
+        mtx->owner = caller;
+        uint __unused total = ++mtx->enter_count;
+        assert(total); // check for overflow
         entered = true;
     } else {
         if (owner_out) *owner_out = (uint32_t) mtx->owner;
@@ -67,47 +101,84 @@ bool __time_critical_func(mutex_enter_timeout_ms)(mutex_t *mtx, uint32_t timeout
     return mutex_enter_block_until(mtx, make_timeout_time_ms(timeout_ms));
 }
 
+bool __time_critical_func(recursive_mutex_enter_timeout_ms)(recursive_mutex_t *mtx, uint32_t timeout_ms) {
+    return recursive_mutex_enter_block_until(mtx, make_timeout_time_ms(timeout_ms));
+}
+
 bool __time_critical_func(mutex_enter_timeout_us)(mutex_t *mtx, uint32_t timeout_us) {
     return mutex_enter_block_until(mtx, make_timeout_time_us(timeout_us));
 }
 
+bool __time_critical_func(recursive_mutex_enter_timeout_us)(recursive_mutex_t *mtx, uint32_t timeout_us) {
+    return recursive_mutex_enter_block_until(mtx, make_timeout_time_us(timeout_us));
+}
+
 bool __time_critical_func(mutex_enter_block_until)(mutex_t *mtx, absolute_time_t until) {
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+    if (mtx->recursive) {
+        return recursive_mutex_enter_block_until(mtx, until);
+    }
+#endif
     assert(mtx->core.spin_lock);
+    lock_owner_id_t caller = lock_get_caller_owner_id();
     do {
         uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
-        lock_owner_id_t caller = lock_get_caller_owner_id();
-        if (mtx->owner == LOCK_INVALID_OWNER_ID) {
+        if (!lock_is_owner_id_valid(mtx->owner)) {
             mtx->owner = caller;
-        } else if (mtx->owner == caller && mtx->recursion_state > 1) {
-            mtx->recursion_state--;
+            spin_unlock(mtx->core.spin_lock, save);
+            return true;
         } else {
             if (lock_internal_spin_unlock_with_best_effort_wait_or_timeout(&mtx->core, save, until)) {
                 // timed out
                 return false;
-            } else {
-                // not timed out; spin lock already unlocked, so loop again
-                continue;
             }
+            // not timed out; spin lock already unlocked, so loop again
+        }
+    } while (true);
+}
+
+bool __time_critical_func(recursive_mutex_enter_block_until)(recursive_mutex_t *mtx, absolute_time_t until) {
+    assert(mtx->core.spin_lock);
+    lock_owner_id_t caller = lock_get_caller_owner_id();
+    do {
+        uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+        if (!lock_is_owner_id_valid(mtx->owner) || mtx->owner == caller) {
+            mtx->owner = caller;
+            uint __unused total = ++mtx->enter_count;
+            spin_unlock(mtx->core.spin_lock, save);
+            assert(total); // check for overflow
+            return true;
+        } else {
+            if (lock_internal_spin_unlock_with_best_effort_wait_or_timeout(&mtx->core, save, until)) {
+                // timed out
+                return false;
+            }
+            // not timed out; spin lock already unlocked, so loop again
         }
-        spin_unlock(mtx->core.spin_lock, save);
-        return true;
     } while (true);
 }
 
 void __time_critical_func(mutex_exit)(mutex_t *mtx) {
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+    if (mtx->recursive) {
+        recursive_mutex_exit(mtx);
+        return;
+    }
+#endif
     uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
-    assert(mtx->owner != LOCK_INVALID_OWNER_ID);
-    if (!mtx->recursion_state) {
+    assert(lock_is_owner_id_valid(mtx->owner));
+    mtx->owner = LOCK_INVALID_OWNER_ID;
+    lock_internal_spin_unlock_with_notify(&mtx->core, save);
+}
+
+void __time_critical_func(recursive_mutex_exit)(recursive_mutex_t *mtx) {
+    uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+    assert(lock_is_owner_id_valid(mtx->owner));
+    assert(mtx->enter_count);
+    if (!--mtx->enter_count) {
         mtx->owner = LOCK_INVALID_OWNER_ID;
         lock_internal_spin_unlock_with_notify(&mtx->core, save);
     } else {
-        mtx->recursion_state++;
-        assert(mtx->recursion_state);
-        if (mtx->recursion_state == MAX_RECURSION_STATE) {
-            mtx->owner = LOCK_INVALID_OWNER_ID;
-            lock_internal_spin_unlock_with_notify(&mtx->core, save);
-        } else {
-            spin_unlock(mtx->core.spin_lock, save);
-        }
+        spin_unlock(mtx->core.spin_lock, save);
     }
 }
\ No newline at end of file
diff --git a/src/common/pico_time/include/pico/time.h b/src/common/pico_time/include/pico/time.h
index 1c347322e..c00b7a82c 100644
--- a/src/common/pico_time/include/pico/time.h
+++ b/src/common/pico_time/include/pico/time.h
@@ -416,9 +416,12 @@ void alarm_pool_destroy(alarm_pool_t *pool);
  * @param time the timestamp when (after which) the callback should fire
  * @param callback the callback function
  * @param user_data user data to pass to the callback function
- * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call
- * @return >0 the alarm id
- * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past)
+ * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set,
+ *                     then the callback should be called during (by) this function instead 
+ * @return >0 the alarm id for an active (at the time of return) alarm
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ *           The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ *           or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
  * @return -1 if there were no alarm slots available
  */
 alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback, void *user_data, bool fire_if_past);
@@ -438,9 +441,12 @@ alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, ala
  * @param us the delay (from now) in microseconds when (after which) the callback should fire
  * @param callback the callback function
  * @param user_data user data to pass to the callback function
- * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call
+ * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set,
+ *                     then the callback should be called during (by) this function instead 
  * @return >0 the alarm id
- * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past)
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ *           The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ *           or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
  * @return -1 if there were no alarm slots available
  */
 static inline alarm_id_t alarm_pool_add_alarm_in_us(alarm_pool_t *pool, uint64_t us, alarm_callback_t callback, void *user_data, bool fire_if_past) {
@@ -462,9 +468,12 @@ static inline alarm_id_t alarm_pool_add_alarm_in_us(alarm_pool_t *pool, uint64_t
  * @param ms the delay (from now) in milliseconds when (after which) the callback should fire
  * @param callback the callback function
  * @param user_data user data to pass to the callback function
- * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call
+ * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set,
+ *                     then the callback should be called during (by) this function instead 
  * @return >0 the alarm id
- * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past)
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ *           The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ *           or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
  * @return -1 if there were no alarm slots available
  */
 static inline alarm_id_t alarm_pool_add_alarm_in_ms(alarm_pool_t *pool, uint32_t ms, alarm_callback_t callback, void *user_data, bool fire_if_past) {
@@ -496,9 +505,12 @@ bool alarm_pool_cancel_alarm(alarm_pool_t *pool, alarm_id_t alarm_id);
  * @param time the timestamp when (after which) the callback should fire
  * @param callback the callback function
  * @param user_data user data to pass to the callback function
- * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call
+ * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set,
+ *                     then the callback should be called during (by) this function instead 
  * @return >0 the alarm id
- * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past)
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ *           The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ *           or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
  * @return -1 if there were no alarm slots available
  */
 static inline alarm_id_t add_alarm_at(absolute_time_t time, alarm_callback_t callback, void *user_data, bool fire_if_past) {
@@ -519,9 +531,12 @@ static inline alarm_id_t add_alarm_at(absolute_time_t time, alarm_callback_t cal
  * @param us the delay (from now) in microseconds when (after which) the callback should fire
  * @param callback the callback function
  * @param user_data user data to pass to the callback function
- * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call
+ * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set,
+ *                     then the callback should be called during (by) this function instead 
  * @return >0 the alarm id
- * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past)
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ *           The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ *           or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
  * @return -1 if there were no alarm slots available
  */
 static inline alarm_id_t add_alarm_in_us(uint64_t us, alarm_callback_t callback, void *user_data, bool fire_if_past) {
@@ -542,9 +557,12 @@ static inline alarm_id_t add_alarm_in_us(uint64_t us, alarm_callback_t callback,
  * @param ms the delay (from now) in milliseconds when (after which) the callback should fire
  * @param callback the callback function
  * @param user_data user data to pass to the callback function
- * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call
+ * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set,
+ *                     then the callback should be called during (by) this function instead 
  * @return >0 the alarm id
- * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past)
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ *           The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ *           or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
  * @return -1 if there were no alarm slots available
  */
 static inline alarm_id_t add_alarm_in_ms(uint32_t ms, alarm_callback_t callback, void *user_data, bool fire_if_past) {
diff --git a/src/common/pico_time/time.c b/src/common/pico_time/time.c
index f965ab89d..3a585f652 100644
--- a/src/common/pico_time/time.c
+++ b/src/common/pico_time/time.c
@@ -219,18 +219,26 @@ alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, ala
     do {
         uint8_t id_high = 0;
         uint32_t save = spin_lock_blocking(pool->lock);
+
         pheap_node_id_t id = add_alarm_under_lock(pool, time, callback, user_data, 0, false, &missed);
         if (id) id_high = *get_entry_id_high(pool, id);
 
         spin_unlock(pool->lock, save);
 
         if (!id) {
+            // no space in pheap to allocate an alarm
             return -1;
         }
 
+        // note that if missed was true, then the id was never added to the pheap (because we
+        // passed false for create_if_past arg above)
         public_id = missed ? 0 : make_public_id(id_high, id);
         if (missed && fire_if_past) {
+            // ... so if fire_if_past == true we call the callback
             int64_t repeat = callback(public_id, user_data);
+            // if not repeated we have no id to return so set public_id to 0,
+            // otherwise we need to repeat, but will assign a new id next time
+            // todo arguably this does mean that the id passed to the first callback may differ from subsequent calls
             if (!repeat) {
                 public_id = 0;
                 break;
@@ -240,6 +248,10 @@ alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, ala
                 time = delayed_by_us(get_absolute_time(), (uint64_t)repeat);
             }
         } else {
+            // either:
+            // a) missed == false && public_id is > 0
+            // b) missed == true && fire_if_past == false && public_id = 0
+            // but we are done in either case
             break;
         }
     } while (true);
@@ -279,7 +291,7 @@ static void alarm_pool_dump_key(pheap_node_id_t id, void *user_data) {
 #if PICO_ON_DEVICE
     printf("%lld (hi %02x)", to_us_since_boot(get_entry(pool, id)->target), *get_entry_id_high(pool, id));
 #else
-    printf(PRIu64, to_us_since_boot(get_entry(pool, id)->target));
+    printf("%"PRIu64, to_us_since_boot(get_entry(pool, id)->target));
 #endif
 }
 
@@ -302,7 +314,9 @@ bool alarm_pool_add_repeating_timer_us(alarm_pool_t *pool, int64_t delay_us, rep
     out->user_data = user_data;
     out->alarm_id = alarm_pool_add_alarm_at(pool, make_timeout_time_us((uint64_t)(delay_us >= 0 ? delay_us : -delay_us)),
                                             repeating_timer_callback, out, true);
-    return out->alarm_id > 0;
+    // note that if out->alarm_id is 0, then the callback was called during the above call (fire_if_past == true)
+    // and then the callback removed itself.
+    return out->alarm_id >= 0;
 }
 
 bool cancel_repeating_timer(repeating_timer_t *timer) {
diff --git a/src/common/pico_usb_reset_interface/CMakeLists.txt b/src/common/pico_usb_reset_interface/CMakeLists.txt
new file mode 100644
index 000000000..369375c39
--- /dev/null
+++ b/src/common/pico_usb_reset_interface/CMakeLists.txt
@@ -0,0 +1,2 @@
+add_library(pico_usb_reset_interface_headers INTERFACE)
+target_include_directories(pico_usb_reset_interface_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
diff --git a/src/common/pico_usb_reset_interface/include/pico/usb_reset_interface.h b/src/common/pico_usb_reset_interface/include/pico/usb_reset_interface.h
new file mode 100644
index 000000000..153acf810
--- /dev/null
+++ b/src/common/pico_usb_reset_interface/include/pico/usb_reset_interface.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_USB_RESET_INTERFACE_H
+#define _PICO_USB_RESET_INTERFACE_H
+
+/** \file usb_reset_interface.h
+ *  \defgroup pico_usb_reset_interface pico_usb_reset_interface
+ *
+ * Definition for the reset interface that may be exposed by the pico_stdio_usb library
+ */
+
+// VENDOR sub-class for the reset interface
+#define RESET_INTERFACE_SUBCLASS 0x00
+// VENDOR protocol for the reset interface
+#define RESET_INTERFACE_PROTOCOL 0x01
+
+// CONTROL requests:
+
+// reset to BOOTSEL
+#define RESET_REQUEST_BOOTSEL 0x01
+// regular flash boot
+#define RESET_REQUEST_FLASH 0x02
+
+#endif
\ No newline at end of file
diff --git a/src/common/pico_util/include/pico/util/datetime.h b/src/common/pico_util/include/pico/util/datetime.h
index 61b5c7e92..bb328351a 100644
--- a/src/common/pico_util/include/pico/util/datetime.h
+++ b/src/common/pico_util/include/pico/util/datetime.h
@@ -9,6 +9,10 @@
 
 #include "pico.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /** \file datetime.h
  * \defgroup util_datetime datetime
  * \brief Date/Time formatting
@@ -24,4 +28,7 @@
  */
 void datetime_to_str(char *buf, uint buf_size, const datetime_t *t);
 
+#ifdef __cplusplus
+}
+#endif
 #endif
diff --git a/src/host/hardware_gpio/include/hardware/gpio.h b/src/host/hardware_gpio/include/hardware/gpio.h
index 223c472ab..b2b83a1ef 100644
--- a/src/host/hardware_gpio/include/hardware/gpio.h
+++ b/src/host/hardware_gpio/include/hardware/gpio.h
@@ -152,7 +152,9 @@ void gpio_set_dir_all_bits(uint32_t value);
 void gpio_set_dir(uint gpio, bool out);
 
 // debugging
+#ifndef PICO_DEBUG_PIN_BASE
 #define PICO_DEBUG_PIN_BASE 19u
+#endif
 
 // note these two macros may only be used once per compilation unit
 #define CU_REGISTER_DEBUG_PINS(p, ...)
diff --git a/src/host/hardware_timer/timer.c b/src/host/hardware_timer/timer.c
index 1bab84563..30f6a2070 100644
--- a/src/host/hardware_timer/timer.c
+++ b/src/host/hardware_timer/timer.c
@@ -65,12 +65,12 @@ void PICO_WEAK_FUNCTION_IMPL_NAME(busy_wait_until)(absolute_time_t target) {
     const int chunk = 1u<<30u;
     uint64_t target_us = to_us_since_boot(target);
     uint64_t time_us = time_us_64();
-    while (target_us - time_us >= chunk) {
+    while ((int64_t)(target_us - time_us) >= chunk) {
         busy_wait_us_32(chunk);
         time_us = time_us_64();
     }
-    if (target_us != time_us) {
-        busy_wait_us_32(target_us - chunk);
+    if (target_us > time_us) {
+        busy_wait_us_32(target_us - time_us);
     }
 #endif
 }
diff --git a/src/host/pico_platform/include/pico/platform.h b/src/host/pico_platform/include/pico/platform.h
index 499bdf648..27e5c0854 100644
--- a/src/host/pico_platform/include/pico/platform.h
+++ b/src/host/pico_platform/include/pico/platform.h
@@ -20,15 +20,21 @@
 extern "C" {
 #endif
 
-#define __not_in_flash(grup)
+#define __not_in_flash(group)
 #define __not_in_flash_func(func) func
 #define __no_inline_not_in_flash_func(func)
 #define __in_flash(group)
 #define __scratch_x(group)
 #define __scratch_y(group)
 
-#define __packed_aligned
+#ifndef _MSC_VER
+#define __packed __attribute__((packed))
+#define __packed_aligned __packed __attribute((aligned))
+#else
+// MSVC requires #pragma pack which isn't compatible with a single attribute style define
 #define __packed
+#define __packed_aligned
+#endif
 
 #define __time_critical_func(x) x
 #define __after_data(group)
diff --git a/src/host/pico_stdio/include/pico/stdio.h b/src/host/pico_stdio/include/pico/stdio.h
index 543185394..de0bde167 100644
--- a/src/host/pico_stdio/include/pico/stdio.h
+++ b/src/host/pico_stdio/include/pico/stdio.h
@@ -16,6 +16,9 @@ void stdio_uart_init();
 static inline void stdio_init_all() { stdio_uart_init(); }
 static inline void stdio_filter_driver(stdio_driver_t *driver) {}
 static inline void stdio_set_translate_crlf(stdio_driver_t *driver, bool enabled) {}
+static inline bool stdio_usb_connected(void) { return true; }
 int getchar_timeout_us(uint32_t timeout_us);
+#define puts_raw puts
+#define putchar_raw putchar
 
 #endif
diff --git a/src/rp2040/hardware_regs/include/hardware/platform_defs.h b/src/rp2040/hardware_regs/include/hardware/platform_defs.h
index 437594c90..08c715944 100644
--- a/src/rp2040/hardware_regs/include/hardware/platform_defs.h
+++ b/src/rp2040/hardware_regs/include/hardware/platform_defs.h
@@ -7,7 +7,7 @@
 #ifndef _HARDWARE_PLATFORM_DEFS_H
 #define _HARDWARE_PLATFORM_DEFS_H
 
-// This header is included from C and assembler - only define macros
+// This header is included from C and assembler - intended mostly for #defines; guard other stuff with #ifdef __ASSEMBLER__
 
 #ifndef _u
 #ifdef __ASSEMBLER__
@@ -19,6 +19,7 @@
 
 #define NUM_CORES _u(2)
 #define NUM_DMA_CHANNELS _u(12)
+#define NUM_DMA_TIMERS _u(4)
 #define NUM_IRQS _u(32)
 #define NUM_PIOS _u(2)
 #define NUM_PIO_STATE_MACHINES _u(4)
@@ -27,28 +28,17 @@
 #define NUM_UARTS _u(2)
 #define NUM_I2CS _u(2)
 #define NUM_SPIS _u(2)
-
+#define NUM_TIMERS _u(4)
 #define NUM_ADC_CHANNELS _u(5)
 
 #define NUM_BANK0_GPIOS _u(30)
+#define NUM_QSPI_GPIOS _u(6)
 
 #define PIO_INSTRUCTION_COUNT _u(32)
 
+// PICO_CONFIG: XOSC_MHZ, The crystal oscillator frequency in Mhz, type=int, default=12, advanced=true, group=hardware_base
+#ifndef XOSC_MHZ
 #define XOSC_MHZ _u(12)
-
-// PICO_CONFIG: PICO_STACK_SIZE, Stack Size, min=0x100, default=0x800, advanced=true, group=pico_standard_link
-#ifndef PICO_STACK_SIZE
-#define PICO_STACK_SIZE _u(0x800)
-#endif
-
-// PICO_CONFIG: PICO_HEAP_SIZE, Heap size to reserve, min=0x100, default=0x800, advanced=true, group=pico_standard_link
-#ifndef PICO_HEAP_SIZE
-#define PICO_HEAP_SIZE _u(0x800)
-#endif
-
-// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_runtime
-#ifndef PICO_NO_RAM_VECTOR_TABLE
-#define PICO_NO_RAM_VECTOR_TABLE 0
 #endif
 
 #endif
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/dma.h b/src/rp2040/hardware_regs/include/hardware/regs/dma.h
index 49938ba92..042c3c17c 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/dma.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/dma.h
@@ -294,7 +294,7 @@
 #define DMA_CH0_AL1_CTRL_RESET  "-"
 #define DMA_CH0_AL1_CTRL_MSB    _u(31)
 #define DMA_CH0_AL1_CTRL_LSB    _u(0)
-#define DMA_CH0_AL1_CTRL_ACCESS "RO"
+#define DMA_CH0_AL1_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH0_AL1_READ_ADDR
 // Description : Alias for channel 0 READ_ADDR register
@@ -303,7 +303,7 @@
 #define DMA_CH0_AL1_READ_ADDR_RESET  "-"
 #define DMA_CH0_AL1_READ_ADDR_MSB    _u(31)
 #define DMA_CH0_AL1_READ_ADDR_LSB    _u(0)
-#define DMA_CH0_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH0_AL1_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH0_AL1_WRITE_ADDR
 // Description : Alias for channel 0 WRITE_ADDR register
@@ -312,7 +312,7 @@
 #define DMA_CH0_AL1_WRITE_ADDR_RESET  "-"
 #define DMA_CH0_AL1_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH0_AL1_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH0_AL1_TRANS_COUNT_TRIG
 // Description : Alias for channel 0 TRANS_COUNT register
@@ -323,7 +323,7 @@
 #define DMA_CH0_AL1_TRANS_COUNT_TRIG_RESET  "-"
 #define DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
 #define DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
-#define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH0_AL2_CTRL
 // Description : Alias for channel 0 CTRL register
@@ -332,7 +332,7 @@
 #define DMA_CH0_AL2_CTRL_RESET  "-"
 #define DMA_CH0_AL2_CTRL_MSB    _u(31)
 #define DMA_CH0_AL2_CTRL_LSB    _u(0)
-#define DMA_CH0_AL2_CTRL_ACCESS "RO"
+#define DMA_CH0_AL2_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH0_AL2_TRANS_COUNT
 // Description : Alias for channel 0 TRANS_COUNT register
@@ -341,7 +341,7 @@
 #define DMA_CH0_AL2_TRANS_COUNT_RESET  "-"
 #define DMA_CH0_AL2_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH0_AL2_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH0_AL2_READ_ADDR
 // Description : Alias for channel 0 READ_ADDR register
@@ -350,7 +350,7 @@
 #define DMA_CH0_AL2_READ_ADDR_RESET  "-"
 #define DMA_CH0_AL2_READ_ADDR_MSB    _u(31)
 #define DMA_CH0_AL2_READ_ADDR_LSB    _u(0)
-#define DMA_CH0_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH0_AL2_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH0_AL2_WRITE_ADDR_TRIG
 // Description : Alias for channel 0 WRITE_ADDR register
@@ -361,7 +361,7 @@
 #define DMA_CH0_AL2_WRITE_ADDR_TRIG_RESET  "-"
 #define DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH0_AL3_CTRL
 // Description : Alias for channel 0 CTRL register
@@ -370,7 +370,7 @@
 #define DMA_CH0_AL3_CTRL_RESET  "-"
 #define DMA_CH0_AL3_CTRL_MSB    _u(31)
 #define DMA_CH0_AL3_CTRL_LSB    _u(0)
-#define DMA_CH0_AL3_CTRL_ACCESS "RO"
+#define DMA_CH0_AL3_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH0_AL3_WRITE_ADDR
 // Description : Alias for channel 0 WRITE_ADDR register
@@ -379,7 +379,7 @@
 #define DMA_CH0_AL3_WRITE_ADDR_RESET  "-"
 #define DMA_CH0_AL3_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH0_AL3_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH0_AL3_TRANS_COUNT
 // Description : Alias for channel 0 TRANS_COUNT register
@@ -388,7 +388,7 @@
 #define DMA_CH0_AL3_TRANS_COUNT_RESET  "-"
 #define DMA_CH0_AL3_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH0_AL3_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH0_AL3_READ_ADDR_TRIG
 // Description : Alias for channel 0 READ_ADDR register
@@ -399,7 +399,7 @@
 #define DMA_CH0_AL3_READ_ADDR_TRIG_RESET  "-"
 #define DMA_CH0_AL3_READ_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH0_AL3_READ_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH1_READ_ADDR
 // Description : DMA Channel 1 Read Address pointer
@@ -683,7 +683,7 @@
 #define DMA_CH1_AL1_CTRL_RESET  "-"
 #define DMA_CH1_AL1_CTRL_MSB    _u(31)
 #define DMA_CH1_AL1_CTRL_LSB    _u(0)
-#define DMA_CH1_AL1_CTRL_ACCESS "RO"
+#define DMA_CH1_AL1_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH1_AL1_READ_ADDR
 // Description : Alias for channel 1 READ_ADDR register
@@ -692,7 +692,7 @@
 #define DMA_CH1_AL1_READ_ADDR_RESET  "-"
 #define DMA_CH1_AL1_READ_ADDR_MSB    _u(31)
 #define DMA_CH1_AL1_READ_ADDR_LSB    _u(0)
-#define DMA_CH1_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH1_AL1_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH1_AL1_WRITE_ADDR
 // Description : Alias for channel 1 WRITE_ADDR register
@@ -701,7 +701,7 @@
 #define DMA_CH1_AL1_WRITE_ADDR_RESET  "-"
 #define DMA_CH1_AL1_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH1_AL1_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH1_AL1_TRANS_COUNT_TRIG
 // Description : Alias for channel 1 TRANS_COUNT register
@@ -712,7 +712,7 @@
 #define DMA_CH1_AL1_TRANS_COUNT_TRIG_RESET  "-"
 #define DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
 #define DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
-#define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH1_AL2_CTRL
 // Description : Alias for channel 1 CTRL register
@@ -721,7 +721,7 @@
 #define DMA_CH1_AL2_CTRL_RESET  "-"
 #define DMA_CH1_AL2_CTRL_MSB    _u(31)
 #define DMA_CH1_AL2_CTRL_LSB    _u(0)
-#define DMA_CH1_AL2_CTRL_ACCESS "RO"
+#define DMA_CH1_AL2_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH1_AL2_TRANS_COUNT
 // Description : Alias for channel 1 TRANS_COUNT register
@@ -730,7 +730,7 @@
 #define DMA_CH1_AL2_TRANS_COUNT_RESET  "-"
 #define DMA_CH1_AL2_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH1_AL2_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH1_AL2_READ_ADDR
 // Description : Alias for channel 1 READ_ADDR register
@@ -739,7 +739,7 @@
 #define DMA_CH1_AL2_READ_ADDR_RESET  "-"
 #define DMA_CH1_AL2_READ_ADDR_MSB    _u(31)
 #define DMA_CH1_AL2_READ_ADDR_LSB    _u(0)
-#define DMA_CH1_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH1_AL2_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH1_AL2_WRITE_ADDR_TRIG
 // Description : Alias for channel 1 WRITE_ADDR register
@@ -750,7 +750,7 @@
 #define DMA_CH1_AL2_WRITE_ADDR_TRIG_RESET  "-"
 #define DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH1_AL3_CTRL
 // Description : Alias for channel 1 CTRL register
@@ -759,7 +759,7 @@
 #define DMA_CH1_AL3_CTRL_RESET  "-"
 #define DMA_CH1_AL3_CTRL_MSB    _u(31)
 #define DMA_CH1_AL3_CTRL_LSB    _u(0)
-#define DMA_CH1_AL3_CTRL_ACCESS "RO"
+#define DMA_CH1_AL3_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH1_AL3_WRITE_ADDR
 // Description : Alias for channel 1 WRITE_ADDR register
@@ -768,7 +768,7 @@
 #define DMA_CH1_AL3_WRITE_ADDR_RESET  "-"
 #define DMA_CH1_AL3_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH1_AL3_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH1_AL3_TRANS_COUNT
 // Description : Alias for channel 1 TRANS_COUNT register
@@ -777,7 +777,7 @@
 #define DMA_CH1_AL3_TRANS_COUNT_RESET  "-"
 #define DMA_CH1_AL3_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH1_AL3_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH1_AL3_READ_ADDR_TRIG
 // Description : Alias for channel 1 READ_ADDR register
@@ -788,7 +788,7 @@
 #define DMA_CH1_AL3_READ_ADDR_TRIG_RESET  "-"
 #define DMA_CH1_AL3_READ_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH1_AL3_READ_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH2_READ_ADDR
 // Description : DMA Channel 2 Read Address pointer
@@ -1072,7 +1072,7 @@
 #define DMA_CH2_AL1_CTRL_RESET  "-"
 #define DMA_CH2_AL1_CTRL_MSB    _u(31)
 #define DMA_CH2_AL1_CTRL_LSB    _u(0)
-#define DMA_CH2_AL1_CTRL_ACCESS "RO"
+#define DMA_CH2_AL1_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH2_AL1_READ_ADDR
 // Description : Alias for channel 2 READ_ADDR register
@@ -1081,7 +1081,7 @@
 #define DMA_CH2_AL1_READ_ADDR_RESET  "-"
 #define DMA_CH2_AL1_READ_ADDR_MSB    _u(31)
 #define DMA_CH2_AL1_READ_ADDR_LSB    _u(0)
-#define DMA_CH2_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH2_AL1_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH2_AL1_WRITE_ADDR
 // Description : Alias for channel 2 WRITE_ADDR register
@@ -1090,7 +1090,7 @@
 #define DMA_CH2_AL1_WRITE_ADDR_RESET  "-"
 #define DMA_CH2_AL1_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH2_AL1_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH2_AL1_TRANS_COUNT_TRIG
 // Description : Alias for channel 2 TRANS_COUNT register
@@ -1101,7 +1101,7 @@
 #define DMA_CH2_AL1_TRANS_COUNT_TRIG_RESET  "-"
 #define DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
 #define DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
-#define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH2_AL2_CTRL
 // Description : Alias for channel 2 CTRL register
@@ -1110,7 +1110,7 @@
 #define DMA_CH2_AL2_CTRL_RESET  "-"
 #define DMA_CH2_AL2_CTRL_MSB    _u(31)
 #define DMA_CH2_AL2_CTRL_LSB    _u(0)
-#define DMA_CH2_AL2_CTRL_ACCESS "RO"
+#define DMA_CH2_AL2_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH2_AL2_TRANS_COUNT
 // Description : Alias for channel 2 TRANS_COUNT register
@@ -1119,7 +1119,7 @@
 #define DMA_CH2_AL2_TRANS_COUNT_RESET  "-"
 #define DMA_CH2_AL2_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH2_AL2_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH2_AL2_READ_ADDR
 // Description : Alias for channel 2 READ_ADDR register
@@ -1128,7 +1128,7 @@
 #define DMA_CH2_AL2_READ_ADDR_RESET  "-"
 #define DMA_CH2_AL2_READ_ADDR_MSB    _u(31)
 #define DMA_CH2_AL2_READ_ADDR_LSB    _u(0)
-#define DMA_CH2_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH2_AL2_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH2_AL2_WRITE_ADDR_TRIG
 // Description : Alias for channel 2 WRITE_ADDR register
@@ -1139,7 +1139,7 @@
 #define DMA_CH2_AL2_WRITE_ADDR_TRIG_RESET  "-"
 #define DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH2_AL3_CTRL
 // Description : Alias for channel 2 CTRL register
@@ -1148,7 +1148,7 @@
 #define DMA_CH2_AL3_CTRL_RESET  "-"
 #define DMA_CH2_AL3_CTRL_MSB    _u(31)
 #define DMA_CH2_AL3_CTRL_LSB    _u(0)
-#define DMA_CH2_AL3_CTRL_ACCESS "RO"
+#define DMA_CH2_AL3_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH2_AL3_WRITE_ADDR
 // Description : Alias for channel 2 WRITE_ADDR register
@@ -1157,7 +1157,7 @@
 #define DMA_CH2_AL3_WRITE_ADDR_RESET  "-"
 #define DMA_CH2_AL3_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH2_AL3_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH2_AL3_TRANS_COUNT
 // Description : Alias for channel 2 TRANS_COUNT register
@@ -1166,7 +1166,7 @@
 #define DMA_CH2_AL3_TRANS_COUNT_RESET  "-"
 #define DMA_CH2_AL3_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH2_AL3_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH2_AL3_READ_ADDR_TRIG
 // Description : Alias for channel 2 READ_ADDR register
@@ -1177,7 +1177,7 @@
 #define DMA_CH2_AL3_READ_ADDR_TRIG_RESET  "-"
 #define DMA_CH2_AL3_READ_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH2_AL3_READ_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH3_READ_ADDR
 // Description : DMA Channel 3 Read Address pointer
@@ -1461,7 +1461,7 @@
 #define DMA_CH3_AL1_CTRL_RESET  "-"
 #define DMA_CH3_AL1_CTRL_MSB    _u(31)
 #define DMA_CH3_AL1_CTRL_LSB    _u(0)
-#define DMA_CH3_AL1_CTRL_ACCESS "RO"
+#define DMA_CH3_AL1_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH3_AL1_READ_ADDR
 // Description : Alias for channel 3 READ_ADDR register
@@ -1470,7 +1470,7 @@
 #define DMA_CH3_AL1_READ_ADDR_RESET  "-"
 #define DMA_CH3_AL1_READ_ADDR_MSB    _u(31)
 #define DMA_CH3_AL1_READ_ADDR_LSB    _u(0)
-#define DMA_CH3_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH3_AL1_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH3_AL1_WRITE_ADDR
 // Description : Alias for channel 3 WRITE_ADDR register
@@ -1479,7 +1479,7 @@
 #define DMA_CH3_AL1_WRITE_ADDR_RESET  "-"
 #define DMA_CH3_AL1_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH3_AL1_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH3_AL1_TRANS_COUNT_TRIG
 // Description : Alias for channel 3 TRANS_COUNT register
@@ -1490,7 +1490,7 @@
 #define DMA_CH3_AL1_TRANS_COUNT_TRIG_RESET  "-"
 #define DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
 #define DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
-#define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH3_AL2_CTRL
 // Description : Alias for channel 3 CTRL register
@@ -1499,7 +1499,7 @@
 #define DMA_CH3_AL2_CTRL_RESET  "-"
 #define DMA_CH3_AL2_CTRL_MSB    _u(31)
 #define DMA_CH3_AL2_CTRL_LSB    _u(0)
-#define DMA_CH3_AL2_CTRL_ACCESS "RO"
+#define DMA_CH3_AL2_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH3_AL2_TRANS_COUNT
 // Description : Alias for channel 3 TRANS_COUNT register
@@ -1508,7 +1508,7 @@
 #define DMA_CH3_AL2_TRANS_COUNT_RESET  "-"
 #define DMA_CH3_AL2_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH3_AL2_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH3_AL2_READ_ADDR
 // Description : Alias for channel 3 READ_ADDR register
@@ -1517,7 +1517,7 @@
 #define DMA_CH3_AL2_READ_ADDR_RESET  "-"
 #define DMA_CH3_AL2_READ_ADDR_MSB    _u(31)
 #define DMA_CH3_AL2_READ_ADDR_LSB    _u(0)
-#define DMA_CH3_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH3_AL2_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH3_AL2_WRITE_ADDR_TRIG
 // Description : Alias for channel 3 WRITE_ADDR register
@@ -1528,7 +1528,7 @@
 #define DMA_CH3_AL2_WRITE_ADDR_TRIG_RESET  "-"
 #define DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH3_AL3_CTRL
 // Description : Alias for channel 3 CTRL register
@@ -1537,7 +1537,7 @@
 #define DMA_CH3_AL3_CTRL_RESET  "-"
 #define DMA_CH3_AL3_CTRL_MSB    _u(31)
 #define DMA_CH3_AL3_CTRL_LSB    _u(0)
-#define DMA_CH3_AL3_CTRL_ACCESS "RO"
+#define DMA_CH3_AL3_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH3_AL3_WRITE_ADDR
 // Description : Alias for channel 3 WRITE_ADDR register
@@ -1546,7 +1546,7 @@
 #define DMA_CH3_AL3_WRITE_ADDR_RESET  "-"
 #define DMA_CH3_AL3_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH3_AL3_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH3_AL3_TRANS_COUNT
 // Description : Alias for channel 3 TRANS_COUNT register
@@ -1555,7 +1555,7 @@
 #define DMA_CH3_AL3_TRANS_COUNT_RESET  "-"
 #define DMA_CH3_AL3_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH3_AL3_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH3_AL3_READ_ADDR_TRIG
 // Description : Alias for channel 3 READ_ADDR register
@@ -1566,7 +1566,7 @@
 #define DMA_CH3_AL3_READ_ADDR_TRIG_RESET  "-"
 #define DMA_CH3_AL3_READ_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH3_AL3_READ_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH4_READ_ADDR
 // Description : DMA Channel 4 Read Address pointer
@@ -1850,7 +1850,7 @@
 #define DMA_CH4_AL1_CTRL_RESET  "-"
 #define DMA_CH4_AL1_CTRL_MSB    _u(31)
 #define DMA_CH4_AL1_CTRL_LSB    _u(0)
-#define DMA_CH4_AL1_CTRL_ACCESS "RO"
+#define DMA_CH4_AL1_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH4_AL1_READ_ADDR
 // Description : Alias for channel 4 READ_ADDR register
@@ -1859,7 +1859,7 @@
 #define DMA_CH4_AL1_READ_ADDR_RESET  "-"
 #define DMA_CH4_AL1_READ_ADDR_MSB    _u(31)
 #define DMA_CH4_AL1_READ_ADDR_LSB    _u(0)
-#define DMA_CH4_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH4_AL1_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH4_AL1_WRITE_ADDR
 // Description : Alias for channel 4 WRITE_ADDR register
@@ -1868,7 +1868,7 @@
 #define DMA_CH4_AL1_WRITE_ADDR_RESET  "-"
 #define DMA_CH4_AL1_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH4_AL1_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH4_AL1_TRANS_COUNT_TRIG
 // Description : Alias for channel 4 TRANS_COUNT register
@@ -1879,7 +1879,7 @@
 #define DMA_CH4_AL1_TRANS_COUNT_TRIG_RESET  "-"
 #define DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
 #define DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
-#define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH4_AL2_CTRL
 // Description : Alias for channel 4 CTRL register
@@ -1888,7 +1888,7 @@
 #define DMA_CH4_AL2_CTRL_RESET  "-"
 #define DMA_CH4_AL2_CTRL_MSB    _u(31)
 #define DMA_CH4_AL2_CTRL_LSB    _u(0)
-#define DMA_CH4_AL2_CTRL_ACCESS "RO"
+#define DMA_CH4_AL2_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH4_AL2_TRANS_COUNT
 // Description : Alias for channel 4 TRANS_COUNT register
@@ -1897,7 +1897,7 @@
 #define DMA_CH4_AL2_TRANS_COUNT_RESET  "-"
 #define DMA_CH4_AL2_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH4_AL2_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH4_AL2_READ_ADDR
 // Description : Alias for channel 4 READ_ADDR register
@@ -1906,7 +1906,7 @@
 #define DMA_CH4_AL2_READ_ADDR_RESET  "-"
 #define DMA_CH4_AL2_READ_ADDR_MSB    _u(31)
 #define DMA_CH4_AL2_READ_ADDR_LSB    _u(0)
-#define DMA_CH4_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH4_AL2_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH4_AL2_WRITE_ADDR_TRIG
 // Description : Alias for channel 4 WRITE_ADDR register
@@ -1917,7 +1917,7 @@
 #define DMA_CH4_AL2_WRITE_ADDR_TRIG_RESET  "-"
 #define DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH4_AL3_CTRL
 // Description : Alias for channel 4 CTRL register
@@ -1926,7 +1926,7 @@
 #define DMA_CH4_AL3_CTRL_RESET  "-"
 #define DMA_CH4_AL3_CTRL_MSB    _u(31)
 #define DMA_CH4_AL3_CTRL_LSB    _u(0)
-#define DMA_CH4_AL3_CTRL_ACCESS "RO"
+#define DMA_CH4_AL3_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH4_AL3_WRITE_ADDR
 // Description : Alias for channel 4 WRITE_ADDR register
@@ -1935,7 +1935,7 @@
 #define DMA_CH4_AL3_WRITE_ADDR_RESET  "-"
 #define DMA_CH4_AL3_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH4_AL3_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH4_AL3_TRANS_COUNT
 // Description : Alias for channel 4 TRANS_COUNT register
@@ -1944,7 +1944,7 @@
 #define DMA_CH4_AL3_TRANS_COUNT_RESET  "-"
 #define DMA_CH4_AL3_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH4_AL3_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH4_AL3_READ_ADDR_TRIG
 // Description : Alias for channel 4 READ_ADDR register
@@ -1955,7 +1955,7 @@
 #define DMA_CH4_AL3_READ_ADDR_TRIG_RESET  "-"
 #define DMA_CH4_AL3_READ_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH4_AL3_READ_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH5_READ_ADDR
 // Description : DMA Channel 5 Read Address pointer
@@ -2239,7 +2239,7 @@
 #define DMA_CH5_AL1_CTRL_RESET  "-"
 #define DMA_CH5_AL1_CTRL_MSB    _u(31)
 #define DMA_CH5_AL1_CTRL_LSB    _u(0)
-#define DMA_CH5_AL1_CTRL_ACCESS "RO"
+#define DMA_CH5_AL1_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH5_AL1_READ_ADDR
 // Description : Alias for channel 5 READ_ADDR register
@@ -2248,7 +2248,7 @@
 #define DMA_CH5_AL1_READ_ADDR_RESET  "-"
 #define DMA_CH5_AL1_READ_ADDR_MSB    _u(31)
 #define DMA_CH5_AL1_READ_ADDR_LSB    _u(0)
-#define DMA_CH5_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH5_AL1_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH5_AL1_WRITE_ADDR
 // Description : Alias for channel 5 WRITE_ADDR register
@@ -2257,7 +2257,7 @@
 #define DMA_CH5_AL1_WRITE_ADDR_RESET  "-"
 #define DMA_CH5_AL1_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH5_AL1_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH5_AL1_TRANS_COUNT_TRIG
 // Description : Alias for channel 5 TRANS_COUNT register
@@ -2268,7 +2268,7 @@
 #define DMA_CH5_AL1_TRANS_COUNT_TRIG_RESET  "-"
 #define DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
 #define DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
-#define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH5_AL2_CTRL
 // Description : Alias for channel 5 CTRL register
@@ -2277,7 +2277,7 @@
 #define DMA_CH5_AL2_CTRL_RESET  "-"
 #define DMA_CH5_AL2_CTRL_MSB    _u(31)
 #define DMA_CH5_AL2_CTRL_LSB    _u(0)
-#define DMA_CH5_AL2_CTRL_ACCESS "RO"
+#define DMA_CH5_AL2_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH5_AL2_TRANS_COUNT
 // Description : Alias for channel 5 TRANS_COUNT register
@@ -2286,7 +2286,7 @@
 #define DMA_CH5_AL2_TRANS_COUNT_RESET  "-"
 #define DMA_CH5_AL2_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH5_AL2_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH5_AL2_READ_ADDR
 // Description : Alias for channel 5 READ_ADDR register
@@ -2295,7 +2295,7 @@
 #define DMA_CH5_AL2_READ_ADDR_RESET  "-"
 #define DMA_CH5_AL2_READ_ADDR_MSB    _u(31)
 #define DMA_CH5_AL2_READ_ADDR_LSB    _u(0)
-#define DMA_CH5_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH5_AL2_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH5_AL2_WRITE_ADDR_TRIG
 // Description : Alias for channel 5 WRITE_ADDR register
@@ -2306,7 +2306,7 @@
 #define DMA_CH5_AL2_WRITE_ADDR_TRIG_RESET  "-"
 #define DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH5_AL3_CTRL
 // Description : Alias for channel 5 CTRL register
@@ -2315,7 +2315,7 @@
 #define DMA_CH5_AL3_CTRL_RESET  "-"
 #define DMA_CH5_AL3_CTRL_MSB    _u(31)
 #define DMA_CH5_AL3_CTRL_LSB    _u(0)
-#define DMA_CH5_AL3_CTRL_ACCESS "RO"
+#define DMA_CH5_AL3_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH5_AL3_WRITE_ADDR
 // Description : Alias for channel 5 WRITE_ADDR register
@@ -2324,7 +2324,7 @@
 #define DMA_CH5_AL3_WRITE_ADDR_RESET  "-"
 #define DMA_CH5_AL3_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH5_AL3_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH5_AL3_TRANS_COUNT
 // Description : Alias for channel 5 TRANS_COUNT register
@@ -2333,7 +2333,7 @@
 #define DMA_CH5_AL3_TRANS_COUNT_RESET  "-"
 #define DMA_CH5_AL3_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH5_AL3_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH5_AL3_READ_ADDR_TRIG
 // Description : Alias for channel 5 READ_ADDR register
@@ -2344,7 +2344,7 @@
 #define DMA_CH5_AL3_READ_ADDR_TRIG_RESET  "-"
 #define DMA_CH5_AL3_READ_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH5_AL3_READ_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH6_READ_ADDR
 // Description : DMA Channel 6 Read Address pointer
@@ -2628,7 +2628,7 @@
 #define DMA_CH6_AL1_CTRL_RESET  "-"
 #define DMA_CH6_AL1_CTRL_MSB    _u(31)
 #define DMA_CH6_AL1_CTRL_LSB    _u(0)
-#define DMA_CH6_AL1_CTRL_ACCESS "RO"
+#define DMA_CH6_AL1_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH6_AL1_READ_ADDR
 // Description : Alias for channel 6 READ_ADDR register
@@ -2637,7 +2637,7 @@
 #define DMA_CH6_AL1_READ_ADDR_RESET  "-"
 #define DMA_CH6_AL1_READ_ADDR_MSB    _u(31)
 #define DMA_CH6_AL1_READ_ADDR_LSB    _u(0)
-#define DMA_CH6_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH6_AL1_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH6_AL1_WRITE_ADDR
 // Description : Alias for channel 6 WRITE_ADDR register
@@ -2646,7 +2646,7 @@
 #define DMA_CH6_AL1_WRITE_ADDR_RESET  "-"
 #define DMA_CH6_AL1_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH6_AL1_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH6_AL1_TRANS_COUNT_TRIG
 // Description : Alias for channel 6 TRANS_COUNT register
@@ -2657,7 +2657,7 @@
 #define DMA_CH6_AL1_TRANS_COUNT_TRIG_RESET  "-"
 #define DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
 #define DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
-#define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH6_AL2_CTRL
 // Description : Alias for channel 6 CTRL register
@@ -2666,7 +2666,7 @@
 #define DMA_CH6_AL2_CTRL_RESET  "-"
 #define DMA_CH6_AL2_CTRL_MSB    _u(31)
 #define DMA_CH6_AL2_CTRL_LSB    _u(0)
-#define DMA_CH6_AL2_CTRL_ACCESS "RO"
+#define DMA_CH6_AL2_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH6_AL2_TRANS_COUNT
 // Description : Alias for channel 6 TRANS_COUNT register
@@ -2675,7 +2675,7 @@
 #define DMA_CH6_AL2_TRANS_COUNT_RESET  "-"
 #define DMA_CH6_AL2_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH6_AL2_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH6_AL2_READ_ADDR
 // Description : Alias for channel 6 READ_ADDR register
@@ -2684,7 +2684,7 @@
 #define DMA_CH6_AL2_READ_ADDR_RESET  "-"
 #define DMA_CH6_AL2_READ_ADDR_MSB    _u(31)
 #define DMA_CH6_AL2_READ_ADDR_LSB    _u(0)
-#define DMA_CH6_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH6_AL2_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH6_AL2_WRITE_ADDR_TRIG
 // Description : Alias for channel 6 WRITE_ADDR register
@@ -2695,7 +2695,7 @@
 #define DMA_CH6_AL2_WRITE_ADDR_TRIG_RESET  "-"
 #define DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH6_AL3_CTRL
 // Description : Alias for channel 6 CTRL register
@@ -2704,7 +2704,7 @@
 #define DMA_CH6_AL3_CTRL_RESET  "-"
 #define DMA_CH6_AL3_CTRL_MSB    _u(31)
 #define DMA_CH6_AL3_CTRL_LSB    _u(0)
-#define DMA_CH6_AL3_CTRL_ACCESS "RO"
+#define DMA_CH6_AL3_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH6_AL3_WRITE_ADDR
 // Description : Alias for channel 6 WRITE_ADDR register
@@ -2713,7 +2713,7 @@
 #define DMA_CH6_AL3_WRITE_ADDR_RESET  "-"
 #define DMA_CH6_AL3_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH6_AL3_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH6_AL3_TRANS_COUNT
 // Description : Alias for channel 6 TRANS_COUNT register
@@ -2722,7 +2722,7 @@
 #define DMA_CH6_AL3_TRANS_COUNT_RESET  "-"
 #define DMA_CH6_AL3_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH6_AL3_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH6_AL3_READ_ADDR_TRIG
 // Description : Alias for channel 6 READ_ADDR register
@@ -2733,7 +2733,7 @@
 #define DMA_CH6_AL3_READ_ADDR_TRIG_RESET  "-"
 #define DMA_CH6_AL3_READ_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH6_AL3_READ_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH7_READ_ADDR
 // Description : DMA Channel 7 Read Address pointer
@@ -3017,7 +3017,7 @@
 #define DMA_CH7_AL1_CTRL_RESET  "-"
 #define DMA_CH7_AL1_CTRL_MSB    _u(31)
 #define DMA_CH7_AL1_CTRL_LSB    _u(0)
-#define DMA_CH7_AL1_CTRL_ACCESS "RO"
+#define DMA_CH7_AL1_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH7_AL1_READ_ADDR
 // Description : Alias for channel 7 READ_ADDR register
@@ -3026,7 +3026,7 @@
 #define DMA_CH7_AL1_READ_ADDR_RESET  "-"
 #define DMA_CH7_AL1_READ_ADDR_MSB    _u(31)
 #define DMA_CH7_AL1_READ_ADDR_LSB    _u(0)
-#define DMA_CH7_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH7_AL1_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH7_AL1_WRITE_ADDR
 // Description : Alias for channel 7 WRITE_ADDR register
@@ -3035,7 +3035,7 @@
 #define DMA_CH7_AL1_WRITE_ADDR_RESET  "-"
 #define DMA_CH7_AL1_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH7_AL1_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH7_AL1_TRANS_COUNT_TRIG
 // Description : Alias for channel 7 TRANS_COUNT register
@@ -3046,7 +3046,7 @@
 #define DMA_CH7_AL1_TRANS_COUNT_TRIG_RESET  "-"
 #define DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
 #define DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
-#define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH7_AL2_CTRL
 // Description : Alias for channel 7 CTRL register
@@ -3055,7 +3055,7 @@
 #define DMA_CH7_AL2_CTRL_RESET  "-"
 #define DMA_CH7_AL2_CTRL_MSB    _u(31)
 #define DMA_CH7_AL2_CTRL_LSB    _u(0)
-#define DMA_CH7_AL2_CTRL_ACCESS "RO"
+#define DMA_CH7_AL2_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH7_AL2_TRANS_COUNT
 // Description : Alias for channel 7 TRANS_COUNT register
@@ -3064,7 +3064,7 @@
 #define DMA_CH7_AL2_TRANS_COUNT_RESET  "-"
 #define DMA_CH7_AL2_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH7_AL2_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH7_AL2_READ_ADDR
 // Description : Alias for channel 7 READ_ADDR register
@@ -3073,7 +3073,7 @@
 #define DMA_CH7_AL2_READ_ADDR_RESET  "-"
 #define DMA_CH7_AL2_READ_ADDR_MSB    _u(31)
 #define DMA_CH7_AL2_READ_ADDR_LSB    _u(0)
-#define DMA_CH7_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH7_AL2_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH7_AL2_WRITE_ADDR_TRIG
 // Description : Alias for channel 7 WRITE_ADDR register
@@ -3084,7 +3084,7 @@
 #define DMA_CH7_AL2_WRITE_ADDR_TRIG_RESET  "-"
 #define DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH7_AL3_CTRL
 // Description : Alias for channel 7 CTRL register
@@ -3093,7 +3093,7 @@
 #define DMA_CH7_AL3_CTRL_RESET  "-"
 #define DMA_CH7_AL3_CTRL_MSB    _u(31)
 #define DMA_CH7_AL3_CTRL_LSB    _u(0)
-#define DMA_CH7_AL3_CTRL_ACCESS "RO"
+#define DMA_CH7_AL3_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH7_AL3_WRITE_ADDR
 // Description : Alias for channel 7 WRITE_ADDR register
@@ -3102,7 +3102,7 @@
 #define DMA_CH7_AL3_WRITE_ADDR_RESET  "-"
 #define DMA_CH7_AL3_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH7_AL3_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH7_AL3_TRANS_COUNT
 // Description : Alias for channel 7 TRANS_COUNT register
@@ -3111,7 +3111,7 @@
 #define DMA_CH7_AL3_TRANS_COUNT_RESET  "-"
 #define DMA_CH7_AL3_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH7_AL3_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH7_AL3_READ_ADDR_TRIG
 // Description : Alias for channel 7 READ_ADDR register
@@ -3122,7 +3122,7 @@
 #define DMA_CH7_AL3_READ_ADDR_TRIG_RESET  "-"
 #define DMA_CH7_AL3_READ_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH7_AL3_READ_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH8_READ_ADDR
 // Description : DMA Channel 8 Read Address pointer
@@ -3406,7 +3406,7 @@
 #define DMA_CH8_AL1_CTRL_RESET  "-"
 #define DMA_CH8_AL1_CTRL_MSB    _u(31)
 #define DMA_CH8_AL1_CTRL_LSB    _u(0)
-#define DMA_CH8_AL1_CTRL_ACCESS "RO"
+#define DMA_CH8_AL1_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH8_AL1_READ_ADDR
 // Description : Alias for channel 8 READ_ADDR register
@@ -3415,7 +3415,7 @@
 #define DMA_CH8_AL1_READ_ADDR_RESET  "-"
 #define DMA_CH8_AL1_READ_ADDR_MSB    _u(31)
 #define DMA_CH8_AL1_READ_ADDR_LSB    _u(0)
-#define DMA_CH8_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH8_AL1_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH8_AL1_WRITE_ADDR
 // Description : Alias for channel 8 WRITE_ADDR register
@@ -3424,7 +3424,7 @@
 #define DMA_CH8_AL1_WRITE_ADDR_RESET  "-"
 #define DMA_CH8_AL1_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH8_AL1_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH8_AL1_TRANS_COUNT_TRIG
 // Description : Alias for channel 8 TRANS_COUNT register
@@ -3435,7 +3435,7 @@
 #define DMA_CH8_AL1_TRANS_COUNT_TRIG_RESET  "-"
 #define DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
 #define DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
-#define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH8_AL2_CTRL
 // Description : Alias for channel 8 CTRL register
@@ -3444,7 +3444,7 @@
 #define DMA_CH8_AL2_CTRL_RESET  "-"
 #define DMA_CH8_AL2_CTRL_MSB    _u(31)
 #define DMA_CH8_AL2_CTRL_LSB    _u(0)
-#define DMA_CH8_AL2_CTRL_ACCESS "RO"
+#define DMA_CH8_AL2_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH8_AL2_TRANS_COUNT
 // Description : Alias for channel 8 TRANS_COUNT register
@@ -3453,7 +3453,7 @@
 #define DMA_CH8_AL2_TRANS_COUNT_RESET  "-"
 #define DMA_CH8_AL2_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH8_AL2_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH8_AL2_READ_ADDR
 // Description : Alias for channel 8 READ_ADDR register
@@ -3462,7 +3462,7 @@
 #define DMA_CH8_AL2_READ_ADDR_RESET  "-"
 #define DMA_CH8_AL2_READ_ADDR_MSB    _u(31)
 #define DMA_CH8_AL2_READ_ADDR_LSB    _u(0)
-#define DMA_CH8_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH8_AL2_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH8_AL2_WRITE_ADDR_TRIG
 // Description : Alias for channel 8 WRITE_ADDR register
@@ -3473,7 +3473,7 @@
 #define DMA_CH8_AL2_WRITE_ADDR_TRIG_RESET  "-"
 #define DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH8_AL3_CTRL
 // Description : Alias for channel 8 CTRL register
@@ -3482,7 +3482,7 @@
 #define DMA_CH8_AL3_CTRL_RESET  "-"
 #define DMA_CH8_AL3_CTRL_MSB    _u(31)
 #define DMA_CH8_AL3_CTRL_LSB    _u(0)
-#define DMA_CH8_AL3_CTRL_ACCESS "RO"
+#define DMA_CH8_AL3_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH8_AL3_WRITE_ADDR
 // Description : Alias for channel 8 WRITE_ADDR register
@@ -3491,7 +3491,7 @@
 #define DMA_CH8_AL3_WRITE_ADDR_RESET  "-"
 #define DMA_CH8_AL3_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH8_AL3_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH8_AL3_TRANS_COUNT
 // Description : Alias for channel 8 TRANS_COUNT register
@@ -3500,7 +3500,7 @@
 #define DMA_CH8_AL3_TRANS_COUNT_RESET  "-"
 #define DMA_CH8_AL3_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH8_AL3_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH8_AL3_READ_ADDR_TRIG
 // Description : Alias for channel 8 READ_ADDR register
@@ -3511,7 +3511,7 @@
 #define DMA_CH8_AL3_READ_ADDR_TRIG_RESET  "-"
 #define DMA_CH8_AL3_READ_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH8_AL3_READ_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH9_READ_ADDR
 // Description : DMA Channel 9 Read Address pointer
@@ -3795,7 +3795,7 @@
 #define DMA_CH9_AL1_CTRL_RESET  "-"
 #define DMA_CH9_AL1_CTRL_MSB    _u(31)
 #define DMA_CH9_AL1_CTRL_LSB    _u(0)
-#define DMA_CH9_AL1_CTRL_ACCESS "RO"
+#define DMA_CH9_AL1_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH9_AL1_READ_ADDR
 // Description : Alias for channel 9 READ_ADDR register
@@ -3804,7 +3804,7 @@
 #define DMA_CH9_AL1_READ_ADDR_RESET  "-"
 #define DMA_CH9_AL1_READ_ADDR_MSB    _u(31)
 #define DMA_CH9_AL1_READ_ADDR_LSB    _u(0)
-#define DMA_CH9_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH9_AL1_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH9_AL1_WRITE_ADDR
 // Description : Alias for channel 9 WRITE_ADDR register
@@ -3813,7 +3813,7 @@
 #define DMA_CH9_AL1_WRITE_ADDR_RESET  "-"
 #define DMA_CH9_AL1_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH9_AL1_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH9_AL1_TRANS_COUNT_TRIG
 // Description : Alias for channel 9 TRANS_COUNT register
@@ -3824,7 +3824,7 @@
 #define DMA_CH9_AL1_TRANS_COUNT_TRIG_RESET  "-"
 #define DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
 #define DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
-#define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH9_AL2_CTRL
 // Description : Alias for channel 9 CTRL register
@@ -3833,7 +3833,7 @@
 #define DMA_CH9_AL2_CTRL_RESET  "-"
 #define DMA_CH9_AL2_CTRL_MSB    _u(31)
 #define DMA_CH9_AL2_CTRL_LSB    _u(0)
-#define DMA_CH9_AL2_CTRL_ACCESS "RO"
+#define DMA_CH9_AL2_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH9_AL2_TRANS_COUNT
 // Description : Alias for channel 9 TRANS_COUNT register
@@ -3842,7 +3842,7 @@
 #define DMA_CH9_AL2_TRANS_COUNT_RESET  "-"
 #define DMA_CH9_AL2_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH9_AL2_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH9_AL2_READ_ADDR
 // Description : Alias for channel 9 READ_ADDR register
@@ -3851,7 +3851,7 @@
 #define DMA_CH9_AL2_READ_ADDR_RESET  "-"
 #define DMA_CH9_AL2_READ_ADDR_MSB    _u(31)
 #define DMA_CH9_AL2_READ_ADDR_LSB    _u(0)
-#define DMA_CH9_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH9_AL2_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH9_AL2_WRITE_ADDR_TRIG
 // Description : Alias for channel 9 WRITE_ADDR register
@@ -3862,7 +3862,7 @@
 #define DMA_CH9_AL2_WRITE_ADDR_TRIG_RESET  "-"
 #define DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH9_AL3_CTRL
 // Description : Alias for channel 9 CTRL register
@@ -3871,7 +3871,7 @@
 #define DMA_CH9_AL3_CTRL_RESET  "-"
 #define DMA_CH9_AL3_CTRL_MSB    _u(31)
 #define DMA_CH9_AL3_CTRL_LSB    _u(0)
-#define DMA_CH9_AL3_CTRL_ACCESS "RO"
+#define DMA_CH9_AL3_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH9_AL3_WRITE_ADDR
 // Description : Alias for channel 9 WRITE_ADDR register
@@ -3880,7 +3880,7 @@
 #define DMA_CH9_AL3_WRITE_ADDR_RESET  "-"
 #define DMA_CH9_AL3_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH9_AL3_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH9_AL3_TRANS_COUNT
 // Description : Alias for channel 9 TRANS_COUNT register
@@ -3889,7 +3889,7 @@
 #define DMA_CH9_AL3_TRANS_COUNT_RESET  "-"
 #define DMA_CH9_AL3_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH9_AL3_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH9_AL3_READ_ADDR_TRIG
 // Description : Alias for channel 9 READ_ADDR register
@@ -3900,7 +3900,7 @@
 #define DMA_CH9_AL3_READ_ADDR_TRIG_RESET  "-"
 #define DMA_CH9_AL3_READ_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH9_AL3_READ_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH10_READ_ADDR
 // Description : DMA Channel 10 Read Address pointer
@@ -4184,7 +4184,7 @@
 #define DMA_CH10_AL1_CTRL_RESET  "-"
 #define DMA_CH10_AL1_CTRL_MSB    _u(31)
 #define DMA_CH10_AL1_CTRL_LSB    _u(0)
-#define DMA_CH10_AL1_CTRL_ACCESS "RO"
+#define DMA_CH10_AL1_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH10_AL1_READ_ADDR
 // Description : Alias for channel 10 READ_ADDR register
@@ -4193,7 +4193,7 @@
 #define DMA_CH10_AL1_READ_ADDR_RESET  "-"
 #define DMA_CH10_AL1_READ_ADDR_MSB    _u(31)
 #define DMA_CH10_AL1_READ_ADDR_LSB    _u(0)
-#define DMA_CH10_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH10_AL1_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH10_AL1_WRITE_ADDR
 // Description : Alias for channel 10 WRITE_ADDR register
@@ -4202,7 +4202,7 @@
 #define DMA_CH10_AL1_WRITE_ADDR_RESET  "-"
 #define DMA_CH10_AL1_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH10_AL1_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH10_AL1_TRANS_COUNT_TRIG
 // Description : Alias for channel 10 TRANS_COUNT register
@@ -4213,7 +4213,7 @@
 #define DMA_CH10_AL1_TRANS_COUNT_TRIG_RESET  "-"
 #define DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
 #define DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
-#define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH10_AL2_CTRL
 // Description : Alias for channel 10 CTRL register
@@ -4222,7 +4222,7 @@
 #define DMA_CH10_AL2_CTRL_RESET  "-"
 #define DMA_CH10_AL2_CTRL_MSB    _u(31)
 #define DMA_CH10_AL2_CTRL_LSB    _u(0)
-#define DMA_CH10_AL2_CTRL_ACCESS "RO"
+#define DMA_CH10_AL2_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH10_AL2_TRANS_COUNT
 // Description : Alias for channel 10 TRANS_COUNT register
@@ -4231,7 +4231,7 @@
 #define DMA_CH10_AL2_TRANS_COUNT_RESET  "-"
 #define DMA_CH10_AL2_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH10_AL2_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH10_AL2_READ_ADDR
 // Description : Alias for channel 10 READ_ADDR register
@@ -4240,7 +4240,7 @@
 #define DMA_CH10_AL2_READ_ADDR_RESET  "-"
 #define DMA_CH10_AL2_READ_ADDR_MSB    _u(31)
 #define DMA_CH10_AL2_READ_ADDR_LSB    _u(0)
-#define DMA_CH10_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH10_AL2_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH10_AL2_WRITE_ADDR_TRIG
 // Description : Alias for channel 10 WRITE_ADDR register
@@ -4251,7 +4251,7 @@
 #define DMA_CH10_AL2_WRITE_ADDR_TRIG_RESET  "-"
 #define DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH10_AL3_CTRL
 // Description : Alias for channel 10 CTRL register
@@ -4260,7 +4260,7 @@
 #define DMA_CH10_AL3_CTRL_RESET  "-"
 #define DMA_CH10_AL3_CTRL_MSB    _u(31)
 #define DMA_CH10_AL3_CTRL_LSB    _u(0)
-#define DMA_CH10_AL3_CTRL_ACCESS "RO"
+#define DMA_CH10_AL3_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH10_AL3_WRITE_ADDR
 // Description : Alias for channel 10 WRITE_ADDR register
@@ -4269,7 +4269,7 @@
 #define DMA_CH10_AL3_WRITE_ADDR_RESET  "-"
 #define DMA_CH10_AL3_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH10_AL3_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH10_AL3_TRANS_COUNT
 // Description : Alias for channel 10 TRANS_COUNT register
@@ -4278,7 +4278,7 @@
 #define DMA_CH10_AL3_TRANS_COUNT_RESET  "-"
 #define DMA_CH10_AL3_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH10_AL3_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH10_AL3_READ_ADDR_TRIG
 // Description : Alias for channel 10 READ_ADDR register
@@ -4289,7 +4289,7 @@
 #define DMA_CH10_AL3_READ_ADDR_TRIG_RESET  "-"
 #define DMA_CH10_AL3_READ_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH10_AL3_READ_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH11_READ_ADDR
 // Description : DMA Channel 11 Read Address pointer
@@ -4573,7 +4573,7 @@
 #define DMA_CH11_AL1_CTRL_RESET  "-"
 #define DMA_CH11_AL1_CTRL_MSB    _u(31)
 #define DMA_CH11_AL1_CTRL_LSB    _u(0)
-#define DMA_CH11_AL1_CTRL_ACCESS "RO"
+#define DMA_CH11_AL1_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH11_AL1_READ_ADDR
 // Description : Alias for channel 11 READ_ADDR register
@@ -4582,7 +4582,7 @@
 #define DMA_CH11_AL1_READ_ADDR_RESET  "-"
 #define DMA_CH11_AL1_READ_ADDR_MSB    _u(31)
 #define DMA_CH11_AL1_READ_ADDR_LSB    _u(0)
-#define DMA_CH11_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH11_AL1_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH11_AL1_WRITE_ADDR
 // Description : Alias for channel 11 WRITE_ADDR register
@@ -4591,7 +4591,7 @@
 #define DMA_CH11_AL1_WRITE_ADDR_RESET  "-"
 #define DMA_CH11_AL1_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH11_AL1_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH11_AL1_TRANS_COUNT_TRIG
 // Description : Alias for channel 11 TRANS_COUNT register
@@ -4602,7 +4602,7 @@
 #define DMA_CH11_AL1_TRANS_COUNT_TRIG_RESET  "-"
 #define DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
 #define DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
-#define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH11_AL2_CTRL
 // Description : Alias for channel 11 CTRL register
@@ -4611,7 +4611,7 @@
 #define DMA_CH11_AL2_CTRL_RESET  "-"
 #define DMA_CH11_AL2_CTRL_MSB    _u(31)
 #define DMA_CH11_AL2_CTRL_LSB    _u(0)
-#define DMA_CH11_AL2_CTRL_ACCESS "RO"
+#define DMA_CH11_AL2_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH11_AL2_TRANS_COUNT
 // Description : Alias for channel 11 TRANS_COUNT register
@@ -4620,7 +4620,7 @@
 #define DMA_CH11_AL2_TRANS_COUNT_RESET  "-"
 #define DMA_CH11_AL2_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH11_AL2_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH11_AL2_READ_ADDR
 // Description : Alias for channel 11 READ_ADDR register
@@ -4629,7 +4629,7 @@
 #define DMA_CH11_AL2_READ_ADDR_RESET  "-"
 #define DMA_CH11_AL2_READ_ADDR_MSB    _u(31)
 #define DMA_CH11_AL2_READ_ADDR_LSB    _u(0)
-#define DMA_CH11_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH11_AL2_READ_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH11_AL2_WRITE_ADDR_TRIG
 // Description : Alias for channel 11 WRITE_ADDR register
@@ -4640,7 +4640,7 @@
 #define DMA_CH11_AL2_WRITE_ADDR_TRIG_RESET  "-"
 #define DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH11_AL3_CTRL
 // Description : Alias for channel 11 CTRL register
@@ -4649,7 +4649,7 @@
 #define DMA_CH11_AL3_CTRL_RESET  "-"
 #define DMA_CH11_AL3_CTRL_MSB    _u(31)
 #define DMA_CH11_AL3_CTRL_LSB    _u(0)
-#define DMA_CH11_AL3_CTRL_ACCESS "RO"
+#define DMA_CH11_AL3_CTRL_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH11_AL3_WRITE_ADDR
 // Description : Alias for channel 11 WRITE_ADDR register
@@ -4658,7 +4658,7 @@
 #define DMA_CH11_AL3_WRITE_ADDR_RESET  "-"
 #define DMA_CH11_AL3_WRITE_ADDR_MSB    _u(31)
 #define DMA_CH11_AL3_WRITE_ADDR_LSB    _u(0)
-#define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH11_AL3_TRANS_COUNT
 // Description : Alias for channel 11 TRANS_COUNT register
@@ -4667,7 +4667,7 @@
 #define DMA_CH11_AL3_TRANS_COUNT_RESET  "-"
 #define DMA_CH11_AL3_TRANS_COUNT_MSB    _u(31)
 #define DMA_CH11_AL3_TRANS_COUNT_LSB    _u(0)
-#define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_CH11_AL3_READ_ADDR_TRIG
 // Description : Alias for channel 11 READ_ADDR register
@@ -4678,7 +4678,7 @@
 #define DMA_CH11_AL3_READ_ADDR_TRIG_RESET  "-"
 #define DMA_CH11_AL3_READ_ADDR_TRIG_MSB    _u(31)
 #define DMA_CH11_AL3_READ_ADDR_TRIG_LSB    _u(0)
-#define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RW"
 // =============================================================================
 // Register    : DMA_INTR
 // Description : Interrupt Status (raw)
@@ -5056,7 +5056,7 @@
 #define DMA_CH0_DBG_CTDREQ_RESET  _u(0x00000000)
 #define DMA_CH0_DBG_CTDREQ_MSB    _u(5)
 #define DMA_CH0_DBG_CTDREQ_LSB    _u(0)
-#define DMA_CH0_DBG_CTDREQ_ACCESS "RO"
+#define DMA_CH0_DBG_CTDREQ_ACCESS "WC"
 // =============================================================================
 // Register    : DMA_CH0_DBG_TCR
 // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5078,7 +5078,7 @@
 #define DMA_CH1_DBG_CTDREQ_RESET  _u(0x00000000)
 #define DMA_CH1_DBG_CTDREQ_MSB    _u(5)
 #define DMA_CH1_DBG_CTDREQ_LSB    _u(0)
-#define DMA_CH1_DBG_CTDREQ_ACCESS "RO"
+#define DMA_CH1_DBG_CTDREQ_ACCESS "WC"
 // =============================================================================
 // Register    : DMA_CH1_DBG_TCR
 // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5100,7 +5100,7 @@
 #define DMA_CH2_DBG_CTDREQ_RESET  _u(0x00000000)
 #define DMA_CH2_DBG_CTDREQ_MSB    _u(5)
 #define DMA_CH2_DBG_CTDREQ_LSB    _u(0)
-#define DMA_CH2_DBG_CTDREQ_ACCESS "RO"
+#define DMA_CH2_DBG_CTDREQ_ACCESS "WC"
 // =============================================================================
 // Register    : DMA_CH2_DBG_TCR
 // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5122,7 +5122,7 @@
 #define DMA_CH3_DBG_CTDREQ_RESET  _u(0x00000000)
 #define DMA_CH3_DBG_CTDREQ_MSB    _u(5)
 #define DMA_CH3_DBG_CTDREQ_LSB    _u(0)
-#define DMA_CH3_DBG_CTDREQ_ACCESS "RO"
+#define DMA_CH3_DBG_CTDREQ_ACCESS "WC"
 // =============================================================================
 // Register    : DMA_CH3_DBG_TCR
 // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5144,7 +5144,7 @@
 #define DMA_CH4_DBG_CTDREQ_RESET  _u(0x00000000)
 #define DMA_CH4_DBG_CTDREQ_MSB    _u(5)
 #define DMA_CH4_DBG_CTDREQ_LSB    _u(0)
-#define DMA_CH4_DBG_CTDREQ_ACCESS "RO"
+#define DMA_CH4_DBG_CTDREQ_ACCESS "WC"
 // =============================================================================
 // Register    : DMA_CH4_DBG_TCR
 // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5166,7 +5166,7 @@
 #define DMA_CH5_DBG_CTDREQ_RESET  _u(0x00000000)
 #define DMA_CH5_DBG_CTDREQ_MSB    _u(5)
 #define DMA_CH5_DBG_CTDREQ_LSB    _u(0)
-#define DMA_CH5_DBG_CTDREQ_ACCESS "RO"
+#define DMA_CH5_DBG_CTDREQ_ACCESS "WC"
 // =============================================================================
 // Register    : DMA_CH5_DBG_TCR
 // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5188,7 +5188,7 @@
 #define DMA_CH6_DBG_CTDREQ_RESET  _u(0x00000000)
 #define DMA_CH6_DBG_CTDREQ_MSB    _u(5)
 #define DMA_CH6_DBG_CTDREQ_LSB    _u(0)
-#define DMA_CH6_DBG_CTDREQ_ACCESS "RO"
+#define DMA_CH6_DBG_CTDREQ_ACCESS "WC"
 // =============================================================================
 // Register    : DMA_CH6_DBG_TCR
 // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5210,7 +5210,7 @@
 #define DMA_CH7_DBG_CTDREQ_RESET  _u(0x00000000)
 #define DMA_CH7_DBG_CTDREQ_MSB    _u(5)
 #define DMA_CH7_DBG_CTDREQ_LSB    _u(0)
-#define DMA_CH7_DBG_CTDREQ_ACCESS "RO"
+#define DMA_CH7_DBG_CTDREQ_ACCESS "WC"
 // =============================================================================
 // Register    : DMA_CH7_DBG_TCR
 // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5232,7 +5232,7 @@
 #define DMA_CH8_DBG_CTDREQ_RESET  _u(0x00000000)
 #define DMA_CH8_DBG_CTDREQ_MSB    _u(5)
 #define DMA_CH8_DBG_CTDREQ_LSB    _u(0)
-#define DMA_CH8_DBG_CTDREQ_ACCESS "RO"
+#define DMA_CH8_DBG_CTDREQ_ACCESS "WC"
 // =============================================================================
 // Register    : DMA_CH8_DBG_TCR
 // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5254,7 +5254,7 @@
 #define DMA_CH9_DBG_CTDREQ_RESET  _u(0x00000000)
 #define DMA_CH9_DBG_CTDREQ_MSB    _u(5)
 #define DMA_CH9_DBG_CTDREQ_LSB    _u(0)
-#define DMA_CH9_DBG_CTDREQ_ACCESS "RO"
+#define DMA_CH9_DBG_CTDREQ_ACCESS "WC"
 // =============================================================================
 // Register    : DMA_CH9_DBG_TCR
 // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5276,7 +5276,7 @@
 #define DMA_CH10_DBG_CTDREQ_RESET  _u(0x00000000)
 #define DMA_CH10_DBG_CTDREQ_MSB    _u(5)
 #define DMA_CH10_DBG_CTDREQ_LSB    _u(0)
-#define DMA_CH10_DBG_CTDREQ_ACCESS "RO"
+#define DMA_CH10_DBG_CTDREQ_ACCESS "WC"
 // =============================================================================
 // Register    : DMA_CH10_DBG_TCR
 // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5298,7 +5298,7 @@
 #define DMA_CH11_DBG_CTDREQ_RESET  _u(0x00000000)
 #define DMA_CH11_DBG_CTDREQ_MSB    _u(5)
 #define DMA_CH11_DBG_CTDREQ_LSB    _u(0)
-#define DMA_CH11_DBG_CTDREQ_ACCESS "RO"
+#define DMA_CH11_DBG_CTDREQ_ACCESS "WC"
 // =============================================================================
 // Register    : DMA_CH11_DBG_TCR
 // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/i2c.h b/src/rp2040/hardware_regs/include/hardware/regs/i2c.h
index 9384bed05..dcddb06a0 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/i2c.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/i2c.h
@@ -8,6 +8,80 @@
 // Version        : 1
 // Bus type       : apb
 // Description    : DW_apb_i2c address block
+//
+//                  List of configuration constants for the Synopsys I2C
+//                  hardware (you may see references to these in I2C register
+//                  header; these are *fixed* values, set at hardware design
+//                  time):
+//
+//                  IC_ULTRA_FAST_MODE ................ 0x0
+//                  IC_UFM_TBUF_CNT_DEFAULT ........... 0x8
+//                  IC_UFM_SCL_LOW_COUNT .............. 0x0008
+//                  IC_UFM_SCL_HIGH_COUNT ............. 0x0006
+//                  IC_TX_TL .......................... 0x0
+//                  IC_TX_CMD_BLOCK ................... 0x1
+//                  IC_HAS_DMA ........................ 0x1
+//                  IC_HAS_ASYNC_FIFO ................. 0x0
+//                  IC_SMBUS_ARP ...................... 0x0
+//                  IC_FIRST_DATA_BYTE_STATUS ......... 0x1
+//                  IC_INTR_IO ........................ 0x1
+//                  IC_MASTER_MODE .................... 0x1
+//                  IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1
+//                  IC_INTR_POL ....................... 0x1
+//                  IC_OPTIONAL_SAR ................... 0x0
+//                  IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055
+//                  IC_DEFAULT_SLAVE_ADDR ............. 0x055
+//                  IC_DEFAULT_HS_SPKLEN .............. 0x1
+//                  IC_FS_SCL_HIGH_COUNT .............. 0x0006
+//                  IC_HS_SCL_LOW_COUNT ............... 0x0008
+//                  IC_DEVICE_ID_VALUE ................ 0x0
+//                  IC_10BITADDR_MASTER ............... 0x0
+//                  IC_CLK_FREQ_OPTIMIZATION .......... 0x0
+//                  IC_DEFAULT_FS_SPKLEN .............. 0x7
+//                  IC_ADD_ENCODED_PARAMS ............. 0x0
+//                  IC_DEFAULT_SDA_HOLD ............... 0x000001
+//                  IC_DEFAULT_SDA_SETUP .............. 0x64
+//                  IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
+//                  IC_CLOCK_PERIOD ................... 100
+//                  IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1
+//                  IC_RESTART_EN ..................... 0x1
+//                  IC_TX_CMD_BLOCK_DEFAULT ........... 0x0
+//                  IC_BUS_CLEAR_FEATURE .............. 0x0
+//                  IC_CAP_LOADING .................... 100
+//                  IC_FS_SCL_LOW_COUNT ............... 0x000d
+//                  APB_DATA_WIDTH .................... 32
+//                  IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
+//                  IC_SLV_DATA_NACK_ONLY ............. 0x1
+//                  IC_10BITADDR_SLAVE ................ 0x0
+//                  IC_CLK_TYPE ....................... 0x0
+//                  IC_SMBUS_UDID_MSB ................. 0x0
+//                  IC_SMBUS_SUSPEND_ALERT ............ 0x0
+//                  IC_HS_SCL_HIGH_COUNT .............. 0x0006
+//                  IC_SLV_RESTART_DET_EN ............. 0x1
+//                  IC_SMBUS .......................... 0x0
+//                  IC_OPTIONAL_SAR_DEFAULT ........... 0x0
+//                  IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0
+//                  IC_USE_COUNTS ..................... 0x0
+//                  IC_RX_BUFFER_DEPTH ................ 16
+//                  IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
+//                  IC_RX_FULL_HLD_BUS_EN ............. 0x1
+//                  IC_SLAVE_DISABLE .................. 0x1
+//                  IC_RX_TL .......................... 0x0
+//                  IC_DEVICE_ID ...................... 0x0
+//                  IC_HC_COUNT_VALUES ................ 0x0
+//                  I2C_DYNAMIC_TAR_UPDATE ............ 0
+//                  IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff
+//                  IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff
+//                  IC_HS_MASTER_CODE ................. 0x1
+//                  IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff
+//                  IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff
+//                  IC_SS_SCL_HIGH_COUNT .............. 0x0028
+//                  IC_SS_SCL_LOW_COUNT ............... 0x002f
+//                  IC_MAX_SPEED_MODE ................. 0x2
+//                  IC_STAT_FOR_CLK_STRETCH ........... 0x0
+//                  IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
+//                  IC_DEFAULT_UFM_SPKLEN ............. 0x1
+//                  IC_TX_BUFFER_DEPTH ................ 16
 // =============================================================================
 #ifndef HARDWARE_REGS_I2C_DEFINED
 #define HARDWARE_REGS_I2C_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/pio.h b/src/rp2040/hardware_regs/include/hardware/regs/pio.h
index 8b4829fbc..b231882ac 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/pio.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/pio.h
@@ -378,7 +378,8 @@
 // =============================================================================
 // Register    : PIO_DBG_PADOUT
 // Description : Read to sample the pad output values PIO is currently driving
-//               to the GPIOs.
+//               to the GPIOs. On RP2040 there are 30 GPIOs, so the two most
+//               significant bits are hardwired to 0.
 #define PIO_DBG_PADOUT_OFFSET _u(0x0000003c)
 #define PIO_DBG_PADOUT_BITS   _u(0xffffffff)
 #define PIO_DBG_PADOUT_RESET  _u(0x00000000)
@@ -388,7 +389,8 @@
 // =============================================================================
 // Register    : PIO_DBG_PADOE
 // Description : Read to sample the pad output enables (direction) PIO is
-//               currently driving to the GPIOs.
+//               currently driving to the GPIOs. On RP2040 there are 30 GPIOs,
+//               so the two most significant bits are hardwired to 0.
 #define PIO_DBG_PADOE_OFFSET _u(0x00000040)
 #define PIO_DBG_PADOE_BITS   _u(0xffffffff)
 #define PIO_DBG_PADOE_RESET  _u(0x00000000)
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/sio.h b/src/rp2040/hardware_regs/include/hardware/regs/sio.h
index 37ee2c133..f64153397 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/sio.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/sio.h
@@ -71,7 +71,7 @@
 #define SIO_GPIO_OUT_SET_RESET  _u(0x00000000)
 #define SIO_GPIO_OUT_SET_MSB    _u(29)
 #define SIO_GPIO_OUT_SET_LSB    _u(0)
-#define SIO_GPIO_OUT_SET_ACCESS "RW"
+#define SIO_GPIO_OUT_SET_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_OUT_CLR
 // Description : GPIO output value clear
@@ -82,7 +82,7 @@
 #define SIO_GPIO_OUT_CLR_RESET  _u(0x00000000)
 #define SIO_GPIO_OUT_CLR_MSB    _u(29)
 #define SIO_GPIO_OUT_CLR_LSB    _u(0)
-#define SIO_GPIO_OUT_CLR_ACCESS "RW"
+#define SIO_GPIO_OUT_CLR_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_OUT_XOR
 // Description : GPIO output value XOR
@@ -93,7 +93,7 @@
 #define SIO_GPIO_OUT_XOR_RESET  _u(0x00000000)
 #define SIO_GPIO_OUT_XOR_MSB    _u(29)
 #define SIO_GPIO_OUT_XOR_LSB    _u(0)
-#define SIO_GPIO_OUT_XOR_ACCESS "RW"
+#define SIO_GPIO_OUT_XOR_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_OE
 // Description : GPIO output enable
@@ -119,7 +119,7 @@
 #define SIO_GPIO_OE_SET_RESET  _u(0x00000000)
 #define SIO_GPIO_OE_SET_MSB    _u(29)
 #define SIO_GPIO_OE_SET_LSB    _u(0)
-#define SIO_GPIO_OE_SET_ACCESS "RW"
+#define SIO_GPIO_OE_SET_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_OE_CLR
 // Description : GPIO output enable clear
@@ -130,7 +130,7 @@
 #define SIO_GPIO_OE_CLR_RESET  _u(0x00000000)
 #define SIO_GPIO_OE_CLR_MSB    _u(29)
 #define SIO_GPIO_OE_CLR_LSB    _u(0)
-#define SIO_GPIO_OE_CLR_ACCESS "RW"
+#define SIO_GPIO_OE_CLR_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_OE_XOR
 // Description : GPIO output enable XOR
@@ -141,7 +141,7 @@
 #define SIO_GPIO_OE_XOR_RESET  _u(0x00000000)
 #define SIO_GPIO_OE_XOR_MSB    _u(29)
 #define SIO_GPIO_OE_XOR_LSB    _u(0)
-#define SIO_GPIO_OE_XOR_ACCESS "RW"
+#define SIO_GPIO_OE_XOR_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_HI_OUT
 // Description : QSPI output value
@@ -169,7 +169,7 @@
 #define SIO_GPIO_HI_OUT_SET_RESET  _u(0x00000000)
 #define SIO_GPIO_HI_OUT_SET_MSB    _u(5)
 #define SIO_GPIO_HI_OUT_SET_LSB    _u(0)
-#define SIO_GPIO_HI_OUT_SET_ACCESS "RW"
+#define SIO_GPIO_HI_OUT_SET_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_HI_OUT_CLR
 // Description : QSPI output value clear
@@ -180,7 +180,7 @@
 #define SIO_GPIO_HI_OUT_CLR_RESET  _u(0x00000000)
 #define SIO_GPIO_HI_OUT_CLR_MSB    _u(5)
 #define SIO_GPIO_HI_OUT_CLR_LSB    _u(0)
-#define SIO_GPIO_HI_OUT_CLR_ACCESS "RW"
+#define SIO_GPIO_HI_OUT_CLR_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_HI_OUT_XOR
 // Description : QSPI output value XOR
@@ -191,7 +191,7 @@
 #define SIO_GPIO_HI_OUT_XOR_RESET  _u(0x00000000)
 #define SIO_GPIO_HI_OUT_XOR_MSB    _u(5)
 #define SIO_GPIO_HI_OUT_XOR_LSB    _u(0)
-#define SIO_GPIO_HI_OUT_XOR_ACCESS "RW"
+#define SIO_GPIO_HI_OUT_XOR_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_HI_OE
 // Description : QSPI output enable
@@ -218,7 +218,7 @@
 #define SIO_GPIO_HI_OE_SET_RESET  _u(0x00000000)
 #define SIO_GPIO_HI_OE_SET_MSB    _u(5)
 #define SIO_GPIO_HI_OE_SET_LSB    _u(0)
-#define SIO_GPIO_HI_OE_SET_ACCESS "RW"
+#define SIO_GPIO_HI_OE_SET_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_HI_OE_CLR
 // Description : QSPI output enable clear
@@ -229,7 +229,7 @@
 #define SIO_GPIO_HI_OE_CLR_RESET  _u(0x00000000)
 #define SIO_GPIO_HI_OE_CLR_MSB    _u(5)
 #define SIO_GPIO_HI_OE_CLR_LSB    _u(0)
-#define SIO_GPIO_HI_OE_CLR_ACCESS "RW"
+#define SIO_GPIO_HI_OE_CLR_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_HI_OE_XOR
 // Description : QSPI output enable XOR
@@ -240,7 +240,7 @@
 #define SIO_GPIO_HI_OE_XOR_RESET  _u(0x00000000)
 #define SIO_GPIO_HI_OE_XOR_MSB    _u(5)
 #define SIO_GPIO_HI_OE_XOR_LSB    _u(0)
-#define SIO_GPIO_HI_OE_XOR_ACCESS "RW"
+#define SIO_GPIO_HI_OE_XOR_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_FIFO_ST
 // Description : Status register for inter-core FIFOs (mailboxes).
@@ -1155,7 +1155,7 @@
 #define SIO_SPINLOCK0_RESET  _u(0x00000000)
 #define SIO_SPINLOCK0_MSB    _u(31)
 #define SIO_SPINLOCK0_LSB    _u(0)
-#define SIO_SPINLOCK0_ACCESS "RO"
+#define SIO_SPINLOCK0_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK1
 // Description : Reading from a spinlock address will:
@@ -1171,7 +1171,7 @@
 #define SIO_SPINLOCK1_RESET  _u(0x00000000)
 #define SIO_SPINLOCK1_MSB    _u(31)
 #define SIO_SPINLOCK1_LSB    _u(0)
-#define SIO_SPINLOCK1_ACCESS "RO"
+#define SIO_SPINLOCK1_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK2
 // Description : Reading from a spinlock address will:
@@ -1187,7 +1187,7 @@
 #define SIO_SPINLOCK2_RESET  _u(0x00000000)
 #define SIO_SPINLOCK2_MSB    _u(31)
 #define SIO_SPINLOCK2_LSB    _u(0)
-#define SIO_SPINLOCK2_ACCESS "RO"
+#define SIO_SPINLOCK2_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK3
 // Description : Reading from a spinlock address will:
@@ -1203,7 +1203,7 @@
 #define SIO_SPINLOCK3_RESET  _u(0x00000000)
 #define SIO_SPINLOCK3_MSB    _u(31)
 #define SIO_SPINLOCK3_LSB    _u(0)
-#define SIO_SPINLOCK3_ACCESS "RO"
+#define SIO_SPINLOCK3_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK4
 // Description : Reading from a spinlock address will:
@@ -1219,7 +1219,7 @@
 #define SIO_SPINLOCK4_RESET  _u(0x00000000)
 #define SIO_SPINLOCK4_MSB    _u(31)
 #define SIO_SPINLOCK4_LSB    _u(0)
-#define SIO_SPINLOCK4_ACCESS "RO"
+#define SIO_SPINLOCK4_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK5
 // Description : Reading from a spinlock address will:
@@ -1235,7 +1235,7 @@
 #define SIO_SPINLOCK5_RESET  _u(0x00000000)
 #define SIO_SPINLOCK5_MSB    _u(31)
 #define SIO_SPINLOCK5_LSB    _u(0)
-#define SIO_SPINLOCK5_ACCESS "RO"
+#define SIO_SPINLOCK5_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK6
 // Description : Reading from a spinlock address will:
@@ -1251,7 +1251,7 @@
 #define SIO_SPINLOCK6_RESET  _u(0x00000000)
 #define SIO_SPINLOCK6_MSB    _u(31)
 #define SIO_SPINLOCK6_LSB    _u(0)
-#define SIO_SPINLOCK6_ACCESS "RO"
+#define SIO_SPINLOCK6_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK7
 // Description : Reading from a spinlock address will:
@@ -1267,7 +1267,7 @@
 #define SIO_SPINLOCK7_RESET  _u(0x00000000)
 #define SIO_SPINLOCK7_MSB    _u(31)
 #define SIO_SPINLOCK7_LSB    _u(0)
-#define SIO_SPINLOCK7_ACCESS "RO"
+#define SIO_SPINLOCK7_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK8
 // Description : Reading from a spinlock address will:
@@ -1283,7 +1283,7 @@
 #define SIO_SPINLOCK8_RESET  _u(0x00000000)
 #define SIO_SPINLOCK8_MSB    _u(31)
 #define SIO_SPINLOCK8_LSB    _u(0)
-#define SIO_SPINLOCK8_ACCESS "RO"
+#define SIO_SPINLOCK8_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK9
 // Description : Reading from a spinlock address will:
@@ -1299,7 +1299,7 @@
 #define SIO_SPINLOCK9_RESET  _u(0x00000000)
 #define SIO_SPINLOCK9_MSB    _u(31)
 #define SIO_SPINLOCK9_LSB    _u(0)
-#define SIO_SPINLOCK9_ACCESS "RO"
+#define SIO_SPINLOCK9_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK10
 // Description : Reading from a spinlock address will:
@@ -1315,7 +1315,7 @@
 #define SIO_SPINLOCK10_RESET  _u(0x00000000)
 #define SIO_SPINLOCK10_MSB    _u(31)
 #define SIO_SPINLOCK10_LSB    _u(0)
-#define SIO_SPINLOCK10_ACCESS "RO"
+#define SIO_SPINLOCK10_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK11
 // Description : Reading from a spinlock address will:
@@ -1331,7 +1331,7 @@
 #define SIO_SPINLOCK11_RESET  _u(0x00000000)
 #define SIO_SPINLOCK11_MSB    _u(31)
 #define SIO_SPINLOCK11_LSB    _u(0)
-#define SIO_SPINLOCK11_ACCESS "RO"
+#define SIO_SPINLOCK11_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK12
 // Description : Reading from a spinlock address will:
@@ -1347,7 +1347,7 @@
 #define SIO_SPINLOCK12_RESET  _u(0x00000000)
 #define SIO_SPINLOCK12_MSB    _u(31)
 #define SIO_SPINLOCK12_LSB    _u(0)
-#define SIO_SPINLOCK12_ACCESS "RO"
+#define SIO_SPINLOCK12_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK13
 // Description : Reading from a spinlock address will:
@@ -1363,7 +1363,7 @@
 #define SIO_SPINLOCK13_RESET  _u(0x00000000)
 #define SIO_SPINLOCK13_MSB    _u(31)
 #define SIO_SPINLOCK13_LSB    _u(0)
-#define SIO_SPINLOCK13_ACCESS "RO"
+#define SIO_SPINLOCK13_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK14
 // Description : Reading from a spinlock address will:
@@ -1379,7 +1379,7 @@
 #define SIO_SPINLOCK14_RESET  _u(0x00000000)
 #define SIO_SPINLOCK14_MSB    _u(31)
 #define SIO_SPINLOCK14_LSB    _u(0)
-#define SIO_SPINLOCK14_ACCESS "RO"
+#define SIO_SPINLOCK14_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK15
 // Description : Reading from a spinlock address will:
@@ -1395,7 +1395,7 @@
 #define SIO_SPINLOCK15_RESET  _u(0x00000000)
 #define SIO_SPINLOCK15_MSB    _u(31)
 #define SIO_SPINLOCK15_LSB    _u(0)
-#define SIO_SPINLOCK15_ACCESS "RO"
+#define SIO_SPINLOCK15_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK16
 // Description : Reading from a spinlock address will:
@@ -1411,7 +1411,7 @@
 #define SIO_SPINLOCK16_RESET  _u(0x00000000)
 #define SIO_SPINLOCK16_MSB    _u(31)
 #define SIO_SPINLOCK16_LSB    _u(0)
-#define SIO_SPINLOCK16_ACCESS "RO"
+#define SIO_SPINLOCK16_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK17
 // Description : Reading from a spinlock address will:
@@ -1427,7 +1427,7 @@
 #define SIO_SPINLOCK17_RESET  _u(0x00000000)
 #define SIO_SPINLOCK17_MSB    _u(31)
 #define SIO_SPINLOCK17_LSB    _u(0)
-#define SIO_SPINLOCK17_ACCESS "RO"
+#define SIO_SPINLOCK17_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK18
 // Description : Reading from a spinlock address will:
@@ -1443,7 +1443,7 @@
 #define SIO_SPINLOCK18_RESET  _u(0x00000000)
 #define SIO_SPINLOCK18_MSB    _u(31)
 #define SIO_SPINLOCK18_LSB    _u(0)
-#define SIO_SPINLOCK18_ACCESS "RO"
+#define SIO_SPINLOCK18_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK19
 // Description : Reading from a spinlock address will:
@@ -1459,7 +1459,7 @@
 #define SIO_SPINLOCK19_RESET  _u(0x00000000)
 #define SIO_SPINLOCK19_MSB    _u(31)
 #define SIO_SPINLOCK19_LSB    _u(0)
-#define SIO_SPINLOCK19_ACCESS "RO"
+#define SIO_SPINLOCK19_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK20
 // Description : Reading from a spinlock address will:
@@ -1475,7 +1475,7 @@
 #define SIO_SPINLOCK20_RESET  _u(0x00000000)
 #define SIO_SPINLOCK20_MSB    _u(31)
 #define SIO_SPINLOCK20_LSB    _u(0)
-#define SIO_SPINLOCK20_ACCESS "RO"
+#define SIO_SPINLOCK20_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK21
 // Description : Reading from a spinlock address will:
@@ -1491,7 +1491,7 @@
 #define SIO_SPINLOCK21_RESET  _u(0x00000000)
 #define SIO_SPINLOCK21_MSB    _u(31)
 #define SIO_SPINLOCK21_LSB    _u(0)
-#define SIO_SPINLOCK21_ACCESS "RO"
+#define SIO_SPINLOCK21_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK22
 // Description : Reading from a spinlock address will:
@@ -1507,7 +1507,7 @@
 #define SIO_SPINLOCK22_RESET  _u(0x00000000)
 #define SIO_SPINLOCK22_MSB    _u(31)
 #define SIO_SPINLOCK22_LSB    _u(0)
-#define SIO_SPINLOCK22_ACCESS "RO"
+#define SIO_SPINLOCK22_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK23
 // Description : Reading from a spinlock address will:
@@ -1523,7 +1523,7 @@
 #define SIO_SPINLOCK23_RESET  _u(0x00000000)
 #define SIO_SPINLOCK23_MSB    _u(31)
 #define SIO_SPINLOCK23_LSB    _u(0)
-#define SIO_SPINLOCK23_ACCESS "RO"
+#define SIO_SPINLOCK23_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK24
 // Description : Reading from a spinlock address will:
@@ -1539,7 +1539,7 @@
 #define SIO_SPINLOCK24_RESET  _u(0x00000000)
 #define SIO_SPINLOCK24_MSB    _u(31)
 #define SIO_SPINLOCK24_LSB    _u(0)
-#define SIO_SPINLOCK24_ACCESS "RO"
+#define SIO_SPINLOCK24_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK25
 // Description : Reading from a spinlock address will:
@@ -1555,7 +1555,7 @@
 #define SIO_SPINLOCK25_RESET  _u(0x00000000)
 #define SIO_SPINLOCK25_MSB    _u(31)
 #define SIO_SPINLOCK25_LSB    _u(0)
-#define SIO_SPINLOCK25_ACCESS "RO"
+#define SIO_SPINLOCK25_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK26
 // Description : Reading from a spinlock address will:
@@ -1571,7 +1571,7 @@
 #define SIO_SPINLOCK26_RESET  _u(0x00000000)
 #define SIO_SPINLOCK26_MSB    _u(31)
 #define SIO_SPINLOCK26_LSB    _u(0)
-#define SIO_SPINLOCK26_ACCESS "RO"
+#define SIO_SPINLOCK26_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK27
 // Description : Reading from a spinlock address will:
@@ -1587,7 +1587,7 @@
 #define SIO_SPINLOCK27_RESET  _u(0x00000000)
 #define SIO_SPINLOCK27_MSB    _u(31)
 #define SIO_SPINLOCK27_LSB    _u(0)
-#define SIO_SPINLOCK27_ACCESS "RO"
+#define SIO_SPINLOCK27_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK28
 // Description : Reading from a spinlock address will:
@@ -1603,7 +1603,7 @@
 #define SIO_SPINLOCK28_RESET  _u(0x00000000)
 #define SIO_SPINLOCK28_MSB    _u(31)
 #define SIO_SPINLOCK28_LSB    _u(0)
-#define SIO_SPINLOCK28_ACCESS "RO"
+#define SIO_SPINLOCK28_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK29
 // Description : Reading from a spinlock address will:
@@ -1619,7 +1619,7 @@
 #define SIO_SPINLOCK29_RESET  _u(0x00000000)
 #define SIO_SPINLOCK29_MSB    _u(31)
 #define SIO_SPINLOCK29_LSB    _u(0)
-#define SIO_SPINLOCK29_ACCESS "RO"
+#define SIO_SPINLOCK29_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK30
 // Description : Reading from a spinlock address will:
@@ -1635,7 +1635,7 @@
 #define SIO_SPINLOCK30_RESET  _u(0x00000000)
 #define SIO_SPINLOCK30_MSB    _u(31)
 #define SIO_SPINLOCK30_LSB    _u(0)
-#define SIO_SPINLOCK30_ACCESS "RO"
+#define SIO_SPINLOCK30_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK31
 // Description : Reading from a spinlock address will:
@@ -1651,6 +1651,6 @@
 #define SIO_SPINLOCK31_RESET  _u(0x00000000)
 #define SIO_SPINLOCK31_MSB    _u(31)
 #define SIO_SPINLOCK31_LSB    _u(0)
-#define SIO_SPINLOCK31_ACCESS "RO"
+#define SIO_SPINLOCK31_ACCESS "RW"
 // =============================================================================
 #endif // HARDWARE_REGS_SIO_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/usb.h b/src/rp2040/hardware_regs/include/hardware/regs/usb.h
index 5461c2915..552cd11a8 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/usb.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/usb.h
@@ -1012,7 +1012,7 @@
 #define USB_SIE_STATUS_CONNECTED_BITS   _u(0x00010000)
 #define USB_SIE_STATUS_CONNECTED_MSB    _u(16)
 #define USB_SIE_STATUS_CONNECTED_LSB    _u(16)
-#define USB_SIE_STATUS_CONNECTED_ACCESS "RO"
+#define USB_SIE_STATUS_CONNECTED_ACCESS "WC"
 // -----------------------------------------------------------------------------
 // Field       : USB_SIE_STATUS_RESUME
 // Description : Host: Device has initiated a remote resume. Device: host has
@@ -1037,7 +1037,7 @@
 #define USB_SIE_STATUS_SPEED_BITS   _u(0x00000300)
 #define USB_SIE_STATUS_SPEED_MSB    _u(9)
 #define USB_SIE_STATUS_SPEED_LSB    _u(8)
-#define USB_SIE_STATUS_SPEED_ACCESS "RO"
+#define USB_SIE_STATUS_SPEED_ACCESS "WC"
 // -----------------------------------------------------------------------------
 // Field       : USB_SIE_STATUS_SUSPENDED
 // Description : Bus in suspended state. Valid for device and host. Host and
@@ -1047,7 +1047,7 @@
 #define USB_SIE_STATUS_SUSPENDED_BITS   _u(0x00000010)
 #define USB_SIE_STATUS_SUSPENDED_MSB    _u(4)
 #define USB_SIE_STATUS_SUSPENDED_LSB    _u(4)
-#define USB_SIE_STATUS_SUSPENDED_ACCESS "RO"
+#define USB_SIE_STATUS_SUSPENDED_ACCESS "WC"
 // -----------------------------------------------------------------------------
 // Field       : USB_SIE_STATUS_LINE_STATE
 // Description : USB bus line state
@@ -2965,7 +2965,7 @@
 #define USB_INTR_BUS_RESET_ACCESS "RO"
 // -----------------------------------------------------------------------------
 // Field       : USB_INTR_VBUS_DETECT
-// Description : Source: SIE_STATUS.VBUS_DETECT
+// Description : Source: SIE_STATUS.VBUS_DETECTED
 #define USB_INTR_VBUS_DETECT_RESET  _u(0x0)
 #define USB_INTR_VBUS_DETECT_BITS   _u(0x00000800)
 #define USB_INTR_VBUS_DETECT_MSB    _u(11)
@@ -3143,7 +3143,7 @@
 #define USB_INTE_BUS_RESET_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_INTE_VBUS_DETECT
-// Description : Source: SIE_STATUS.VBUS_DETECT
+// Description : Source: SIE_STATUS.VBUS_DETECTED
 #define USB_INTE_VBUS_DETECT_RESET  _u(0x0)
 #define USB_INTE_VBUS_DETECT_BITS   _u(0x00000800)
 #define USB_INTE_VBUS_DETECT_MSB    _u(11)
@@ -3321,7 +3321,7 @@
 #define USB_INTF_BUS_RESET_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_INTF_VBUS_DETECT
-// Description : Source: SIE_STATUS.VBUS_DETECT
+// Description : Source: SIE_STATUS.VBUS_DETECTED
 #define USB_INTF_VBUS_DETECT_RESET  _u(0x0)
 #define USB_INTF_VBUS_DETECT_BITS   _u(0x00000800)
 #define USB_INTF_VBUS_DETECT_MSB    _u(11)
@@ -3499,7 +3499,7 @@
 #define USB_INTS_BUS_RESET_ACCESS "RO"
 // -----------------------------------------------------------------------------
 // Field       : USB_INTS_VBUS_DETECT
-// Description : Source: SIE_STATUS.VBUS_DETECT
+// Description : Source: SIE_STATUS.VBUS_DETECTED
 #define USB_INTS_VBUS_DETECT_RESET  _u(0x0)
 #define USB_INTS_VBUS_DETECT_BITS   _u(0x00000800)
 #define USB_INTS_VBUS_DETECT_MSB    _u(11)
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h b/src/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h
index 6422774c4..fe65ffb1f 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h
@@ -2621,7 +2621,7 @@
 #define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -2756,7 +2756,7 @@
 #define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -2890,7 +2890,7 @@
 #define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -3025,7 +3025,7 @@
 #define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -3159,7 +3159,7 @@
 #define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -3294,7 +3294,7 @@
 #define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -3428,7 +3428,7 @@
 #define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -3563,7 +3563,7 @@
 #define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -3697,7 +3697,7 @@
 #define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -3832,7 +3832,7 @@
 #define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -3966,7 +3966,7 @@
 #define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -4101,7 +4101,7 @@
 #define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -4235,7 +4235,7 @@
 #define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -4370,7 +4370,7 @@
 #define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -4504,7 +4504,7 @@
 #define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -4639,7 +4639,7 @@
 #define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -4773,7 +4773,7 @@
 #define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -4908,7 +4908,7 @@
 #define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -5042,7 +5042,7 @@
 #define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -5177,7 +5177,7 @@
 #define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -5312,7 +5312,7 @@
 #define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -5447,7 +5447,7 @@
 #define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -5582,7 +5582,7 @@
 #define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -5717,7 +5717,7 @@
 #define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -5852,7 +5852,7 @@
 #define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -5987,7 +5987,7 @@
 #define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -6122,7 +6122,7 @@
 #define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -6257,7 +6257,7 @@
 #define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -6392,7 +6392,7 @@
 #define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -6527,7 +6527,7 @@
 #define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -6662,7 +6662,7 @@
 #define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -6797,7 +6797,7 @@
 #define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/xosc.h b/src/rp2040/hardware_regs/include/hardware/regs/xosc.h
index 4af78b956..ec84d3d90 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/xosc.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/xosc.h
@@ -124,20 +124,21 @@
 // Description : Controls the startup delay
 #define XOSC_STARTUP_OFFSET _u(0x0000000c)
 #define XOSC_STARTUP_BITS   _u(0x00103fff)
-#define XOSC_STARTUP_RESET  _u(0x00000000)
+#define XOSC_STARTUP_RESET  _u(0x000000c4)
 // -----------------------------------------------------------------------------
 // Field       : XOSC_STARTUP_X4
 // Description : Multiplies the startup_delay by 4. This is of little value to
-//               the user given that the delay can be programmed directly
-#define XOSC_STARTUP_X4_RESET  "-"
+//               the user given that the delay can be programmed directly.
+#define XOSC_STARTUP_X4_RESET  _u(0x0)
 #define XOSC_STARTUP_X4_BITS   _u(0x00100000)
 #define XOSC_STARTUP_X4_MSB    _u(20)
 #define XOSC_STARTUP_X4_LSB    _u(20)
 #define XOSC_STARTUP_X4_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : XOSC_STARTUP_DELAY
-// Description : in multiples of 256*xtal_period
-#define XOSC_STARTUP_DELAY_RESET  "-"
+// Description : in multiples of 256*xtal_period. The reset value of 0xc4
+//               corresponds to approx 50 000 cycles.
+#define XOSC_STARTUP_DELAY_RESET  _u(0x00c4)
 #define XOSC_STARTUP_DELAY_BITS   _u(0x00003fff)
 #define XOSC_STARTUP_DELAY_MSB    _u(13)
 #define XOSC_STARTUP_DELAY_LSB    _u(0)
diff --git a/src/rp2040/hardware_regs/rp2040.svd b/src/rp2040/hardware_regs/rp2040.svd
index f600d4709..52da2c076 100644
--- a/src/rp2040/hardware_regs/rp2040.svd
+++ b/src/rp2040/hardware_regs/rp2040.svd
@@ -22320,18 +22320,18 @@
             <field>
               <access>read-write</access>
               <bitRange>[20:20]</bitRange>
-              <description>Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly</description>
+              <description>Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly.</description>
               <name>X4</name>
             </field>
             <field>
               <access>read-write</access>
               <bitRange>[13:0]</bitRange>
-              <description>in multiples of 256*xtal_period</description>
+              <description>in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles.</description>
               <name>DELAY</name>
             </field>
           </fields>
           <name>STARTUP</name>
-          <resetValue>0x00000000</resetValue>
+          <resetValue>0x000000c4</resetValue>
         </register>
         <register>
           <addressOffset>0x001c</addressOffset>
@@ -24228,7 +24228,76 @@
         <usage>registers</usage>
       </addressBlock>
       <baseAddress>0x40044000</baseAddress>
-      <description>DW_apb_i2c address block</description>
+      <description>DW_apb_i2c address block\n\n
+        List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):\n\n
+        IC_ULTRA_FAST_MODE ................ 0x0\n
+        IC_UFM_TBUF_CNT_DEFAULT ........... 0x8\n
+        IC_UFM_SCL_LOW_COUNT .............. 0x0008\n
+        IC_UFM_SCL_HIGH_COUNT ............. 0x0006\n
+        IC_TX_TL .......................... 0x0\n
+        IC_TX_CMD_BLOCK ................... 0x1\n
+        IC_HAS_DMA ........................ 0x1\n
+        IC_HAS_ASYNC_FIFO ................. 0x0\n
+        IC_SMBUS_ARP ...................... 0x0\n
+        IC_FIRST_DATA_BYTE_STATUS ......... 0x1\n
+        IC_INTR_IO ........................ 0x1\n
+        IC_MASTER_MODE .................... 0x1\n
+        IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1\n
+        IC_INTR_POL ....................... 0x1\n
+        IC_OPTIONAL_SAR ................... 0x0\n
+        IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055\n
+        IC_DEFAULT_SLAVE_ADDR ............. 0x055\n
+        IC_DEFAULT_HS_SPKLEN .............. 0x1\n
+        IC_FS_SCL_HIGH_COUNT .............. 0x0006\n
+        IC_HS_SCL_LOW_COUNT ............... 0x0008\n
+        IC_DEVICE_ID_VALUE ................ 0x0\n
+        IC_10BITADDR_MASTER ............... 0x0\n
+        IC_CLK_FREQ_OPTIMIZATION .......... 0x0\n
+        IC_DEFAULT_FS_SPKLEN .............. 0x7\n
+        IC_ADD_ENCODED_PARAMS ............. 0x0\n
+        IC_DEFAULT_SDA_HOLD ............... 0x000001\n
+        IC_DEFAULT_SDA_SETUP .............. 0x64\n
+        IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0\n
+        IC_CLOCK_PERIOD ................... 100\n
+        IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1\n
+        IC_RESTART_EN ..................... 0x1\n
+        IC_TX_CMD_BLOCK_DEFAULT ........... 0x0\n
+        IC_BUS_CLEAR_FEATURE .............. 0x0\n
+        IC_CAP_LOADING .................... 100\n
+        IC_FS_SCL_LOW_COUNT ............... 0x000d\n
+        APB_DATA_WIDTH .................... 32\n
+        IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n
+        IC_SLV_DATA_NACK_ONLY ............. 0x1\n
+        IC_10BITADDR_SLAVE ................ 0x0\n
+        IC_CLK_TYPE ....................... 0x0\n
+        IC_SMBUS_UDID_MSB ................. 0x0\n
+        IC_SMBUS_SUSPEND_ALERT ............ 0x0\n
+        IC_HS_SCL_HIGH_COUNT .............. 0x0006\n
+        IC_SLV_RESTART_DET_EN ............. 0x1\n
+        IC_SMBUS .......................... 0x0\n
+        IC_OPTIONAL_SAR_DEFAULT ........... 0x0\n
+        IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0\n
+        IC_USE_COUNTS ..................... 0x0\n
+        IC_RX_BUFFER_DEPTH ................ 16\n
+        IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n
+        IC_RX_FULL_HLD_BUS_EN ............. 0x1\n
+        IC_SLAVE_DISABLE .................. 0x1\n
+        IC_RX_TL .......................... 0x0\n
+        IC_DEVICE_ID ...................... 0x0\n
+        IC_HC_COUNT_VALUES ................ 0x0\n
+        I2C_DYNAMIC_TAR_UPDATE ............ 0\n
+        IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff\n
+        IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff\n
+        IC_HS_MASTER_CODE ................. 0x1\n
+        IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff\n
+        IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff\n
+        IC_SS_SCL_HIGH_COUNT .............. 0x0028\n
+        IC_SS_SCL_LOW_COUNT ............... 0x002f\n
+        IC_MAX_SPEED_MODE ................. 0x2\n
+        IC_STAT_FOR_CLK_STRETCH ........... 0x0\n
+        IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0\n
+        IC_DEFAULT_UFM_SPKLEN ............. 0x1\n
+        IC_TX_BUFFER_DEPTH ................ 16</description>
       <interrupt>
         <name>I2C0_IRQ</name>
         <value>23</value>
@@ -29762,28 +29831,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0010</addressOffset>
           <description>Alias for channel 0 CTRL register</description>
           <name>CH0_AL1_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0014</addressOffset>
           <description>Alias for channel 0 READ_ADDR register</description>
           <name>CH0_AL1_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0018</addressOffset>
           <description>Alias for channel 0 WRITE_ADDR register</description>
           <name>CH0_AL1_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x001c</addressOffset>
           <description>Alias for channel 0 TRANS_COUNT register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -29792,28 +29861,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0020</addressOffset>
           <description>Alias for channel 0 CTRL register</description>
           <name>CH0_AL2_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0024</addressOffset>
           <description>Alias for channel 0 TRANS_COUNT register</description>
           <name>CH0_AL2_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0028</addressOffset>
           <description>Alias for channel 0 READ_ADDR register</description>
           <name>CH0_AL2_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x002c</addressOffset>
           <description>Alias for channel 0 WRITE_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -29822,28 +29891,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0030</addressOffset>
           <description>Alias for channel 0 CTRL register</description>
           <name>CH0_AL3_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0034</addressOffset>
           <description>Alias for channel 0 WRITE_ADDR register</description>
           <name>CH0_AL3_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0038</addressOffset>
           <description>Alias for channel 0 TRANS_COUNT register</description>
           <name>CH0_AL3_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x003c</addressOffset>
           <description>Alias for channel 0 READ_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30047,28 +30116,28 @@
           <resetValue>0x00000800</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0050</addressOffset>
           <description>Alias for channel 1 CTRL register</description>
           <name>CH1_AL1_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0054</addressOffset>
           <description>Alias for channel 1 READ_ADDR register</description>
           <name>CH1_AL1_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0058</addressOffset>
           <description>Alias for channel 1 WRITE_ADDR register</description>
           <name>CH1_AL1_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x005c</addressOffset>
           <description>Alias for channel 1 TRANS_COUNT register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30077,28 +30146,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0060</addressOffset>
           <description>Alias for channel 1 CTRL register</description>
           <name>CH1_AL2_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0064</addressOffset>
           <description>Alias for channel 1 TRANS_COUNT register</description>
           <name>CH1_AL2_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0068</addressOffset>
           <description>Alias for channel 1 READ_ADDR register</description>
           <name>CH1_AL2_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x006c</addressOffset>
           <description>Alias for channel 1 WRITE_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30107,28 +30176,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0070</addressOffset>
           <description>Alias for channel 1 CTRL register</description>
           <name>CH1_AL3_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0074</addressOffset>
           <description>Alias for channel 1 WRITE_ADDR register</description>
           <name>CH1_AL3_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0078</addressOffset>
           <description>Alias for channel 1 TRANS_COUNT register</description>
           <name>CH1_AL3_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x007c</addressOffset>
           <description>Alias for channel 1 READ_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30332,28 +30401,28 @@
           <resetValue>0x00001000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0090</addressOffset>
           <description>Alias for channel 2 CTRL register</description>
           <name>CH2_AL1_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0094</addressOffset>
           <description>Alias for channel 2 READ_ADDR register</description>
           <name>CH2_AL1_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0098</addressOffset>
           <description>Alias for channel 2 WRITE_ADDR register</description>
           <name>CH2_AL1_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x009c</addressOffset>
           <description>Alias for channel 2 TRANS_COUNT register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30362,28 +30431,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x00a0</addressOffset>
           <description>Alias for channel 2 CTRL register</description>
           <name>CH2_AL2_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x00a4</addressOffset>
           <description>Alias for channel 2 TRANS_COUNT register</description>
           <name>CH2_AL2_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x00a8</addressOffset>
           <description>Alias for channel 2 READ_ADDR register</description>
           <name>CH2_AL2_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x00ac</addressOffset>
           <description>Alias for channel 2 WRITE_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30392,28 +30461,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x00b0</addressOffset>
           <description>Alias for channel 2 CTRL register</description>
           <name>CH2_AL3_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x00b4</addressOffset>
           <description>Alias for channel 2 WRITE_ADDR register</description>
           <name>CH2_AL3_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x00b8</addressOffset>
           <description>Alias for channel 2 TRANS_COUNT register</description>
           <name>CH2_AL3_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x00bc</addressOffset>
           <description>Alias for channel 2 READ_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30617,28 +30686,28 @@
           <resetValue>0x00001800</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x00d0</addressOffset>
           <description>Alias for channel 3 CTRL register</description>
           <name>CH3_AL1_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x00d4</addressOffset>
           <description>Alias for channel 3 READ_ADDR register</description>
           <name>CH3_AL1_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x00d8</addressOffset>
           <description>Alias for channel 3 WRITE_ADDR register</description>
           <name>CH3_AL1_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x00dc</addressOffset>
           <description>Alias for channel 3 TRANS_COUNT register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30647,28 +30716,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x00e0</addressOffset>
           <description>Alias for channel 3 CTRL register</description>
           <name>CH3_AL2_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x00e4</addressOffset>
           <description>Alias for channel 3 TRANS_COUNT register</description>
           <name>CH3_AL2_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x00e8</addressOffset>
           <description>Alias for channel 3 READ_ADDR register</description>
           <name>CH3_AL2_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x00ec</addressOffset>
           <description>Alias for channel 3 WRITE_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30677,28 +30746,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x00f0</addressOffset>
           <description>Alias for channel 3 CTRL register</description>
           <name>CH3_AL3_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x00f4</addressOffset>
           <description>Alias for channel 3 WRITE_ADDR register</description>
           <name>CH3_AL3_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x00f8</addressOffset>
           <description>Alias for channel 3 TRANS_COUNT register</description>
           <name>CH3_AL3_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x00fc</addressOffset>
           <description>Alias for channel 3 READ_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30902,28 +30971,28 @@
           <resetValue>0x00002000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0110</addressOffset>
           <description>Alias for channel 4 CTRL register</description>
           <name>CH4_AL1_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0114</addressOffset>
           <description>Alias for channel 4 READ_ADDR register</description>
           <name>CH4_AL1_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0118</addressOffset>
           <description>Alias for channel 4 WRITE_ADDR register</description>
           <name>CH4_AL1_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x011c</addressOffset>
           <description>Alias for channel 4 TRANS_COUNT register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30932,28 +31001,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0120</addressOffset>
           <description>Alias for channel 4 CTRL register</description>
           <name>CH4_AL2_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0124</addressOffset>
           <description>Alias for channel 4 TRANS_COUNT register</description>
           <name>CH4_AL2_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0128</addressOffset>
           <description>Alias for channel 4 READ_ADDR register</description>
           <name>CH4_AL2_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x012c</addressOffset>
           <description>Alias for channel 4 WRITE_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30962,28 +31031,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0130</addressOffset>
           <description>Alias for channel 4 CTRL register</description>
           <name>CH4_AL3_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0134</addressOffset>
           <description>Alias for channel 4 WRITE_ADDR register</description>
           <name>CH4_AL3_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0138</addressOffset>
           <description>Alias for channel 4 TRANS_COUNT register</description>
           <name>CH4_AL3_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x013c</addressOffset>
           <description>Alias for channel 4 READ_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -31187,28 +31256,28 @@
           <resetValue>0x00002800</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0150</addressOffset>
           <description>Alias for channel 5 CTRL register</description>
           <name>CH5_AL1_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0154</addressOffset>
           <description>Alias for channel 5 READ_ADDR register</description>
           <name>CH5_AL1_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0158</addressOffset>
           <description>Alias for channel 5 WRITE_ADDR register</description>
           <name>CH5_AL1_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x015c</addressOffset>
           <description>Alias for channel 5 TRANS_COUNT register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -31217,28 +31286,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0160</addressOffset>
           <description>Alias for channel 5 CTRL register</description>
           <name>CH5_AL2_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0164</addressOffset>
           <description>Alias for channel 5 TRANS_COUNT register</description>
           <name>CH5_AL2_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0168</addressOffset>
           <description>Alias for channel 5 READ_ADDR register</description>
           <name>CH5_AL2_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x016c</addressOffset>
           <description>Alias for channel 5 WRITE_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -31247,28 +31316,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0170</addressOffset>
           <description>Alias for channel 5 CTRL register</description>
           <name>CH5_AL3_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0174</addressOffset>
           <description>Alias for channel 5 WRITE_ADDR register</description>
           <name>CH5_AL3_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0178</addressOffset>
           <description>Alias for channel 5 TRANS_COUNT register</description>
           <name>CH5_AL3_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x017c</addressOffset>
           <description>Alias for channel 5 READ_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -31472,28 +31541,28 @@
           <resetValue>0x00003000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0190</addressOffset>
           <description>Alias for channel 6 CTRL register</description>
           <name>CH6_AL1_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0194</addressOffset>
           <description>Alias for channel 6 READ_ADDR register</description>
           <name>CH6_AL1_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0198</addressOffset>
           <description>Alias for channel 6 WRITE_ADDR register</description>
           <name>CH6_AL1_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x019c</addressOffset>
           <description>Alias for channel 6 TRANS_COUNT register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -31502,28 +31571,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x01a0</addressOffset>
           <description>Alias for channel 6 CTRL register</description>
           <name>CH6_AL2_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x01a4</addressOffset>
           <description>Alias for channel 6 TRANS_COUNT register</description>
           <name>CH6_AL2_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x01a8</addressOffset>
           <description>Alias for channel 6 READ_ADDR register</description>
           <name>CH6_AL2_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x01ac</addressOffset>
           <description>Alias for channel 6 WRITE_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -31532,28 +31601,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x01b0</addressOffset>
           <description>Alias for channel 6 CTRL register</description>
           <name>CH6_AL3_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x01b4</addressOffset>
           <description>Alias for channel 6 WRITE_ADDR register</description>
           <name>CH6_AL3_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x01b8</addressOffset>
           <description>Alias for channel 6 TRANS_COUNT register</description>
           <name>CH6_AL3_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x01bc</addressOffset>
           <description>Alias for channel 6 READ_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -31757,28 +31826,28 @@
           <resetValue>0x00003800</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x01d0</addressOffset>
           <description>Alias for channel 7 CTRL register</description>
           <name>CH7_AL1_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x01d4</addressOffset>
           <description>Alias for channel 7 READ_ADDR register</description>
           <name>CH7_AL1_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x01d8</addressOffset>
           <description>Alias for channel 7 WRITE_ADDR register</description>
           <name>CH7_AL1_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x01dc</addressOffset>
           <description>Alias for channel 7 TRANS_COUNT register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -31787,28 +31856,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x01e0</addressOffset>
           <description>Alias for channel 7 CTRL register</description>
           <name>CH7_AL2_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x01e4</addressOffset>
           <description>Alias for channel 7 TRANS_COUNT register</description>
           <name>CH7_AL2_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x01e8</addressOffset>
           <description>Alias for channel 7 READ_ADDR register</description>
           <name>CH7_AL2_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x01ec</addressOffset>
           <description>Alias for channel 7 WRITE_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -31817,28 +31886,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x01f0</addressOffset>
           <description>Alias for channel 7 CTRL register</description>
           <name>CH7_AL3_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x01f4</addressOffset>
           <description>Alias for channel 7 WRITE_ADDR register</description>
           <name>CH7_AL3_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x01f8</addressOffset>
           <description>Alias for channel 7 TRANS_COUNT register</description>
           <name>CH7_AL3_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x01fc</addressOffset>
           <description>Alias for channel 7 READ_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32042,28 +32111,28 @@
           <resetValue>0x00004000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0210</addressOffset>
           <description>Alias for channel 8 CTRL register</description>
           <name>CH8_AL1_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0214</addressOffset>
           <description>Alias for channel 8 READ_ADDR register</description>
           <name>CH8_AL1_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0218</addressOffset>
           <description>Alias for channel 8 WRITE_ADDR register</description>
           <name>CH8_AL1_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x021c</addressOffset>
           <description>Alias for channel 8 TRANS_COUNT register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32072,28 +32141,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0220</addressOffset>
           <description>Alias for channel 8 CTRL register</description>
           <name>CH8_AL2_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0224</addressOffset>
           <description>Alias for channel 8 TRANS_COUNT register</description>
           <name>CH8_AL2_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0228</addressOffset>
           <description>Alias for channel 8 READ_ADDR register</description>
           <name>CH8_AL2_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x022c</addressOffset>
           <description>Alias for channel 8 WRITE_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32102,28 +32171,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0230</addressOffset>
           <description>Alias for channel 8 CTRL register</description>
           <name>CH8_AL3_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0234</addressOffset>
           <description>Alias for channel 8 WRITE_ADDR register</description>
           <name>CH8_AL3_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0238</addressOffset>
           <description>Alias for channel 8 TRANS_COUNT register</description>
           <name>CH8_AL3_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x023c</addressOffset>
           <description>Alias for channel 8 READ_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32327,28 +32396,28 @@
           <resetValue>0x00004800</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0250</addressOffset>
           <description>Alias for channel 9 CTRL register</description>
           <name>CH9_AL1_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0254</addressOffset>
           <description>Alias for channel 9 READ_ADDR register</description>
           <name>CH9_AL1_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0258</addressOffset>
           <description>Alias for channel 9 WRITE_ADDR register</description>
           <name>CH9_AL1_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x025c</addressOffset>
           <description>Alias for channel 9 TRANS_COUNT register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32357,28 +32426,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0260</addressOffset>
           <description>Alias for channel 9 CTRL register</description>
           <name>CH9_AL2_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0264</addressOffset>
           <description>Alias for channel 9 TRANS_COUNT register</description>
           <name>CH9_AL2_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0268</addressOffset>
           <description>Alias for channel 9 READ_ADDR register</description>
           <name>CH9_AL2_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x026c</addressOffset>
           <description>Alias for channel 9 WRITE_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32387,28 +32456,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0270</addressOffset>
           <description>Alias for channel 9 CTRL register</description>
           <name>CH9_AL3_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0274</addressOffset>
           <description>Alias for channel 9 WRITE_ADDR register</description>
           <name>CH9_AL3_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0278</addressOffset>
           <description>Alias for channel 9 TRANS_COUNT register</description>
           <name>CH9_AL3_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x027c</addressOffset>
           <description>Alias for channel 9 READ_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32612,28 +32681,28 @@
           <resetValue>0x00005000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0290</addressOffset>
           <description>Alias for channel 10 CTRL register</description>
           <name>CH10_AL1_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0294</addressOffset>
           <description>Alias for channel 10 READ_ADDR register</description>
           <name>CH10_AL1_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0298</addressOffset>
           <description>Alias for channel 10 WRITE_ADDR register</description>
           <name>CH10_AL1_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x029c</addressOffset>
           <description>Alias for channel 10 TRANS_COUNT register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32642,28 +32711,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x02a0</addressOffset>
           <description>Alias for channel 10 CTRL register</description>
           <name>CH10_AL2_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x02a4</addressOffset>
           <description>Alias for channel 10 TRANS_COUNT register</description>
           <name>CH10_AL2_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x02a8</addressOffset>
           <description>Alias for channel 10 READ_ADDR register</description>
           <name>CH10_AL2_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x02ac</addressOffset>
           <description>Alias for channel 10 WRITE_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32672,28 +32741,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x02b0</addressOffset>
           <description>Alias for channel 10 CTRL register</description>
           <name>CH10_AL3_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x02b4</addressOffset>
           <description>Alias for channel 10 WRITE_ADDR register</description>
           <name>CH10_AL3_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x02b8</addressOffset>
           <description>Alias for channel 10 TRANS_COUNT register</description>
           <name>CH10_AL3_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x02bc</addressOffset>
           <description>Alias for channel 10 READ_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32897,28 +32966,28 @@
           <resetValue>0x00005800</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x02d0</addressOffset>
           <description>Alias for channel 11 CTRL register</description>
           <name>CH11_AL1_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x02d4</addressOffset>
           <description>Alias for channel 11 READ_ADDR register</description>
           <name>CH11_AL1_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x02d8</addressOffset>
           <description>Alias for channel 11 WRITE_ADDR register</description>
           <name>CH11_AL1_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x02dc</addressOffset>
           <description>Alias for channel 11 TRANS_COUNT register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32927,28 +32996,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x02e0</addressOffset>
           <description>Alias for channel 11 CTRL register</description>
           <name>CH11_AL2_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x02e4</addressOffset>
           <description>Alias for channel 11 TRANS_COUNT register</description>
           <name>CH11_AL2_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x02e8</addressOffset>
           <description>Alias for channel 11 READ_ADDR register</description>
           <name>CH11_AL2_READ_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x02ec</addressOffset>
           <description>Alias for channel 11 WRITE_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32957,28 +33026,28 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x02f0</addressOffset>
           <description>Alias for channel 11 CTRL register</description>
           <name>CH11_AL3_CTRL</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x02f4</addressOffset>
           <description>Alias for channel 11 WRITE_ADDR register</description>
           <name>CH11_AL3_WRITE_ADDR</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x02f8</addressOffset>
           <description>Alias for channel 11 TRANS_COUNT register</description>
           <name>CH11_AL3_TRANS_COUNT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x02fc</addressOffset>
           <description>Alias for channel 11 READ_ADDR register\n
             This is a trigger register (0xc). Writing a nonzero value will\n
@@ -33334,8 +33403,9 @@
           <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
           <fields>
             <field>
-              <access>read-only</access>
+              <access>read-write</access>
               <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
               <name>CH0_DBG_CTDREQ</name>
             </field>
           </fields>
@@ -33354,8 +33424,9 @@
           <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
           <fields>
             <field>
-              <access>read-only</access>
+              <access>read-write</access>
               <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
               <name>CH1_DBG_CTDREQ</name>
             </field>
           </fields>
@@ -33374,8 +33445,9 @@
           <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
           <fields>
             <field>
-              <access>read-only</access>
+              <access>read-write</access>
               <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
               <name>CH2_DBG_CTDREQ</name>
             </field>
           </fields>
@@ -33394,8 +33466,9 @@
           <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
           <fields>
             <field>
-              <access>read-only</access>
+              <access>read-write</access>
               <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
               <name>CH3_DBG_CTDREQ</name>
             </field>
           </fields>
@@ -33414,8 +33487,9 @@
           <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
           <fields>
             <field>
-              <access>read-only</access>
+              <access>read-write</access>
               <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
               <name>CH4_DBG_CTDREQ</name>
             </field>
           </fields>
@@ -33434,8 +33508,9 @@
           <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
           <fields>
             <field>
-              <access>read-only</access>
+              <access>read-write</access>
               <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
               <name>CH5_DBG_CTDREQ</name>
             </field>
           </fields>
@@ -33454,8 +33529,9 @@
           <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
           <fields>
             <field>
-              <access>read-only</access>
+              <access>read-write</access>
               <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
               <name>CH6_DBG_CTDREQ</name>
             </field>
           </fields>
@@ -33474,8 +33550,9 @@
           <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
           <fields>
             <field>
-              <access>read-only</access>
+              <access>read-write</access>
               <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
               <name>CH7_DBG_CTDREQ</name>
             </field>
           </fields>
@@ -33494,8 +33571,9 @@
           <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
           <fields>
             <field>
-              <access>read-only</access>
+              <access>read-write</access>
               <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
               <name>CH8_DBG_CTDREQ</name>
             </field>
           </fields>
@@ -33514,8 +33592,9 @@
           <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
           <fields>
             <field>
-              <access>read-only</access>
+              <access>read-write</access>
               <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
               <name>CH9_DBG_CTDREQ</name>
             </field>
           </fields>
@@ -33534,8 +33613,9 @@
           <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
           <fields>
             <field>
-              <access>read-only</access>
+              <access>read-write</access>
               <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
               <name>CH10_DBG_CTDREQ</name>
             </field>
           </fields>
@@ -33554,8 +33634,9 @@
           <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
           <fields>
             <field>
-              <access>read-only</access>
+              <access>read-write</access>
               <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
               <name>CH11_DBG_CTDREQ</name>
             </field>
           </fields>
@@ -35883,7 +35964,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -35989,7 +36070,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -36095,7 +36176,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -36201,7 +36282,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -36307,7 +36388,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -36413,7 +36494,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -36519,7 +36600,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -36625,7 +36706,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -36731,7 +36812,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -36837,7 +36918,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -36943,7 +37024,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -37049,7 +37130,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -37155,7 +37236,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -37261,7 +37342,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -37367,7 +37448,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -37473,7 +37554,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -37579,7 +37660,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -37685,7 +37766,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -37791,7 +37872,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -37897,7 +37978,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -38003,7 +38084,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -38109,7 +38190,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -38215,7 +38296,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -38321,7 +38402,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -38427,7 +38508,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -38533,7 +38614,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -38639,7 +38720,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -38745,7 +38826,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -38851,7 +38932,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -38957,7 +39038,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -39063,7 +39144,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -39169,7 +39250,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[9:0]</bitRange>
-              <description>The length of the data in buffer 1.</description>
+              <description>The length of the data in buffer 0.</description>
               <name>LENGTH_0</name>
             </field>
           </fields>
@@ -39992,9 +40073,10 @@
               <name>SETUP_REC</name>
             </field>
             <field>
-              <access>read-only</access>
+              <access>read-write</access>
               <bitRange>[16:16]</bitRange>
               <description>Device: connected</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
               <name>CONNECTED</name>
             </field>
             <field>
@@ -40011,15 +40093,17 @@
               <name>VBUS_OVER_CURR</name>
             </field>
             <field>
-              <access>read-only</access>
+              <access>read-write</access>
               <bitRange>[9:8]</bitRange>
               <description>Host: device speed. Disconnected = 00, LS = 01, FS = 10</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
               <name>SPEED</name>
             </field>
             <field>
-              <access>read-only</access>
+              <access>read-write</access>
               <bitRange>[4:4]</bitRange>
               <description>Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
               <name>SUSPENDED</name>
             </field>
             <field>
@@ -41389,7 +41473,7 @@
             <field>
               <access>read-only</access>
               <bitRange>[11:11]</bitRange>
-              <description>Source: SIE_STATUS.VBUS_DETECT</description>
+              <description>Source: SIE_STATUS.VBUS_DETECTED</description>
               <name>VBUS_DETECT</name>
             </field>
             <field>
@@ -41517,7 +41601,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[11:11]</bitRange>
-              <description>Source: SIE_STATUS.VBUS_DETECT</description>
+              <description>Source: SIE_STATUS.VBUS_DETECTED</description>
               <name>VBUS_DETECT</name>
             </field>
             <field>
@@ -41645,7 +41729,7 @@
             <field>
               <access>read-write</access>
               <bitRange>[11:11]</bitRange>
-              <description>Source: SIE_STATUS.VBUS_DETECT</description>
+              <description>Source: SIE_STATUS.VBUS_DETECTED</description>
               <name>VBUS_DETECT</name>
             </field>
             <field>
@@ -41773,7 +41857,7 @@
             <field>
               <access>read-only</access>
               <bitRange>[11:11]</bitRange>
-              <description>Source: SIE_STATUS.VBUS_DETECT</description>
+              <description>Source: SIE_STATUS.VBUS_DETECTED</description>
               <name>VBUS_DETECT</name>
             </field>
             <field>
@@ -42112,14 +42196,14 @@
         <register>
           <access>read-only</access>
           <addressOffset>0x003c</addressOffset>
-          <description>Read to sample the pad output values PIO is currently driving to the GPIOs.</description>
+          <description>Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.</description>
           <name>DBG_PADOUT</name>
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
           <access>read-only</access>
           <addressOffset>0x0040</addressOffset>
-          <description>Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs.</description>
+          <description>Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.</description>
           <name>DBG_PADOE</name>
           <resetValue>0x00000000</resetValue>
         </register>
@@ -42157,7 +42241,7 @@
           <description>Write-only access to instruction memory location 0</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM0</name>
             </field>
@@ -42170,7 +42254,7 @@
           <description>Write-only access to instruction memory location 1</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM1</name>
             </field>
@@ -42183,7 +42267,7 @@
           <description>Write-only access to instruction memory location 2</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM2</name>
             </field>
@@ -42196,7 +42280,7 @@
           <description>Write-only access to instruction memory location 3</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM3</name>
             </field>
@@ -42209,7 +42293,7 @@
           <description>Write-only access to instruction memory location 4</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM4</name>
             </field>
@@ -42222,7 +42306,7 @@
           <description>Write-only access to instruction memory location 5</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM5</name>
             </field>
@@ -42235,7 +42319,7 @@
           <description>Write-only access to instruction memory location 6</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM6</name>
             </field>
@@ -42248,7 +42332,7 @@
           <description>Write-only access to instruction memory location 7</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM7</name>
             </field>
@@ -42261,7 +42345,7 @@
           <description>Write-only access to instruction memory location 8</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM8</name>
             </field>
@@ -42274,7 +42358,7 @@
           <description>Write-only access to instruction memory location 9</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM9</name>
             </field>
@@ -42287,7 +42371,7 @@
           <description>Write-only access to instruction memory location 10</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM10</name>
             </field>
@@ -42300,7 +42384,7 @@
           <description>Write-only access to instruction memory location 11</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM11</name>
             </field>
@@ -42313,7 +42397,7 @@
           <description>Write-only access to instruction memory location 12</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM12</name>
             </field>
@@ -42326,7 +42410,7 @@
           <description>Write-only access to instruction memory location 13</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM13</name>
             </field>
@@ -42339,7 +42423,7 @@
           <description>Write-only access to instruction memory location 14</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM14</name>
             </field>
@@ -42352,7 +42436,7 @@
           <description>Write-only access to instruction memory location 15</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM15</name>
             </field>
@@ -42365,7 +42449,7 @@
           <description>Write-only access to instruction memory location 16</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM16</name>
             </field>
@@ -42378,7 +42462,7 @@
           <description>Write-only access to instruction memory location 17</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM17</name>
             </field>
@@ -42391,7 +42475,7 @@
           <description>Write-only access to instruction memory location 18</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM18</name>
             </field>
@@ -42404,7 +42488,7 @@
           <description>Write-only access to instruction memory location 19</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM19</name>
             </field>
@@ -42417,7 +42501,7 @@
           <description>Write-only access to instruction memory location 20</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM20</name>
             </field>
@@ -42430,7 +42514,7 @@
           <description>Write-only access to instruction memory location 21</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM21</name>
             </field>
@@ -42443,7 +42527,7 @@
           <description>Write-only access to instruction memory location 22</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM22</name>
             </field>
@@ -42456,7 +42540,7 @@
           <description>Write-only access to instruction memory location 23</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM23</name>
             </field>
@@ -42469,7 +42553,7 @@
           <description>Write-only access to instruction memory location 24</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM24</name>
             </field>
@@ -42482,7 +42566,7 @@
           <description>Write-only access to instruction memory location 25</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM25</name>
             </field>
@@ -42495,7 +42579,7 @@
           <description>Write-only access to instruction memory location 26</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM26</name>
             </field>
@@ -42508,7 +42592,7 @@
           <description>Write-only access to instruction memory location 27</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM27</name>
             </field>
@@ -42521,7 +42605,7 @@
           <description>Write-only access to instruction memory location 28</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM28</name>
             </field>
@@ -42534,7 +42618,7 @@
           <description>Write-only access to instruction memory location 29</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM29</name>
             </field>
@@ -42547,7 +42631,7 @@
           <description>Write-only access to instruction memory location 30</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM30</name>
             </field>
@@ -42560,7 +42644,7 @@
           <description>Write-only access to instruction memory location 31</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[15:0]</bitRange>
               <name>INSTR_MEM31</name>
             </field>
@@ -44142,7 +44226,7 @@
           <description>GPIO output value set</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[29:0]</bitRange>
               <description>Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`</description>
               <name>GPIO_OUT_SET</name>
@@ -44156,7 +44240,7 @@
           <description>GPIO output value clear</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[29:0]</bitRange>
               <description>Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &amp;= ~wdata`</description>
               <name>GPIO_OUT_CLR</name>
@@ -44170,7 +44254,7 @@
           <description>GPIO output value XOR</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[29:0]</bitRange>
               <description>Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata`</description>
               <name>GPIO_OUT_XOR</name>
@@ -44202,7 +44286,7 @@
           <description>GPIO output enable set</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[29:0]</bitRange>
               <description>Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`</description>
               <name>GPIO_OE_SET</name>
@@ -44216,7 +44300,7 @@
           <description>GPIO output enable clear</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[29:0]</bitRange>
               <description>Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &amp;= ~wdata`</description>
               <name>GPIO_OE_CLR</name>
@@ -44230,7 +44314,7 @@
           <description>GPIO output enable XOR</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[29:0]</bitRange>
               <description>Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata`</description>
               <name>GPIO_OE_XOR</name>
@@ -44262,7 +44346,7 @@
           <description>QSPI output value set</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[5:0]</bitRange>
               <description>Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata`</description>
               <name>GPIO_HI_OUT_SET</name>
@@ -44276,7 +44360,7 @@
           <description>QSPI output value clear</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[5:0]</bitRange>
               <description>Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &amp;= ~wdata`</description>
               <name>GPIO_HI_OUT_CLR</name>
@@ -44290,7 +44374,7 @@
           <description>QSPI output value XOR</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[5:0]</bitRange>
               <description>Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata`</description>
               <name>GPIO_HI_OUT_XOR</name>
@@ -44322,7 +44406,7 @@
           <description>QSPI output enable set</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[5:0]</bitRange>
               <description>Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata`</description>
               <name>GPIO_HI_OE_SET</name>
@@ -44336,7 +44420,7 @@
           <description>QSPI output enable clear</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[5:0]</bitRange>
               <description>Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &amp;= ~wdata`</description>
               <name>GPIO_HI_OE_CLR</name>
@@ -44350,7 +44434,7 @@
           <description>QSPI output enable XOR</description>
           <fields>
             <field>
-              <access>read-write</access>
+              <access>write-only</access>
               <bitRange>[5:0]</bitRange>
               <description>Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata`</description>
               <name>GPIO_HI_OE_XOR</name>
@@ -44767,7 +44851,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-write</access>
+          <access>write-only</access>
           <addressOffset>0x00bc</addressOffset>
           <description>On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n
             Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.</description>
@@ -45029,7 +45113,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-write</access>
+          <access>write-only</access>
           <addressOffset>0x00fc</addressOffset>
           <description>On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n
             Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.</description>
@@ -45037,7 +45121,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0100</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45049,7 +45133,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0104</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45061,7 +45145,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0108</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45073,7 +45157,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x010c</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45085,7 +45169,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0110</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45097,7 +45181,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0114</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45109,7 +45193,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0118</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45121,7 +45205,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x011c</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45133,7 +45217,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0120</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45145,7 +45229,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0124</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45157,7 +45241,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0128</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45169,7 +45253,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x012c</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45181,7 +45265,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0130</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45193,7 +45277,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0134</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45205,7 +45289,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0138</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45217,7 +45301,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x013c</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45229,7 +45313,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0140</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45241,7 +45325,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0144</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45253,7 +45337,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0148</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45265,7 +45349,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x014c</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45277,7 +45361,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0150</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45289,7 +45373,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0154</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45301,7 +45385,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0158</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45313,7 +45397,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x015c</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45325,7 +45409,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0160</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45337,7 +45421,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0164</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45349,7 +45433,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0168</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45361,7 +45445,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x016c</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45373,7 +45457,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0170</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45385,7 +45469,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0174</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45397,7 +45481,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x0178</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
@@ -45409,7 +45493,7 @@
           <resetValue>0x00000000</resetValue>
         </register>
         <register>
-          <access>read-only</access>
+          <access>read-write</access>
           <addressOffset>0x017c</addressOffset>
           <description>Reading from a spinlock address will:\n
             - Return 0 if lock is already locked\n
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/adc.h b/src/rp2040/hardware_structs/include/hardware/structs/adc.h
index 559b5f177..c47e9d453 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/adc.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/adc.h
@@ -1,27 +1,90 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
+
 #ifndef _HARDWARE_STRUCTS_ADC_H
 #define _HARDWARE_STRUCTS_ADC_H
 
 #include "hardware/address_mapped.h"
 #include "hardware/regs/adc.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_adc
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/adc.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(ADC_CS_OFFSET) // ADC_CS
+    // ADC Control and Status
+    // 0x001f0000 [20:16] : RROBIN (0): Round-robin sampling
+    // 0x00007000 [14:12] : AINSEL (0): Select analog mux input
+    // 0x00000400 [10]    : ERR_STICKY (0): Some past ADC conversion encountered an error
+    // 0x00000200 [9]     : ERR (0): The most recent ADC conversion encountered an error; result is undefined or noisy
+    // 0x00000100 [8]     : READY (0): 1 if the ADC is ready to start a new conversion
+    // 0x00000008 [3]     : START_MANY (0): Continuously perform conversions whilst this bit is 1
+    // 0x00000004 [2]     : START_ONCE (0): Start a single conversion
+    // 0x00000002 [1]     : TS_EN (0): Power on temperature sensor
+    // 0x00000001 [0]     : EN (0): Power on ADC and enable its clock
     io_rw_32 cs;
-    io_rw_32 result;
+
+    _REG_(ADC_RESULT_OFFSET) // ADC_RESULT
+    // Result of most recent ADC conversion
+    // 0x00000fff [11:0]  : RESULT (0)
+    io_ro_32 result;
+
+    _REG_(ADC_FCS_OFFSET) // ADC_FCS
+    // FIFO control and status
+    // 0x0f000000 [27:24] : THRESH (0): DREQ/IRQ asserted when level >= threshold
+    // 0x000f0000 [19:16] : LEVEL (0): The number of conversion results currently waiting in the FIFO
+    // 0x00000800 [11]    : OVER (0): 1 if the FIFO has been overflowed
+    // 0x00000400 [10]    : UNDER (0): 1 if the FIFO has been underflowed
+    // 0x00000200 [9]     : FULL (0)
+    // 0x00000100 [8]     : EMPTY (0)
+    // 0x00000008 [3]     : DREQ_EN (0): If 1: assert DMA requests when FIFO contains data
+    // 0x00000004 [2]     : ERR (0): If 1: conversion error bit appears in the FIFO alongside the result
+    // 0x00000002 [1]     : SHIFT (0): If 1: FIFO results are right-shifted to be one byte in size
+    // 0x00000001 [0]     : EN (0): If 1: write result to the FIFO after each conversion
     io_rw_32 fcs;
-    io_rw_32 fifo;
+
+    _REG_(ADC_FIFO_OFFSET) // ADC_FIFO
+    // Conversion result FIFO
+    // 0x00008000 [15]    : ERR (0): 1 if this particular sample experienced a conversion error
+    // 0x00000fff [11:0]  : VAL (0)
+    io_ro_32 fifo;
+
+    _REG_(ADC_DIV_OFFSET) // ADC_DIV
+    // Clock divider
+    // 0x00ffff00 [23:8]  : INT (0): Integer part of clock divisor
+    // 0x000000ff [7:0]   : FRAC (0): Fractional part of clock divisor
     io_rw_32 div;
-    io_rw_32 intr;
+
+    _REG_(ADC_INTR_OFFSET) // ADC_INTR
+    // Raw Interrupts
+    // 0x00000001 [0]     : FIFO (0): Triggered when the sample FIFO reaches a certain level
+    io_ro_32 intr;
+
+    _REG_(ADC_INTE_OFFSET) // ADC_INTE
+    // Interrupt Enable
+    // 0x00000001 [0]     : FIFO (0): Triggered when the sample FIFO reaches a certain level
     io_rw_32 inte;
+
+    _REG_(ADC_INTF_OFFSET) // ADC_INTF
+    // Interrupt Force
+    // 0x00000001 [0]     : FIFO (0): Triggered when the sample FIFO reaches a certain level
     io_rw_32 intf;
-    io_rw_32 ints;
-} adc_hw_t;
 
-check_hw_layout(adc_hw_t, ints, ADC_INTS_OFFSET);
+    _REG_(ADC_INTS_OFFSET) // ADC_INTS
+    // Interrupt status after masking & forcing
+    // 0x00000001 [0]     : FIFO (0): Triggered when the sample FIFO reaches a certain level
+    io_ro_32 ints;
+} adc_hw_t;
 
 #define adc_hw ((adc_hw_t *const)ADC_BASE)
 
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h b/src/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h
index ce95a7c19..81118a8f3 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h
@@ -1,14 +1,25 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
+
 #ifndef _HARDWARE_STRUCTS_BUS_CTRL_H
 #define _HARDWARE_STRUCTS_BUS_CTRL_H
 
 #include "hardware/address_mapped.h"
 #include "hardware/regs/busctrl.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_busctrl
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 enum bus_ctrl_perf_counter {
     arbiter_rom_perf_event_access = 19,
     arbiter_rom_perf_event_access_contested = 18,
@@ -33,15 +44,33 @@ enum bus_ctrl_perf_counter {
 };
 
 typedef struct {
+    _REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0
+    // Bus fabric performance counter 0
+    // 0x00ffffff [23:0]  : PERFCTR0 (0): Busfabric saturating performance counter 0
+    io_rw_32 value;
+
+    _REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0
+    // Bus fabric performance event select for PERFCTR0
+    // 0x0000001f [4:0]   : PERFSEL0 (0x1f): Select an event for PERFCTR0
+    io_rw_32 sel;
+} bus_ctrl_perf_hw_t;
+
+typedef struct {
+    _REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY
+    // Set the priority of each master for bus arbitration
+    // 0x00001000 [12]    : DMA_W (0): 0 - low priority, 1 - high priority
+    // 0x00000100 [8]     : DMA_R (0): 0 - low priority, 1 - high priority
+    // 0x00000010 [4]     : PROC1 (0): 0 - low priority, 1 - high priority
+    // 0x00000001 [0]     : PROC0 (0): 0 - low priority, 1 - high priority
     io_rw_32 priority;
+
+    _REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK
+    // Bus priority acknowledge
+    // 0x00000001 [0]     : BUS_PRIORITY_ACK (0): Goes to 1 once all arbiters have registered the new global priority levels
     io_ro_32 priority_ack;
-    struct {
-        io_rw_32 value;
-        io_rw_32 sel;
-    } counter[4];
-} bus_ctrl_hw_t;
 
-check_hw_layout(bus_ctrl_hw_t, counter[0].value, BUSCTRL_PERFCTR0_OFFSET);
+    bus_ctrl_perf_hw_t counter[4];
+} bus_ctrl_hw_t;
 
 #define bus_ctrl_hw ((bus_ctrl_hw_t *const)BUSCTRL_BASE)
 
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/clocks.h b/src/rp2040/hardware_structs/include/hardware/structs/clocks.h
index 489876d16..a245dbd48 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/clocks.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/clocks.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,9 +10,16 @@
 #define _HARDWARE_STRUCTS_CLOCKS_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/clocks.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_clocks
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 /*! \brief Enumeration identifying a hardware clock
  *  \ingroup hardware_clocks
  */
@@ -32,41 +41,286 @@ enum clock_index {
 
 /// \tag::clock_hw[]
 typedef struct {
+    _REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL
+    // Clock control, can be changed on-the-fly (except for auxsrc)
+    // 0x00100000 [20]    : NUDGE (0): An edge on this signal shifts the phase of the output by 1 cycle of the input clock
+    // 0x00030000 [17:16] : PHASE (0): This delays the enable signal by up to 3 cycles of the input clock
+    // 0x00001000 [12]    : DC50 (0): Enables duty cycle correction for odd divisors
+    // 0x00000800 [11]    : ENABLE (0): Starts and stops the clock generator cleanly
+    // 0x00000400 [10]    : KILL (0): Asynchronously kills the clock generator
+    // 0x000001e0 [8:5]   : AUXSRC (0): Selects the auxiliary clock source, will glitch when switching
     io_rw_32 ctrl;
+
+    _REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV
+    // Clock divisor, can be changed on-the-fly
+    // 0xffffff00 [31:8]  : INT (1): Integer component of the divisor, 0 -> divide by 2^16
+    // 0x000000ff [7:0]   : FRAC (0): Fractional component of the divisor
     io_rw_32 div;
-    io_rw_32 selected;
+
+    _REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED
+    // Indicates which SRC is currently selected by the glitchless mux (one-hot)
+    io_ro_32 selected;
 } clock_hw_t;
 /// \end::clock_hw[]
 
 typedef struct {
+    _REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL
+    // 0x00010000 [16]    : CLEAR (0): For clearing the resus after the fault that triggered it has been corrected
+    // 0x00001000 [12]    : FRCE (0): Force a resus, for test purposes only
+    // 0x00000100 [8]     : ENABLE (0): Enable resus
+    // 0x000000ff [7:0]   : TIMEOUT (0xff): This is expressed as a number of clk_ref cycles
+    io_rw_32 ctrl;
+
+    _REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS
+    // 0x00000001 [0]     : RESUSSED (0): Clock has been resuscitated, correct the error then send ctrl_clear=1
+    io_ro_32 status;
+} clock_resus_hw_t;
+
+typedef struct {
+    _REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ
+    // Reference clock frequency in kHz
+    // 0x000fffff [19:0]  : FC0_REF_KHZ (0)
     io_rw_32 ref_khz;
+
+    _REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ
+    // Minimum pass frequency in kHz
+    // 0x01ffffff [24:0]  : FC0_MIN_KHZ (0)
     io_rw_32 min_khz;
+
+    _REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ
+    // Maximum pass frequency in kHz
+    // 0x01ffffff [24:0]  : FC0_MAX_KHZ (0x1ffffff)
     io_rw_32 max_khz;
+
+    _REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY
+    // Delays the start of frequency counting to allow the mux to settle
+    // 0x00000007 [2:0]   : FC0_DELAY (1)
     io_rw_32 delay;
+
+    _REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL
+    // The test interval is 0
+    // 0x0000000f [3:0]   : FC0_INTERVAL (0x8)
     io_rw_32 interval;
+
+    _REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC
+    // Clock sent to frequency counter, set to 0 when not required
+    // 0x000000ff [7:0]   : FC0_SRC (0)
     io_rw_32 src;
+
+    _REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS
+    // Frequency counter status
+    // 0x10000000 [28]    : DIED (0): Test clock stopped during test
+    // 0x01000000 [24]    : FAST (0): Test clock faster than expected, only valid when status_done=1
+    // 0x00100000 [20]    : SLOW (0): Test clock slower than expected, only valid when status_done=1
+    // 0x00010000 [16]    : FAIL (0): Test failed
+    // 0x00001000 [12]    : WAITING (0): Waiting for test clock to start
+    // 0x00000100 [8]     : RUNNING (0): Test running
+    // 0x00000010 [4]     : DONE (0): Test complete
+    // 0x00000001 [0]     : PASS (0): Test passed
     io_ro_32 status;
+
+    _REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT
+    // Result of frequency measurement, only valid when status_done=1
+    // 0x3fffffe0 [29:5]  : KHZ (0)
+    // 0x0000001f [4:0]   : FRAC (0)
     io_ro_32 result;
 } fc_hw_t;
 
 typedef struct {
-    clock_hw_t clk[CLK_COUNT];
-    struct {
-        io_rw_32 ctrl;
-        io_rw_32 status;
-    } resus;
+    clock_hw_t clk[CLK_COUNT]; // 10
+
+    clock_resus_hw_t resus;
+
     fc_hw_t fc0;
+
+    _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0
+    // enable clock in wake mode
+    // 0x80000000 [31]    : clk_sys_sram3 (1)
+    // 0x40000000 [30]    : clk_sys_sram2 (1)
+    // 0x20000000 [29]    : clk_sys_sram1 (1)
+    // 0x10000000 [28]    : clk_sys_sram0 (1)
+    // 0x08000000 [27]    : clk_sys_spi1 (1)
+    // 0x04000000 [26]    : clk_peri_spi1 (1)
+    // 0x02000000 [25]    : clk_sys_spi0 (1)
+    // 0x01000000 [24]    : clk_peri_spi0 (1)
+    // 0x00800000 [23]    : clk_sys_sio (1)
+    // 0x00400000 [22]    : clk_sys_rtc (1)
+    // 0x00200000 [21]    : clk_rtc_rtc (1)
+    // 0x00100000 [20]    : clk_sys_rosc (1)
+    // 0x00080000 [19]    : clk_sys_rom (1)
+    // 0x00040000 [18]    : clk_sys_resets (1)
+    // 0x00020000 [17]    : clk_sys_pwm (1)
+    // 0x00010000 [16]    : clk_sys_psm (1)
+    // 0x00008000 [15]    : clk_sys_pll_usb (1)
+    // 0x00004000 [14]    : clk_sys_pll_sys (1)
+    // 0x00002000 [13]    : clk_sys_pio1 (1)
+    // 0x00001000 [12]    : clk_sys_pio0 (1)
+    // 0x00000800 [11]    : clk_sys_pads (1)
+    // 0x00000400 [10]    : clk_sys_vreg_and_chip_reset (1)
+    // 0x00000200 [9]     : clk_sys_jtag (1)
+    // 0x00000100 [8]     : clk_sys_io (1)
+    // 0x00000080 [7]     : clk_sys_i2c1 (1)
+    // 0x00000040 [6]     : clk_sys_i2c0 (1)
+    // 0x00000020 [5]     : clk_sys_dma (1)
+    // 0x00000010 [4]     : clk_sys_busfabric (1)
+    // 0x00000008 [3]     : clk_sys_busctrl (1)
+    // 0x00000004 [2]     : clk_sys_adc (1)
+    // 0x00000002 [1]     : clk_adc_adc (1)
+    // 0x00000001 [0]     : clk_sys_clocks (1)
     io_rw_32 wake_en0;
+
+    _REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1
+    // enable clock in wake mode
+    // 0x00004000 [14]    : clk_sys_xosc (1)
+    // 0x00002000 [13]    : clk_sys_xip (1)
+    // 0x00001000 [12]    : clk_sys_watchdog (1)
+    // 0x00000800 [11]    : clk_usb_usbctrl (1)
+    // 0x00000400 [10]    : clk_sys_usbctrl (1)
+    // 0x00000200 [9]     : clk_sys_uart1 (1)
+    // 0x00000100 [8]     : clk_peri_uart1 (1)
+    // 0x00000080 [7]     : clk_sys_uart0 (1)
+    // 0x00000040 [6]     : clk_peri_uart0 (1)
+    // 0x00000020 [5]     : clk_sys_timer (1)
+    // 0x00000010 [4]     : clk_sys_tbman (1)
+    // 0x00000008 [3]     : clk_sys_sysinfo (1)
+    // 0x00000004 [2]     : clk_sys_syscfg (1)
+    // 0x00000002 [1]     : clk_sys_sram5 (1)
+    // 0x00000001 [0]     : clk_sys_sram4 (1)
     io_rw_32 wake_en1;
+
+    _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0
+    // enable clock in sleep mode
+    // 0x80000000 [31]    : clk_sys_sram3 (1)
+    // 0x40000000 [30]    : clk_sys_sram2 (1)
+    // 0x20000000 [29]    : clk_sys_sram1 (1)
+    // 0x10000000 [28]    : clk_sys_sram0 (1)
+    // 0x08000000 [27]    : clk_sys_spi1 (1)
+    // 0x04000000 [26]    : clk_peri_spi1 (1)
+    // 0x02000000 [25]    : clk_sys_spi0 (1)
+    // 0x01000000 [24]    : clk_peri_spi0 (1)
+    // 0x00800000 [23]    : clk_sys_sio (1)
+    // 0x00400000 [22]    : clk_sys_rtc (1)
+    // 0x00200000 [21]    : clk_rtc_rtc (1)
+    // 0x00100000 [20]    : clk_sys_rosc (1)
+    // 0x00080000 [19]    : clk_sys_rom (1)
+    // 0x00040000 [18]    : clk_sys_resets (1)
+    // 0x00020000 [17]    : clk_sys_pwm (1)
+    // 0x00010000 [16]    : clk_sys_psm (1)
+    // 0x00008000 [15]    : clk_sys_pll_usb (1)
+    // 0x00004000 [14]    : clk_sys_pll_sys (1)
+    // 0x00002000 [13]    : clk_sys_pio1 (1)
+    // 0x00001000 [12]    : clk_sys_pio0 (1)
+    // 0x00000800 [11]    : clk_sys_pads (1)
+    // 0x00000400 [10]    : clk_sys_vreg_and_chip_reset (1)
+    // 0x00000200 [9]     : clk_sys_jtag (1)
+    // 0x00000100 [8]     : clk_sys_io (1)
+    // 0x00000080 [7]     : clk_sys_i2c1 (1)
+    // 0x00000040 [6]     : clk_sys_i2c0 (1)
+    // 0x00000020 [5]     : clk_sys_dma (1)
+    // 0x00000010 [4]     : clk_sys_busfabric (1)
+    // 0x00000008 [3]     : clk_sys_busctrl (1)
+    // 0x00000004 [2]     : clk_sys_adc (1)
+    // 0x00000002 [1]     : clk_adc_adc (1)
+    // 0x00000001 [0]     : clk_sys_clocks (1)
     io_rw_32 sleep_en0;
+
+    _REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1
+    // enable clock in sleep mode
+    // 0x00004000 [14]    : clk_sys_xosc (1)
+    // 0x00002000 [13]    : clk_sys_xip (1)
+    // 0x00001000 [12]    : clk_sys_watchdog (1)
+    // 0x00000800 [11]    : clk_usb_usbctrl (1)
+    // 0x00000400 [10]    : clk_sys_usbctrl (1)
+    // 0x00000200 [9]     : clk_sys_uart1 (1)
+    // 0x00000100 [8]     : clk_peri_uart1 (1)
+    // 0x00000080 [7]     : clk_sys_uart0 (1)
+    // 0x00000040 [6]     : clk_peri_uart0 (1)
+    // 0x00000020 [5]     : clk_sys_timer (1)
+    // 0x00000010 [4]     : clk_sys_tbman (1)
+    // 0x00000008 [3]     : clk_sys_sysinfo (1)
+    // 0x00000004 [2]     : clk_sys_syscfg (1)
+    // 0x00000002 [1]     : clk_sys_sram5 (1)
+    // 0x00000001 [0]     : clk_sys_sram4 (1)
     io_rw_32 sleep_en1;
-    io_rw_32 enabled0;
-    io_rw_32 enabled1;
-    io_rw_32 intr;
+
+    _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0
+    // indicates the state of the clock enable
+    // 0x80000000 [31]    : clk_sys_sram3 (0)
+    // 0x40000000 [30]    : clk_sys_sram2 (0)
+    // 0x20000000 [29]    : clk_sys_sram1 (0)
+    // 0x10000000 [28]    : clk_sys_sram0 (0)
+    // 0x08000000 [27]    : clk_sys_spi1 (0)
+    // 0x04000000 [26]    : clk_peri_spi1 (0)
+    // 0x02000000 [25]    : clk_sys_spi0 (0)
+    // 0x01000000 [24]    : clk_peri_spi0 (0)
+    // 0x00800000 [23]    : clk_sys_sio (0)
+    // 0x00400000 [22]    : clk_sys_rtc (0)
+    // 0x00200000 [21]    : clk_rtc_rtc (0)
+    // 0x00100000 [20]    : clk_sys_rosc (0)
+    // 0x00080000 [19]    : clk_sys_rom (0)
+    // 0x00040000 [18]    : clk_sys_resets (0)
+    // 0x00020000 [17]    : clk_sys_pwm (0)
+    // 0x00010000 [16]    : clk_sys_psm (0)
+    // 0x00008000 [15]    : clk_sys_pll_usb (0)
+    // 0x00004000 [14]    : clk_sys_pll_sys (0)
+    // 0x00002000 [13]    : clk_sys_pio1 (0)
+    // 0x00001000 [12]    : clk_sys_pio0 (0)
+    // 0x00000800 [11]    : clk_sys_pads (0)
+    // 0x00000400 [10]    : clk_sys_vreg_and_chip_reset (0)
+    // 0x00000200 [9]     : clk_sys_jtag (0)
+    // 0x00000100 [8]     : clk_sys_io (0)
+    // 0x00000080 [7]     : clk_sys_i2c1 (0)
+    // 0x00000040 [6]     : clk_sys_i2c0 (0)
+    // 0x00000020 [5]     : clk_sys_dma (0)
+    // 0x00000010 [4]     : clk_sys_busfabric (0)
+    // 0x00000008 [3]     : clk_sys_busctrl (0)
+    // 0x00000004 [2]     : clk_sys_adc (0)
+    // 0x00000002 [1]     : clk_adc_adc (0)
+    // 0x00000001 [0]     : clk_sys_clocks (0)
+    io_ro_32 enabled0;
+
+    _REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1
+    // indicates the state of the clock enable
+    // 0x00004000 [14]    : clk_sys_xosc (0)
+    // 0x00002000 [13]    : clk_sys_xip (0)
+    // 0x00001000 [12]    : clk_sys_watchdog (0)
+    // 0x00000800 [11]    : clk_usb_usbctrl (0)
+    // 0x00000400 [10]    : clk_sys_usbctrl (0)
+    // 0x00000200 [9]     : clk_sys_uart1 (0)
+    // 0x00000100 [8]     : clk_peri_uart1 (0)
+    // 0x00000080 [7]     : clk_sys_uart0 (0)
+    // 0x00000040 [6]     : clk_peri_uart0 (0)
+    // 0x00000020 [5]     : clk_sys_timer (0)
+    // 0x00000010 [4]     : clk_sys_tbman (0)
+    // 0x00000008 [3]     : clk_sys_sysinfo (0)
+    // 0x00000004 [2]     : clk_sys_syscfg (0)
+    // 0x00000002 [1]     : clk_sys_sram5 (0)
+    // 0x00000001 [0]     : clk_sys_sram4 (0)
+    io_ro_32 enabled1;
+
+    _REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR
+    // Raw Interrupts
+    // 0x00000001 [0]     : CLK_SYS_RESUS (0)
+    io_ro_32 intr;
+
+    _REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE
+    // Interrupt Enable
+    // 0x00000001 [0]     : CLK_SYS_RESUS (0)
     io_rw_32 inte;
+
+    _REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF
+    // Interrupt Force
+    // 0x00000001 [0]     : CLK_SYS_RESUS (0)
     io_rw_32 intf;
-    io_rw_32 ints;
+
+    _REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS
+    // Interrupt status after masking & forcing
+    // 0x00000001 [0]     : CLK_SYS_RESUS (0)
+    io_ro_32 ints;
 } clocks_hw_t;
 
 #define clocks_hw ((clocks_hw_t *const)CLOCKS_BASE)
+
+static_assert( CLK_COUNT == 10, "");
+
 #endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/dma.h b/src/rp2040/hardware_structs/include/hardware/structs/dma.h
index 06cdf7927..0d206416a 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/dma.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/dma.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,51 +10,185 @@
 #define _HARDWARE_STRUCTS_DMA_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/dma.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/dma.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR
+    // DMA Channel 0 Read Address pointer
     io_rw_32 read_addr;
+
+    _REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR
+    // DMA Channel 0 Write Address pointer
     io_rw_32 write_addr;
+
+    _REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT
+    // DMA Channel 0 Transfer Count
     io_rw_32 transfer_count;
+
+    _REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG
+    // DMA Channel 0 Control and Status
+    // 0x80000000 [31]    : AHB_ERROR (0): Logical OR of the READ_ERROR and WRITE_ERROR flags
+    // 0x40000000 [30]    : READ_ERROR (0): If 1, the channel received a read bus error
+    // 0x20000000 [29]    : WRITE_ERROR (0): If 1, the channel received a write bus error
+    // 0x01000000 [24]    : BUSY (0): This flag goes high when the channel starts a new transfer sequence, and low when the...
+    // 0x00800000 [23]    : SNIFF_EN (0): If 1, this channel's data transfers are visible to the sniff hardware, and each...
+    // 0x00400000 [22]    : BSWAP (0): Apply byte-swap transformation to DMA data
+    // 0x00200000 [21]    : IRQ_QUIET (0): In QUIET mode, the channel does not generate IRQs at the end of every transfer block
+    // 0x001f8000 [20:15] : TREQ_SEL (0): Select a Transfer Request signal
+    // 0x00007800 [14:11] : CHAIN_TO (0): When this channel completes, it will trigger the channel indicated by CHAIN_TO
+    // 0x00000400 [10]    : RING_SEL (0): Select whether RING_SIZE applies to read or write addresses
+    // 0x000003c0 [9:6]   : RING_SIZE (0): Size of address wrap region
+    // 0x00000020 [5]     : INCR_WRITE (0): If 1, the write address increments with each transfer
+    // 0x00000010 [4]     : INCR_READ (0): If 1, the read address increments with each transfer
+    // 0x0000000c [3:2]   : DATA_SIZE (0): Set the size of each bus transfer (byte/halfword/word)
+    // 0x00000002 [1]     : HIGH_PRIORITY (0): HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in...
+    // 0x00000001 [0]     : EN (0): DMA Channel Enable
     io_rw_32 ctrl_trig;
+
+    _REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL
+    // Alias for channel 0 CTRL register
     io_rw_32 al1_ctrl;
+
+    _REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR
+    // Alias for channel 0 READ_ADDR register
     io_rw_32 al1_read_addr;
+
+    _REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR
+    // Alias for channel 0 WRITE_ADDR register
     io_rw_32 al1_write_addr;
+
+    _REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG
+    // Alias for channel 0 TRANS_COUNT register
     io_rw_32 al1_transfer_count_trig;
+
+    _REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL
+    // Alias for channel 0 CTRL register
     io_rw_32 al2_ctrl;
+
+    _REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT
+    // Alias for channel 0 TRANS_COUNT register
     io_rw_32 al2_transfer_count;
+
+    _REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) // DMA_CH0_AL2_READ_ADDR
+    // Alias for channel 0 READ_ADDR register
     io_rw_32 al2_read_addr;
+
+    _REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) // DMA_CH0_AL2_WRITE_ADDR_TRIG
+    // Alias for channel 0 WRITE_ADDR register
     io_rw_32 al2_write_addr_trig;
+
+    _REG_(DMA_CH0_AL3_CTRL_OFFSET) // DMA_CH0_AL3_CTRL
+    // Alias for channel 0 CTRL register
     io_rw_32 al3_ctrl;
+
+    _REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) // DMA_CH0_AL3_WRITE_ADDR
+    // Alias for channel 0 WRITE_ADDR register
     io_rw_32 al3_write_addr;
+
+    _REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) // DMA_CH0_AL3_TRANS_COUNT
+    // Alias for channel 0 TRANS_COUNT register
     io_rw_32 al3_transfer_count;
+
+    _REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) // DMA_CH0_AL3_READ_ADDR_TRIG
+    // Alias for channel 0 READ_ADDR register
     io_rw_32 al3_read_addr_trig;
-}  dma_channel_hw_t;
+} dma_channel_hw_t;
 
 typedef struct {
-    dma_channel_hw_t ch[NUM_DMA_CHANNELS];
-    uint32_t _pad0[16 * (16 - NUM_DMA_CHANNELS)];
+    dma_channel_hw_t ch[NUM_DMA_CHANNELS]; // 12
+
+    uint32_t _pad0[64];
+
+    _REG_(DMA_INTR_OFFSET) // DMA_INTR
+    // Interrupt Status (raw)
+    // 0x0000ffff [15:0]  : INTR (0): Raw interrupt status for DMA Channels 0
     io_ro_32 intr;
+
+    _REG_(DMA_INTE0_OFFSET) // DMA_INTE0
+    // Interrupt Enables for IRQ 0
+    // 0x0000ffff [15:0]  : INTE0 (0): Set bit n to pass interrupts from channel n to DMA IRQ 0
     io_rw_32 inte0;
+
+    _REG_(DMA_INTF0_OFFSET) // DMA_INTF0
+    // Force Interrupts
+    // 0x0000ffff [15:0]  : INTF0 (0): Write 1s to force the corresponding bits in INTE0
     io_rw_32 intf0;
+
+    _REG_(DMA_INTS0_OFFSET) // DMA_INTS0
+    // Interrupt Status for IRQ 0
+    // 0x0000ffff [15:0]  : INTS0 (0): Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted
     io_rw_32 ints0;
-    uint32_t _pad1[1];
+
+    uint32_t _pad1;
+
+    _REG_(DMA_INTE1_OFFSET) // DMA_INTE1
+    // Interrupt Enables for IRQ 1
+    // 0x0000ffff [15:0]  : INTE1 (0): Set bit n to pass interrupts from channel n to DMA IRQ 1
     io_rw_32 inte1;
+
+    _REG_(DMA_INTF1_OFFSET) // DMA_INTF1
+    // Force Interrupts for IRQ 1
+    // 0x0000ffff [15:0]  : INTF1 (0): Write 1s to force the corresponding bits in INTE0
     io_rw_32 intf1;
+
+    _REG_(DMA_INTS1_OFFSET) // DMA_INTS1
+    // Interrupt Status (masked) for IRQ 1
+    // 0x0000ffff [15:0]  : INTS1 (0): Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted
     io_rw_32 ints1;
-    io_rw_32 timer[4];
-    io_wo_32 multi_channel_trigger;
+
+    _REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0
+    // (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes)
+    //
+    // Pacing (X/Y) Fractional Timer
+    // 0xffff0000 [31:16] : X (0): Pacing Timer Dividend
+    // 0x0000ffff [15:0]  : Y (0): Pacing Timer Divisor
+    io_rw_32 timer[NUM_DMA_TIMERS]; // 4
+
+    _REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER
+    // Trigger one or more channels simultaneously
+    // 0x0000ffff [15:0]  : MULTI_CHAN_TRIGGER (0): Each bit in this register corresponds to a DMA channel
+    io_rw_32 multi_channel_trigger;
+
+    _REG_(DMA_SNIFF_CTRL_OFFSET) // DMA_SNIFF_CTRL
+    // Sniffer Control
+    // 0x00000800 [11]    : OUT_INV (0): If set, the result appears inverted (bitwise complement) when read
+    // 0x00000400 [10]    : OUT_REV (0): If set, the result appears bit-reversed when read
+    // 0x00000200 [9]     : BSWAP (0): Locally perform a byte reverse on the sniffed data, before feeding into checksum
+    // 0x000001e0 [8:5]   : CALC (0)
+    // 0x0000001e [4:1]   : DMACH (0): DMA channel for Sniffer to observe
+    // 0x00000001 [0]     : EN (0): Enable sniffer
     io_rw_32 sniff_ctrl;
+
+    _REG_(DMA_SNIFF_DATA_OFFSET) // DMA_SNIFF_DATA
+    // Data accumulator for sniff hardware
     io_rw_32 sniff_data;
-    uint32_t _pad2[1];
+
+    uint32_t _pad2;
+
+    _REG_(DMA_FIFO_LEVELS_OFFSET) // DMA_FIFO_LEVELS
+    // Debug RAF, WAF, TDF levels
+    // 0x00ff0000 [23:16] : RAF_LVL (0): Current Read-Address-FIFO fill level
+    // 0x0000ff00 [15:8]  : WAF_LVL (0): Current Write-Address-FIFO fill level
+    // 0x000000ff [7:0]   : TDF_LVL (0): Current Transfer-Data-FIFO fill level
     io_ro_32 fifo_levels;
-    io_wo_32 abort;
+
+    _REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT
+    // Abort an in-progress transfer sequence on one or more channels
+    // 0x0000ffff [15:0]  : CHAN_ABORT (0): Each bit corresponds to a channel
+    io_rw_32 abort;
 } dma_hw_t;
 
 typedef struct {
     struct dma_debug_hw_channel {
-        io_ro_32 ctrdeq;
+        io_rw_32 ctrdeq;
         io_ro_32 tcr;
         uint32_t pad[14];
     } ch[NUM_DMA_CHANNELS];
@@ -61,4 +197,7 @@ typedef struct {
 #define dma_hw ((dma_hw_t *const)DMA_BASE)
 #define dma_debug_hw ((dma_debug_hw_t *const)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET))
 
+static_assert( NUM_DMA_TIMERS == 4, "");
+static_assert( NUM_DMA_CHANNELS == 12, "");
+
 #endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/i2c.h b/src/rp2040/hardware_structs/include/hardware/structs/i2c.h
index 1a58c50dd..43d608636 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/i2c.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/i2c.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,125 +12,322 @@
 #include "hardware/address_mapped.h"
 #include "hardware/regs/i2c.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_i2c
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/i2c.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(I2C_IC_CON_OFFSET) // I2C_IC_CON
+    // I2C Control Register
+    // 0x00000400 [10]    : STOP_DET_IF_MASTER_ACTIVE (0): Master issues the STOP_DET interrupt irrespective of whether...
+    // 0x00000200 [9]     : RX_FIFO_FULL_HLD_CTRL (0): This bit controls whether DW_apb_i2c should hold the bus when the Rx...
+    // 0x00000100 [8]     : TX_EMPTY_CTRL (0): This bit controls the generation of the TX_EMPTY interrupt, as described in...
+    // 0x00000080 [7]     : STOP_DET_IFADDRESSED (0): In slave mode: - 1'b1:  issues the STOP_DET interrupt only when it is...
+    // 0x00000040 [6]     : IC_SLAVE_DISABLE (1): This bit controls whether I2C has its slave disabled, which means once...
+    // 0x00000020 [5]     : IC_RESTART_EN (1): Determines whether RESTART conditions may be sent when acting as a master
+    // 0x00000010 [4]     : IC_10BITADDR_MASTER (0): Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit...
+    // 0x00000008 [3]     : IC_10BITADDR_SLAVE (0): When acting as a slave, this bit controls whether the DW_apb_i2c...
+    // 0x00000006 [2:1]   : SPEED (0x2): These bits control at which speed the DW_apb_i2c operates; its setting is relevant...
+    // 0x00000001 [0]     : MASTER_MODE (1): This bit controls whether the DW_apb_i2c master is enabled
     io_rw_32 con;
+
+    _REG_(I2C_IC_TAR_OFFSET) // I2C_IC_TAR
+    // I2C Target Address Register
+    // 0x00000800 [11]    : SPECIAL (0): This bit indicates whether software performs a Device-ID or General Call or START...
+    // 0x00000400 [10]    : GC_OR_START (0): If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this...
+    // 0x000003ff [9:0]   : IC_TAR (0x55): This is the target address for any master transaction
     io_rw_32 tar;
+
+    _REG_(I2C_IC_SAR_OFFSET) // I2C_IC_SAR
+    // I2C Slave Address Register
+    // 0x000003ff [9:0]   : IC_SAR (0x55): The IC_SAR holds the slave address when the I2C is operating as a slave
     io_rw_32 sar;
+
     uint32_t _pad0;
+
+    _REG_(I2C_IC_DATA_CMD_OFFSET) // I2C_IC_DATA_CMD
+    // I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the...
+    // 0x00000800 [11]    : FIRST_DATA_BYTE (0): Indicates the first data byte received after the address phase for receive...
+    // 0x00000400 [10]    : RESTART (0): This bit controls whether a RESTART is issued before the byte is sent or received
+    // 0x00000200 [9]     : STOP (0): This bit controls whether a STOP is issued after the byte is sent or received
+    // 0x00000100 [8]     : CMD (0): This bit controls whether a read or a write is performed
+    // 0x000000ff [7:0]   : DAT (0): This register contains the data to be transmitted or received on the I2C bus
     io_rw_32 data_cmd;
+
+    _REG_(I2C_IC_SS_SCL_HCNT_OFFSET) // I2C_IC_SS_SCL_HCNT
+    // Standard Speed I2C Clock SCL High Count Register
+    // 0x0000ffff [15:0]  : IC_SS_SCL_HCNT (0x28): This register must be set before any I2C bus transaction can take place...
     io_rw_32 ss_scl_hcnt;
+
+    _REG_(I2C_IC_SS_SCL_LCNT_OFFSET) // I2C_IC_SS_SCL_LCNT
+    // Standard Speed I2C Clock SCL Low Count Register
+    // 0x0000ffff [15:0]  : IC_SS_SCL_LCNT (0x2f): This register must be set before any I2C bus transaction can take place...
     io_rw_32 ss_scl_lcnt;
+
+    _REG_(I2C_IC_FS_SCL_HCNT_OFFSET) // I2C_IC_FS_SCL_HCNT
+    // Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
+    // 0x0000ffff [15:0]  : IC_FS_SCL_HCNT (0x6): This register must be set before any I2C bus transaction can take place...
     io_rw_32 fs_scl_hcnt;
+
+    _REG_(I2C_IC_FS_SCL_LCNT_OFFSET) // I2C_IC_FS_SCL_LCNT
+    // Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
+    // 0x0000ffff [15:0]  : IC_FS_SCL_LCNT (0xd): This register must be set before any I2C bus transaction can take place...
     io_rw_32 fs_scl_lcnt;
+
     uint32_t _pad1[2];
-    io_rw_32 intr_stat;
+
+    _REG_(I2C_IC_INTR_STAT_OFFSET) // I2C_IC_INTR_STAT
+    // I2C Interrupt Status Register
+    // 0x00001000 [12]    : R_RESTART_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit
+    // 0x00000800 [11]    : R_GEN_CALL (0): See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit
+    // 0x00000400 [10]    : R_START_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit
+    // 0x00000200 [9]     : R_STOP_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit
+    // 0x00000100 [8]     : R_ACTIVITY (0): See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit
+    // 0x00000080 [7]     : R_RX_DONE (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit
+    // 0x00000040 [6]     : R_TX_ABRT (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit
+    // 0x00000020 [5]     : R_RD_REQ (0): See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit
+    // 0x00000010 [4]     : R_TX_EMPTY (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit
+    // 0x00000008 [3]     : R_TX_OVER (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit
+    // 0x00000004 [2]     : R_RX_FULL (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit
+    // 0x00000002 [1]     : R_RX_OVER (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit
+    // 0x00000001 [0]     : R_RX_UNDER (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit
+    io_ro_32 intr_stat;
+
+    _REG_(I2C_IC_INTR_MASK_OFFSET) // I2C_IC_INTR_MASK
+    // I2C Interrupt Mask Register
+    // 0x00001000 [12]    : M_RESTART_DET (0): This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register
+    // 0x00000800 [11]    : M_GEN_CALL (1): This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register
+    // 0x00000400 [10]    : M_START_DET (0): This bit masks the R_START_DET interrupt in IC_INTR_STAT register
+    // 0x00000200 [9]     : M_STOP_DET (0): This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register
+    // 0x00000100 [8]     : M_ACTIVITY (0): This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register
+    // 0x00000080 [7]     : M_RX_DONE (1): This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register
+    // 0x00000040 [6]     : M_TX_ABRT (1): This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register
+    // 0x00000020 [5]     : M_RD_REQ (1): This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register
+    // 0x00000010 [4]     : M_TX_EMPTY (1): This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register
+    // 0x00000008 [3]     : M_TX_OVER (1): This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register
+    // 0x00000004 [2]     : M_RX_FULL (1): This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register
+    // 0x00000002 [1]     : M_RX_OVER (1): This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register
+    // 0x00000001 [0]     : M_RX_UNDER (1): This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register
     io_rw_32 intr_mask;
-    io_rw_32 raw_intr_stat;
+
+    _REG_(I2C_IC_RAW_INTR_STAT_OFFSET) // I2C_IC_RAW_INTR_STAT
+    // I2C Raw Interrupt Status Register
+    // 0x00001000 [12]    : RESTART_DET (0): Indicates whether a RESTART condition has occurred on the I2C interface when...
+    // 0x00000800 [11]    : GEN_CALL (0): Set only when a General Call address is received and it is acknowledged
+    // 0x00000400 [10]    : START_DET (0): Indicates whether a START or RESTART condition has occurred on the I2C interface...
+    // 0x00000200 [9]     : STOP_DET (0): Indicates whether a STOP condition has occurred on the I2C interface regardless...
+    // 0x00000100 [8]     : ACTIVITY (0): This bit captures DW_apb_i2c activity and stays set until it is cleared
+    // 0x00000080 [7]     : RX_DONE (0): When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the...
+    // 0x00000040 [6]     : TX_ABRT (0): This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the...
+    // 0x00000020 [5]     : RD_REQ (0): This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is...
+    // 0x00000010 [4]     : TX_EMPTY (0): The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL...
+    // 0x00000008 [3]     : TX_OVER (0): Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the...
+    // 0x00000004 [2]     : RX_FULL (0): Set when the receive buffer reaches or goes above the RX_TL threshold in the...
+    // 0x00000002 [1]     : RX_OVER (0): Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an...
+    // 0x00000001 [0]     : RX_UNDER (0): Set if the processor attempts to read the receive buffer when it is empty by...
+    io_ro_32 raw_intr_stat;
+
+    _REG_(I2C_IC_RX_TL_OFFSET) // I2C_IC_RX_TL
+    // I2C Receive FIFO Threshold Register
+    // 0x000000ff [7:0]   : RX_TL (0): Receive FIFO Threshold Level
     io_rw_32 rx_tl;
+
+    _REG_(I2C_IC_TX_TL_OFFSET) // I2C_IC_TX_TL
+    // I2C Transmit FIFO Threshold Register
+    // 0x000000ff [7:0]   : TX_TL (0): Transmit FIFO Threshold Level
     io_rw_32 tx_tl;
-    io_rw_32 clr_intr;
-    io_rw_32 clr_rx_under;
-    io_rw_32 clr_rx_over;
-    io_rw_32 clr_tx_over;
-    io_rw_32 clr_rd_req;
-    io_rw_32 clr_tx_abrt;
-    io_rw_32 clr_rx_done;
-    io_rw_32 clr_activity;
-    io_rw_32 clr_stop_det;
-    io_rw_32 clr_start_det;
-    io_rw_32 clr_gen_call;
+
+    _REG_(I2C_IC_CLR_INTR_OFFSET) // I2C_IC_CLR_INTR
+    // Clear Combined and Individual Interrupt Register
+    // 0x00000001 [0]     : CLR_INTR (0): Read this register to clear the combined interrupt, all individual interrupts,...
+    io_ro_32 clr_intr;
+
+    _REG_(I2C_IC_CLR_RX_UNDER_OFFSET) // I2C_IC_CLR_RX_UNDER
+    // Clear RX_UNDER Interrupt Register
+    // 0x00000001 [0]     : CLR_RX_UNDER (0): Read this register to clear the RX_UNDER interrupt (bit 0) of the...
+    io_ro_32 clr_rx_under;
+
+    _REG_(I2C_IC_CLR_RX_OVER_OFFSET) // I2C_IC_CLR_RX_OVER
+    // Clear RX_OVER Interrupt Register
+    // 0x00000001 [0]     : CLR_RX_OVER (0): Read this register to clear the RX_OVER interrupt (bit 1) of the...
+    io_ro_32 clr_rx_over;
+
+    _REG_(I2C_IC_CLR_TX_OVER_OFFSET) // I2C_IC_CLR_TX_OVER
+    // Clear TX_OVER Interrupt Register
+    // 0x00000001 [0]     : CLR_TX_OVER (0): Read this register to clear the TX_OVER interrupt (bit 3) of the...
+    io_ro_32 clr_tx_over;
+
+    _REG_(I2C_IC_CLR_RD_REQ_OFFSET) // I2C_IC_CLR_RD_REQ
+    // Clear RD_REQ Interrupt Register
+    // 0x00000001 [0]     : CLR_RD_REQ (0): Read this register to clear the RD_REQ interrupt (bit 5) of the...
+    io_ro_32 clr_rd_req;
+
+    _REG_(I2C_IC_CLR_TX_ABRT_OFFSET) // I2C_IC_CLR_TX_ABRT
+    // Clear TX_ABRT Interrupt Register
+    // 0x00000001 [0]     : CLR_TX_ABRT (0): Read this register to clear the TX_ABRT interrupt (bit 6) of the...
+    io_ro_32 clr_tx_abrt;
+
+    _REG_(I2C_IC_CLR_RX_DONE_OFFSET) // I2C_IC_CLR_RX_DONE
+    // Clear RX_DONE Interrupt Register
+    // 0x00000001 [0]     : CLR_RX_DONE (0): Read this register to clear the RX_DONE interrupt (bit 7) of the...
+    io_ro_32 clr_rx_done;
+
+    _REG_(I2C_IC_CLR_ACTIVITY_OFFSET) // I2C_IC_CLR_ACTIVITY
+    // Clear ACTIVITY Interrupt Register
+    // 0x00000001 [0]     : CLR_ACTIVITY (0): Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore
+    io_ro_32 clr_activity;
+
+    _REG_(I2C_IC_CLR_STOP_DET_OFFSET) // I2C_IC_CLR_STOP_DET
+    // Clear STOP_DET Interrupt Register
+    // 0x00000001 [0]     : CLR_STOP_DET (0): Read this register to clear the STOP_DET interrupt (bit 9) of the...
+    io_ro_32 clr_stop_det;
+
+    _REG_(I2C_IC_CLR_START_DET_OFFSET) // I2C_IC_CLR_START_DET
+    // Clear START_DET Interrupt Register
+    // 0x00000001 [0]     : CLR_START_DET (0): Read this register to clear the START_DET interrupt (bit 10) of the...
+    io_ro_32 clr_start_det;
+
+    _REG_(I2C_IC_CLR_GEN_CALL_OFFSET) // I2C_IC_CLR_GEN_CALL
+    // Clear GEN_CALL Interrupt Register
+    // 0x00000001 [0]     : CLR_GEN_CALL (0): Read this register to clear the GEN_CALL interrupt (bit 11) of...
+    io_ro_32 clr_gen_call;
+
+    _REG_(I2C_IC_ENABLE_OFFSET) // I2C_IC_ENABLE
+    // I2C Enable Register
+    // 0x00000004 [2]     : TX_CMD_BLOCK (0): In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx...
+    // 0x00000002 [1]     : ABORT (0): When set, the controller initiates the transfer abort
+    // 0x00000001 [0]     : ENABLE (0): Controls whether the DW_apb_i2c is enabled
     io_rw_32 enable;
-    io_rw_32 status;
-    io_rw_32 txflr;
-    io_rw_32 rxflr;
+
+    _REG_(I2C_IC_STATUS_OFFSET) // I2C_IC_STATUS
+    // I2C Status Register
+    // 0x00000040 [6]     : SLV_ACTIVITY (0): Slave FSM Activity Status
+    // 0x00000020 [5]     : MST_ACTIVITY (0): Master FSM Activity Status
+    // 0x00000010 [4]     : RFF (0): Receive FIFO Completely Full
+    // 0x00000008 [3]     : RFNE (0): Receive FIFO Not Empty
+    // 0x00000004 [2]     : TFE (1): Transmit FIFO Completely Empty
+    // 0x00000002 [1]     : TFNF (1): Transmit FIFO Not Full
+    // 0x00000001 [0]     : ACTIVITY (0): I2C Activity Status
+    io_ro_32 status;
+
+    _REG_(I2C_IC_TXFLR_OFFSET) // I2C_IC_TXFLR
+    // I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer
+    // 0x0000001f [4:0]   : TXFLR (0): Transmit FIFO Level
+    io_ro_32 txflr;
+
+    _REG_(I2C_IC_RXFLR_OFFSET) // I2C_IC_RXFLR
+    // I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer
+    // 0x0000001f [4:0]   : RXFLR (0): Receive FIFO Level
+    io_ro_32 rxflr;
+
+    _REG_(I2C_IC_SDA_HOLD_OFFSET) // I2C_IC_SDA_HOLD
+    // I2C SDA Hold Time Length Register
+    // 0x00ff0000 [23:16] : IC_SDA_RX_HOLD (0): Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c...
+    // 0x0000ffff [15:0]  : IC_SDA_TX_HOLD (1): Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c...
     io_rw_32 sda_hold;
-    io_rw_32 tx_abrt_source;
+
+    _REG_(I2C_IC_TX_ABRT_SOURCE_OFFSET) // I2C_IC_TX_ABRT_SOURCE
+    // I2C Transmit Abort Source Register
+    // 0xff800000 [31:23] : TX_FLUSH_CNT (0): This field indicates the number of Tx FIFO Data Commands which are flushed...
+    // 0x00010000 [16]    : ABRT_USER_ABRT (0): This is a master-mode-only bit
+    // 0x00008000 [15]    : ABRT_SLVRD_INTX (0): 1: When the processor side responds to a slave mode request for data to be...
+    // 0x00004000 [14]    : ABRT_SLV_ARBLOST (0): This field indicates that a Slave has lost the bus while transmitting...
+    // 0x00002000 [13]    : ABRT_SLVFLUSH_TXFIFO (0): This field specifies that the Slave has received a read command and...
+    // 0x00001000 [12]    : ARB_LOST (0): This field specifies that the Master has lost arbitration, or if...
+    // 0x00000800 [11]    : ABRT_MASTER_DIS (0): This field indicates that the User tries to initiate a Master operation...
+    // 0x00000400 [10]    : ABRT_10B_RD_NORSTRT (0): This field indicates that the restart is disabled (IC_RESTART_EN bit...
+    // 0x00000200 [9]     : ABRT_SBYTE_NORSTRT (0): To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed...
+    // 0x00000100 [8]     : ABRT_HS_NORSTRT (0): This field indicates that the restart is disabled (IC_RESTART_EN bit...
+    // 0x00000080 [7]     : ABRT_SBYTE_ACKDET (0): This field indicates that the Master has sent a START Byte and the START...
+    // 0x00000040 [6]     : ABRT_HS_ACKDET (0): This field indicates that the Master is in High Speed mode and the High...
+    // 0x00000020 [5]     : ABRT_GCALL_READ (0): This field indicates that DW_apb_i2c in the master mode has sent a General...
+    // 0x00000010 [4]     : ABRT_GCALL_NOACK (0): This field indicates that DW_apb_i2c in master mode has sent a General...
+    // 0x00000008 [3]     : ABRT_TXDATA_NOACK (0): This field indicates the master-mode only bit
+    // 0x00000004 [2]     : ABRT_10ADDR2_NOACK (0): This field indicates that the Master is in 10-bit address mode and that...
+    // 0x00000002 [1]     : ABRT_10ADDR1_NOACK (0): This field indicates that the Master is in 10-bit address mode and the...
+    // 0x00000001 [0]     : ABRT_7B_ADDR_NOACK (0): This field indicates that the Master is in 7-bit addressing mode and...
+    io_ro_32 tx_abrt_source;
+
+    _REG_(I2C_IC_SLV_DATA_NACK_ONLY_OFFSET) // I2C_IC_SLV_DATA_NACK_ONLY
+    // Generate Slave Data NACK Register
+    // 0x00000001 [0]     : NACK (0): Generate NACK
     io_rw_32 slv_data_nack_only;
+
+    _REG_(I2C_IC_DMA_CR_OFFSET) // I2C_IC_DMA_CR
+    // DMA Control Register
+    // 0x00000002 [1]     : TDMAE (0): Transmit DMA Enable
+    // 0x00000001 [0]     : RDMAE (0): Receive DMA Enable
     io_rw_32 dma_cr;
+
+    _REG_(I2C_IC_DMA_TDLR_OFFSET) // I2C_IC_DMA_TDLR
+    // DMA Transmit Data Level Register
+    // 0x0000000f [3:0]   : DMATDL (0): Transmit Data Level
     io_rw_32 dma_tdlr;
+
+    _REG_(I2C_IC_DMA_RDLR_OFFSET) // I2C_IC_DMA_RDLR
+    // I2C Receive Data Level Register
+    // 0x0000000f [3:0]   : DMARDL (0): Receive Data Level
     io_rw_32 dma_rdlr;
+
+    _REG_(I2C_IC_SDA_SETUP_OFFSET) // I2C_IC_SDA_SETUP
+    // I2C SDA Setup Register
+    // 0x000000ff [7:0]   : SDA_SETUP (0x64): SDA Setup
     io_rw_32 sda_setup;
+
+    _REG_(I2C_IC_ACK_GENERAL_CALL_OFFSET) // I2C_IC_ACK_GENERAL_CALL
+    // I2C ACK General Call Register
+    // 0x00000001 [0]     : ACK_GEN_CALL (1): ACK General Call
     io_rw_32 ack_general_call;
-    io_rw_32 enable_status;
+
+    _REG_(I2C_IC_ENABLE_STATUS_OFFSET) // I2C_IC_ENABLE_STATUS
+    // I2C Enable Status Register
+    // 0x00000004 [2]     : SLV_RX_DATA_LOST (0): Slave Received Data Lost
+    // 0x00000002 [1]     : SLV_DISABLED_WHILE_BUSY (0): Slave Disabled While Busy (Transmit, Receive)
+    // 0x00000001 [0]     : IC_EN (0): ic_en Status
+    io_ro_32 enable_status;
+
+    _REG_(I2C_IC_FS_SPKLEN_OFFSET) // I2C_IC_FS_SPKLEN
+    // I2C SS, FS or FM+ spike suppression limit
+    // 0x000000ff [7:0]   : IC_FS_SPKLEN (0x7): This register must be set before any I2C bus transaction can take place to...
     io_rw_32 fs_spklen;
+
     uint32_t _pad2;
-    io_rw_32 clr_restart_det;
+
+    _REG_(I2C_IC_CLR_RESTART_DET_OFFSET) // I2C_IC_CLR_RESTART_DET
+    // Clear RESTART_DET Interrupt Register
+    // 0x00000001 [0]     : CLR_RESTART_DET (0): Read this register to clear the RESTART_DET interrupt (bit 12) of...
+    io_ro_32 clr_restart_det;
+
+    uint32_t _pad3[18];
+
+    _REG_(I2C_IC_COMP_PARAM_1_OFFSET) // I2C_IC_COMP_PARAM_1
+    // Component Parameter Register 1
+    // 0x00ff0000 [23:16] : TX_BUFFER_DEPTH (0): TX Buffer Depth = 16
+    // 0x0000ff00 [15:8]  : RX_BUFFER_DEPTH (0): RX Buffer Depth = 16
+    // 0x00000080 [7]     : ADD_ENCODED_PARAMS (0): Encoded parameters not visible
+    // 0x00000040 [6]     : HAS_DMA (0): DMA handshaking signals are enabled
+    // 0x00000020 [5]     : INTR_IO (0): COMBINED Interrupt outputs
+    // 0x00000010 [4]     : HC_COUNT_VALUES (0): Programmable count values for each mode
+    // 0x0000000c [3:2]   : MAX_SPEED_MODE (0): MAX SPEED MODE = FAST MODE
+    // 0x00000003 [1:0]   : APB_DATA_WIDTH (0): APB data bus width is 32 bits
+    io_ro_32 comp_param_1;
+
+    _REG_(I2C_IC_COMP_VERSION_OFFSET) // I2C_IC_COMP_VERSION
+    // I2C Component Version Register
+    // 0xffffffff [31:0]  : IC_COMP_VERSION (0x3230312a)
+    io_ro_32 comp_version;
+
+    _REG_(I2C_IC_COMP_TYPE_OFFSET) // I2C_IC_COMP_TYPE
+    // I2C Component Type Register
+    // 0xffffffff [31:0]  : IC_COMP_TYPE (0x44570140): Designware Component Type number = 0x44_57_01_40
+    io_ro_32 comp_type;
 } i2c_hw_t;
 
 #define i2c0_hw ((i2c_hw_t *const)I2C0_BASE)
 #define i2c1_hw ((i2c_hw_t *const)I2C1_BASE)
 
-// List of configuration constants for the Synopsys I2C hardware (you may see
-// references to these in I2C register header; these are *fixed* values,
-// set at hardware design time):
-
-// IC_ULTRA_FAST_MODE ................ 0x0
-// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8
-// IC_UFM_SCL_LOW_COUNT .............. 0x0008
-// IC_UFM_SCL_HIGH_COUNT ............. 0x0006
-// IC_TX_TL .......................... 0x0
-// IC_TX_CMD_BLOCK ................... 0x1
-// IC_HAS_DMA ........................ 0x1
-// IC_HAS_ASYNC_FIFO ................. 0x0
-// IC_SMBUS_ARP ...................... 0x0
-// IC_FIRST_DATA_BYTE_STATUS ......... 0x1
-// IC_INTR_IO ........................ 0x1
-// IC_MASTER_MODE .................... 0x1
-// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1
-// IC_INTR_POL ....................... 0x1
-// IC_OPTIONAL_SAR ................... 0x0
-// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055
-// IC_DEFAULT_SLAVE_ADDR ............. 0x055
-// IC_DEFAULT_HS_SPKLEN .............. 0x1
-// IC_FS_SCL_HIGH_COUNT .............. 0x0006
-// IC_HS_SCL_LOW_COUNT ............... 0x0008
-// IC_DEVICE_ID_VALUE ................ 0x0
-// IC_10BITADDR_MASTER ............... 0x0
-// IC_CLK_FREQ_OPTIMIZATION .......... 0x0
-// IC_DEFAULT_FS_SPKLEN .............. 0x7
-// IC_ADD_ENCODED_PARAMS ............. 0x0
-// IC_DEFAULT_SDA_HOLD ............... 0x000001
-// IC_DEFAULT_SDA_SETUP .............. 0x64
-// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
-// IC_CLOCK_PERIOD ................... 100
-// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1
-// IC_RESTART_EN ..................... 0x1
-// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0
-// IC_BUS_CLEAR_FEATURE .............. 0x0
-// IC_CAP_LOADING .................... 100
-// IC_FS_SCL_LOW_COUNT ............... 0x000d
-// APB_DATA_WIDTH .................... 32
-// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
-// IC_SLV_DATA_NACK_ONLY ............. 0x1
-// IC_10BITADDR_SLAVE ................ 0x0
-// IC_CLK_TYPE ....................... 0x0
-// IC_SMBUS_UDID_MSB ................. 0x0
-// IC_SMBUS_SUSPEND_ALERT ............ 0x0
-// IC_HS_SCL_HIGH_COUNT .............. 0x0006
-// IC_SLV_RESTART_DET_EN ............. 0x1
-// IC_SMBUS .......................... 0x0
-// IC_OPTIONAL_SAR_DEFAULT ........... 0x0
-// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0
-// IC_USE_COUNTS ..................... 0x0
-// IC_RX_BUFFER_DEPTH ................ 16
-// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
-// IC_RX_FULL_HLD_BUS_EN ............. 0x1
-// IC_SLAVE_DISABLE .................. 0x1
-// IC_RX_TL .......................... 0x0
-// IC_DEVICE_ID ...................... 0x0
-// IC_HC_COUNT_VALUES ................ 0x0
-// I2C_DYNAMIC_TAR_UPDATE ............ 0
-// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff
-// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff
-// IC_HS_MASTER_CODE ................. 0x1
-// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff
-// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff
-// IC_SS_SCL_HIGH_COUNT .............. 0x0028
-// IC_SS_SCL_LOW_COUNT ............... 0x002f
-// IC_MAX_SPEED_MODE ................. 0x2
-// IC_STAT_FOR_CLK_STRETCH ........... 0x0
-// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
-// IC_DEFAULT_UFM_SPKLEN ............. 0x1
-// IC_TX_BUFFER_DEPTH ................ 16
-
 #endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/interp.h b/src/rp2040/hardware_structs/include/hardware/structs/interp.h
index 683750733..e96caab2f 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/interp.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/interp.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,16 +10,68 @@
 #define _HARDWARE_STRUCTS_INTERP_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/sio.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0
+    // (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes)
+    //
+    // Read/write access to accumulator 0
     io_rw_32 accum[2];
+
+    _REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0
+    // (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes)
+    //
+    // Read/write access to BASE0 register
     io_rw_32 base[3];
+
+    _REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0
+    // (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes)
+    //
+    // Read LANE0 result, and simultaneously write lane results to both accumulators (POP)
     io_ro_32 pop[3];
+
+    _REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0
+    // (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes)
+    //
+    // Read LANE0 result, without altering any internal state (PEEK)
     io_ro_32 peek[3];
+
+    _REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0
+    // (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes)
+    //
+    // Control register for lane 0
+    // 0x02000000 [25]    : OVERF (0): Set if either OVERF0 or OVERF1 is set
+    // 0x01000000 [24]    : OVERF1 (0): Indicates if any masked-off MSBs in ACCUM1 are set
+    // 0x00800000 [23]    : OVERF0 (0): Indicates if any masked-off MSBs in ACCUM0 are set
+    // 0x00200000 [21]    : BLEND (0): Only present on INTERP0 on each core
+    // 0x00180000 [20:19] : FORCE_MSB (0): ORed into bits 29:28 of the lane result presented to the processor on the bus
+    // 0x00040000 [18]    : ADD_RAW (0): If 1, mask + shift is bypassed for LANE0 result
+    // 0x00020000 [17]    : CROSS_RESULT (0): If 1, feed the opposite lane's result into this lane's accumulator on POP
+    // 0x00010000 [16]    : CROSS_INPUT (0): If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware
+    // 0x00008000 [15]    : SIGNED (0): If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits
+    // 0x00007c00 [14:10] : MASK_MSB (0): The most-significant bit allowed to pass by the mask (inclusive)
+    // 0x000003e0 [9:5]   : MASK_LSB (0): The least-significant bit allowed to pass by the mask (inclusive)
+    // 0x0000001f [4:0]   : SHIFT (0): Logical right-shift applied to accumulator before masking
     io_rw_32 ctrl[2];
+
+    _REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD
+    // (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes)
+    //
+    // Values written here are atomically added to ACCUM0
+    // 0x00ffffff [23:0]  : INTERP0_ACCUM0_ADD (0)
     io_rw_32 add_raw[2];
+
+    _REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0
+    // On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously
     io_wo_32 base01;
 } interp_hw_t;
 
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/iobank0.h b/src/rp2040/hardware_structs/include/hardware/structs/iobank0.h
index b19800fa7..aae74b2a6 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/iobank0.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/iobank0.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,28 +10,207 @@
 #define _HARDWARE_STRUCTS_IOBANK0_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/io_bank0.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_bank0
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(IO_BANK0_GPIO0_STATUS_OFFSET) // IO_BANK0_GPIO0_STATUS
+    // GPIO status
+    // 0x04000000 [26]    : IRQTOPROC (0): interrupt to processors, after override is applied
+    // 0x01000000 [24]    : IRQFROMPAD (0): interrupt from pad before override is applied
+    // 0x00080000 [19]    : INTOPERI (0): input signal to peripheral, after override is applied
+    // 0x00020000 [17]    : INFROMPAD (0): input signal from pad, before override is applied
+    // 0x00002000 [13]    : OETOPAD (0): output enable to pad after register override is applied
+    // 0x00001000 [12]    : OEFROMPERI (0): output enable from selected peripheral, before register override is applied
+    // 0x00000200 [9]     : OUTTOPAD (0): output signal to pad after register override is applied
+    // 0x00000100 [8]     : OUTFROMPERI (0): output signal from selected peripheral, before register override is applied
+    io_ro_32 status;
+
+    _REG_(IO_BANK0_GPIO0_CTRL_OFFSET) // IO_BANK0_GPIO0_CTRL
+    // GPIO control including function select and overrides
+    // 0x30000000 [29:28] : IRQOVER (0)
+    // 0x00030000 [17:16] : INOVER (0)
+    // 0x00003000 [13:12] : OEOVER (0)
+    // 0x00000300 [9:8]   : OUTOVER (0)
+    // 0x0000001f [4:0]   : FUNCSEL (0x1f): 0-31 -> selects pin function according to the gpio table
+    io_rw_32 ctrl;
+} iobank0_status_ctrl_hw_t;
+
+typedef struct {
+    _REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0
+    // (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes)
+    //
+    // Interrupt Enable for proc0
+    // 0x80000000 [31]    : GPIO7_EDGE_HIGH (0)
+    // 0x40000000 [30]    : GPIO7_EDGE_LOW (0)
+    // 0x20000000 [29]    : GPIO7_LEVEL_HIGH (0)
+    // 0x10000000 [28]    : GPIO7_LEVEL_LOW (0)
+    // 0x08000000 [27]    : GPIO6_EDGE_HIGH (0)
+    // 0x04000000 [26]    : GPIO6_EDGE_LOW (0)
+    // 0x02000000 [25]    : GPIO6_LEVEL_HIGH (0)
+    // 0x01000000 [24]    : GPIO6_LEVEL_LOW (0)
+    // 0x00800000 [23]    : GPIO5_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO5_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO5_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO5_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO4_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO4_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO4_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO4_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO3_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO3_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO3_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO3_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO2_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO2_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO2_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO2_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO1_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO1_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO1_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO1_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO0_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO0_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO0_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO0_LEVEL_LOW (0)
     io_rw_32 inte[4];
+
+    _REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0
+    // (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes)
+    //
+    // Interrupt Force for proc0
+    // 0x80000000 [31]    : GPIO7_EDGE_HIGH (0)
+    // 0x40000000 [30]    : GPIO7_EDGE_LOW (0)
+    // 0x20000000 [29]    : GPIO7_LEVEL_HIGH (0)
+    // 0x10000000 [28]    : GPIO7_LEVEL_LOW (0)
+    // 0x08000000 [27]    : GPIO6_EDGE_HIGH (0)
+    // 0x04000000 [26]    : GPIO6_EDGE_LOW (0)
+    // 0x02000000 [25]    : GPIO6_LEVEL_HIGH (0)
+    // 0x01000000 [24]    : GPIO6_LEVEL_LOW (0)
+    // 0x00800000 [23]    : GPIO5_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO5_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO5_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO5_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO4_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO4_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO4_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO4_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO3_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO3_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO3_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO3_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO2_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO2_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO2_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO2_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO1_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO1_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO1_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO1_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO0_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO0_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO0_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO0_LEVEL_LOW (0)
     io_rw_32 intf[4];
-    io_rw_32 ints[4];
+
+    _REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0
+    // (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes)
+    //
+    // Interrupt status after masking & forcing for proc0
+    // 0x80000000 [31]    : GPIO7_EDGE_HIGH (0)
+    // 0x40000000 [30]    : GPIO7_EDGE_LOW (0)
+    // 0x20000000 [29]    : GPIO7_LEVEL_HIGH (0)
+    // 0x10000000 [28]    : GPIO7_LEVEL_LOW (0)
+    // 0x08000000 [27]    : GPIO6_EDGE_HIGH (0)
+    // 0x04000000 [26]    : GPIO6_EDGE_LOW (0)
+    // 0x02000000 [25]    : GPIO6_LEVEL_HIGH (0)
+    // 0x01000000 [24]    : GPIO6_LEVEL_LOW (0)
+    // 0x00800000 [23]    : GPIO5_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO5_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO5_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO5_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO4_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO4_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO4_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO4_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO3_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO3_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO3_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO3_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO2_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO2_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO2_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO2_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO1_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO1_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO1_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO1_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO0_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO0_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO0_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO0_LEVEL_LOW (0)
+    io_ro_32 ints[4];
 } io_irq_ctrl_hw_t;
 
 /// \tag::iobank0_hw[]
 typedef struct {
-    struct {
-        io_rw_32 status;
-        io_rw_32 ctrl;
-    } io[30];
+    iobank0_status_ctrl_hw_t io[NUM_BANK0_GPIOS]; // 30
+
+    _REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0
+    // (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes)
+    //
+    // Raw Interrupts
+    // 0x80000000 [31]    : GPIO7_EDGE_HIGH (0)
+    // 0x40000000 [30]    : GPIO7_EDGE_LOW (0)
+    // 0x20000000 [29]    : GPIO7_LEVEL_HIGH (0)
+    // 0x10000000 [28]    : GPIO7_LEVEL_LOW (0)
+    // 0x08000000 [27]    : GPIO6_EDGE_HIGH (0)
+    // 0x04000000 [26]    : GPIO6_EDGE_LOW (0)
+    // 0x02000000 [25]    : GPIO6_LEVEL_HIGH (0)
+    // 0x01000000 [24]    : GPIO6_LEVEL_LOW (0)
+    // 0x00800000 [23]    : GPIO5_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO5_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO5_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO5_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO4_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO4_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO4_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO4_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO3_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO3_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO3_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO3_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO2_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO2_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO2_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO2_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO1_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO1_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO1_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO1_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO0_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO0_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO0_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO0_LEVEL_LOW (0)
     io_rw_32 intr[4];
+
     io_irq_ctrl_hw_t proc0_irq_ctrl;
+
     io_irq_ctrl_hw_t proc1_irq_ctrl;
+
     io_irq_ctrl_hw_t dormant_wake_irq_ctrl;
 } iobank0_hw_t;
-/// \end::iobank0_hw[]
 
 #define iobank0_hw ((iobank0_hw_t *const)IO_BANK0_BASE)
+/// \end::iobank0_hw[]
+
+static_assert( NUM_BANK0_GPIOS == 30, "");
 
 #endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/ioqspi.h b/src/rp2040/hardware_structs/include/hardware/structs/ioqspi.h
index 48d08a7c9..2992bfe52 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/ioqspi.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/ioqspi.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,16 +10,165 @@
 #define _HARDWARE_STRUCTS_IOQSPI_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/io_qspi.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_qspi
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS
+    // GPIO status
+    // 0x04000000 [26]    : IRQTOPROC (0): interrupt to processors, after override is applied
+    // 0x01000000 [24]    : IRQFROMPAD (0): interrupt from pad before override is applied
+    // 0x00080000 [19]    : INTOPERI (0): input signal to peripheral, after override is applied
+    // 0x00020000 [17]    : INFROMPAD (0): input signal from pad, before override is applied
+    // 0x00002000 [13]    : OETOPAD (0): output enable to pad after register override is applied
+    // 0x00001000 [12]    : OEFROMPERI (0): output enable from selected peripheral, before register override is applied
+    // 0x00000200 [9]     : OUTTOPAD (0): output signal to pad after register override is applied
+    // 0x00000100 [8]     : OUTFROMPERI (0): output signal from selected peripheral, before register override is applied
+    io_ro_32 status;
+
+    _REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL
+    // GPIO control including function select and overrides
+    // 0x30000000 [29:28] : IRQOVER (0)
+    // 0x00030000 [17:16] : INOVER (0)
+    // 0x00003000 [13:12] : OEOVER (0)
+    // 0x00000300 [9:8]   : OUTOVER (0)
+    // 0x0000001f [4:0]   : FUNCSEL (0x1f): 0-31 -> selects pin function according to the gpio table
+    io_rw_32 ctrl;
+} ioqspi_status_ctrl_hw_t;
+
+typedef struct {
+    _REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE
+    // Interrupt Enable for proc0
+    // 0x00800000 [23]    : GPIO_QSPI_SD3_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO_QSPI_SD3_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO_QSPI_SD3_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO_QSPI_SD3_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO_QSPI_SD2_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO_QSPI_SD2_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO_QSPI_SD2_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO_QSPI_SD2_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO_QSPI_SD1_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO_QSPI_SD1_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO_QSPI_SD1_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO_QSPI_SD1_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO_QSPI_SD0_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO_QSPI_SD0_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO_QSPI_SD0_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO_QSPI_SD0_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO_QSPI_SS_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO_QSPI_SS_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO_QSPI_SS_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO_QSPI_SS_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO_QSPI_SCLK_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO_QSPI_SCLK_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO_QSPI_SCLK_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO_QSPI_SCLK_LEVEL_LOW (0)
+    io_rw_32 inte;
+
+    _REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF
+    // Interrupt Force for proc0
+    // 0x00800000 [23]    : GPIO_QSPI_SD3_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO_QSPI_SD3_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO_QSPI_SD3_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO_QSPI_SD3_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO_QSPI_SD2_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO_QSPI_SD2_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO_QSPI_SD2_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO_QSPI_SD2_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO_QSPI_SD1_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO_QSPI_SD1_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO_QSPI_SD1_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO_QSPI_SD1_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO_QSPI_SD0_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO_QSPI_SD0_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO_QSPI_SD0_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO_QSPI_SD0_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO_QSPI_SS_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO_QSPI_SS_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO_QSPI_SS_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO_QSPI_SS_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO_QSPI_SCLK_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO_QSPI_SCLK_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO_QSPI_SCLK_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO_QSPI_SCLK_LEVEL_LOW (0)
+    io_rw_32 intf;
+
+    _REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS
+    // Interrupt status after masking & forcing for proc0
+    // 0x00800000 [23]    : GPIO_QSPI_SD3_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO_QSPI_SD3_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO_QSPI_SD3_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO_QSPI_SD3_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO_QSPI_SD2_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO_QSPI_SD2_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO_QSPI_SD2_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO_QSPI_SD2_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO_QSPI_SD1_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO_QSPI_SD1_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO_QSPI_SD1_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO_QSPI_SD1_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO_QSPI_SD0_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO_QSPI_SD0_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO_QSPI_SD0_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO_QSPI_SD0_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO_QSPI_SS_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO_QSPI_SS_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO_QSPI_SS_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO_QSPI_SS_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO_QSPI_SCLK_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO_QSPI_SCLK_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO_QSPI_SCLK_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO_QSPI_SCLK_LEVEL_LOW (0)
+    io_ro_32 ints;
+} io_qspi_ctrl_hw_t;
+
 typedef struct {
-    struct {
-        io_rw_32 status;
-        io_rw_32 ctrl;
-    } io[6];
+    ioqspi_status_ctrl_hw_t io[NUM_QSPI_GPIOS]; // 6
+
+    _REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR
+    // Raw Interrupts
+    // 0x00800000 [23]    : GPIO_QSPI_SD3_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO_QSPI_SD3_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO_QSPI_SD3_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO_QSPI_SD3_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO_QSPI_SD2_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO_QSPI_SD2_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO_QSPI_SD2_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO_QSPI_SD2_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO_QSPI_SD1_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO_QSPI_SD1_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO_QSPI_SD1_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO_QSPI_SD1_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO_QSPI_SD0_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO_QSPI_SD0_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO_QSPI_SD0_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO_QSPI_SD0_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO_QSPI_SS_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO_QSPI_SS_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO_QSPI_SS_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO_QSPI_SS_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO_QSPI_SCLK_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO_QSPI_SCLK_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO_QSPI_SCLK_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO_QSPI_SCLK_LEVEL_LOW (0)
+    io_rw_32 intr;
+
+    io_qspi_ctrl_hw_t proc0_qspi_ctrl;
+
+    io_qspi_ctrl_hw_t proc1_qspi_ctrl;
+
+    io_qspi_ctrl_hw_t dormant_wake_qspi_ctrl;
 } ioqspi_hw_t;
 
 #define ioqspi_hw ((ioqspi_hw_t *const)IO_QSPI_BASE)
 
+static_assert( NUM_QSPI_GPIOS == 6, "");
+
 #endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/mpu.h b/src/rp2040/hardware_structs/include/hardware/structs/mpu.h
index 34e5c39e8..e6472209b 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/mpu.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/mpu.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,11 +12,47 @@
 #include "hardware/address_mapped.h"
 #include "hardware/regs/m0plus.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE
+    // Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports
+    // 0x00ff0000 [23:16] : IREGION (0): Instruction region
+    // 0x0000ff00 [15:8]  : DREGION (0x8): Number of regions supported by the MPU
+    // 0x00000001 [0]     : SEPARATE (0): Indicates support for separate instruction and data address maps
     io_ro_32 type;
+
+    _REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL
+    // Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled...
+    // 0x00000004 [2]     : PRIVDEFENA (0): Controls whether the default memory map is enabled as a background region for...
+    // 0x00000002 [1]     : HFNMIENA (0): Controls the use of the MPU for HardFaults and NMIs
+    // 0x00000001 [0]     : ENABLE (0): Enables the MPU
     io_rw_32 ctrl;
+
+    _REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR
+    // Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR
+    // 0x0000000f [3:0]   : REGION (0): Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers
     io_rw_32 rnr;
+
+    _REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR
+    // Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR
+    // 0xffffff00 [31:8]  : ADDR (0): Base address of the region
+    // 0x00000010 [4]     : VALID (0): On writes, indicates whether the write must update the base address of the region...
+    // 0x0000000f [3:0]   : REGION (0): On writes, specifies the number of the region whose base address to update provided...
     io_rw_32 rbar;
+
+    _REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR
+    // Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region...
+    // 0xffff0000 [31:16] : ATTRS (0): The MPU Region Attribute field
+    // 0x0000ff00 [15:8]  : SRD (0): Subregion Disable
+    // 0x0000003e [5:1]   : SIZE (0): Indicates the region size
+    // 0x00000001 [0]     : ENABLE (0): Enables the region
     io_rw_32 rasr;
 } mpu_hw_t;
 
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h b/src/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h
index 451d7ebc3..8036cd940 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,14 +10,38 @@
 #define _HARDWARE_STRUCTS_PADS_QSPI_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/pads_qspi.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_qspi
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/pads_qspi.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(PADS_QSPI_VOLTAGE_SELECT_OFFSET) // PADS_QSPI_VOLTAGE_SELECT
+    // Voltage select
+    // 0x00000001 [0]     : VOLTAGE_SELECT (0)
     io_rw_32 voltage_select;
-    io_rw_32 io[6];
+
+    _REG_(PADS_QSPI_GPIO_QSPI_SCLK_OFFSET) // PADS_QSPI_GPIO_QSPI_SCLK
+    // (Description copied from array index 0 register PADS_QSPI_GPIO_QSPI_SCLK applies similarly to other array indexes)
+    //
+    // Pad control register
+    // 0x00000080 [7]     : OD (0): Output disable
+    // 0x00000040 [6]     : IE (1): Input enable
+    // 0x00000030 [5:4]   : DRIVE (1): Drive strength
+    // 0x00000008 [3]     : PUE (0): Pull up enable
+    // 0x00000004 [2]     : PDE (1): Pull down enable
+    // 0x00000002 [1]     : SCHMITT (1): Enable schmitt trigger
+    // 0x00000001 [0]     : SLEWFAST (0): Slew rate control
+    io_rw_32 io[NUM_QSPI_GPIOS]; // 6
 } pads_qspi_hw_t;
 
 #define pads_qspi_hw ((pads_qspi_hw_t *const)PADS_QSPI_BASE)
 
+static_assert( NUM_QSPI_GPIOS == 6, "");
+
 #endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/padsbank0.h b/src/rp2040/hardware_structs/include/hardware/structs/padsbank0.h
index f56dc4011..2c067fa95 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/padsbank0.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/padsbank0.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,14 +10,38 @@
 #define _HARDWARE_STRUCTS_PADSBANK0_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/pads_bank0.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_bank0
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/pads_bank0.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(PADS_BANK0_VOLTAGE_SELECT_OFFSET) // PADS_BANK0_VOLTAGE_SELECT
+    // Voltage select
+    // 0x00000001 [0]     : VOLTAGE_SELECT (0)
     io_rw_32 voltage_select;
-    io_rw_32 io[30];
+
+    _REG_(PADS_BANK0_GPIO0_OFFSET) // PADS_BANK0_GPIO0
+    // (Description copied from array index 0 register PADS_BANK0_GPIO0 applies similarly to other array indexes)
+    //
+    // Pad control register
+    // 0x00000080 [7]     : OD (0): Output disable
+    // 0x00000040 [6]     : IE (1): Input enable
+    // 0x00000030 [5:4]   : DRIVE (1): Drive strength
+    // 0x00000008 [3]     : PUE (0): Pull up enable
+    // 0x00000004 [2]     : PDE (1): Pull down enable
+    // 0x00000002 [1]     : SCHMITT (1): Enable schmitt trigger
+    // 0x00000001 [0]     : SLEWFAST (0): Slew rate control
+    io_rw_32 io[NUM_BANK0_GPIOS]; // 30
 } padsbank0_hw_t;
 
-#define padsbank0_hw ((padsbank0_hw_t *)PADS_BANK0_BASE)
+#define padsbank0_hw ((padsbank0_hw_t *const)PADS_BANK0_BASE)
+
+static_assert( NUM_BANK0_GPIOS == 30, "");
 
 #endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/pio.h b/src/rp2040/hardware_structs/include/hardware/structs/pio.h
index 176863bb4..515e4d1a0 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/pio.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/pio.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,41 +10,275 @@
 #define _HARDWARE_STRUCTS_PIO_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/pio.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pio
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/pio.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct pio_sm_hw {
+    _REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV
+    // Clock divisor register for state machine 0
+    // 0xffff0000 [31:16] : INT (1): Effective frequency is sysclk/(int + frac/256)
+    // 0x0000ff00 [15:8]  : FRAC (0): Fractional part of clock divisor
+    io_rw_32 clkdiv;
+
+    _REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL
+    // Execution/behavioural settings for state machine 0
+    // 0x80000000 [31]    : EXEC_STALLED (0): If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine
+    // 0x40000000 [30]    : SIDE_EN (0): If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable,...
+    // 0x20000000 [29]    : SIDE_PINDIR (0): If 1, side-set data is asserted to pin directions, instead of pin values
+    // 0x1f000000 [28:24] : JMP_PIN (0): The GPIO number to use as condition for JMP PIN
+    // 0x00f80000 [23:19] : OUT_EN_SEL (0): Which data bit to use for inline OUT enable
+    // 0x00040000 [18]    : INLINE_OUT_EN (0): If 1, use a bit of OUT data as an auxiliary write enable
+    // 0x00020000 [17]    : OUT_STICKY (0): Continuously assert the most recent OUT/SET to the pins
+    // 0x0001f000 [16:12] : WRAP_TOP (0x1f): After reaching this address, execution is wrapped to wrap_bottom
+    // 0x00000f80 [11:7]  : WRAP_BOTTOM (0): After reaching wrap_top, execution is wrapped to this address
+    // 0x00000010 [4]     : STATUS_SEL (0): Comparison used for the MOV x, STATUS instruction
+    // 0x0000000f [3:0]   : STATUS_N (0): Comparison level for the MOV x, STATUS instruction
+    io_rw_32 execctrl;
+
+    _REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL
+    // Control behaviour of the input/output shift registers for state machine 0
+    // 0x80000000 [31]    : FJOIN_RX (0): When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep
+    // 0x40000000 [30]    : FJOIN_TX (0): When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep
+    // 0x3e000000 [29:25] : PULL_THRESH (0): Number of bits shifted out of OSR before autopull, or conditional pull (PULL...
+    // 0x01f00000 [24:20] : PUSH_THRESH (0): Number of bits shifted into ISR before autopush, or conditional push (PUSH...
+    // 0x00080000 [19]    : OUT_SHIFTDIR (1): 1 = shift out of output shift register to right
+    // 0x00040000 [18]    : IN_SHIFTDIR (1): 1 = shift input shift register to right (data enters from left)
+    // 0x00020000 [17]    : AUTOPULL (0): Pull automatically when the output shift register is emptied, i
+    // 0x00010000 [16]    : AUTOPUSH (0): Push automatically when the input shift register is filled, i
+    io_rw_32 shiftctrl;
+
+    _REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR
+    // Current instruction address of state machine 0
+    // 0x0000001f [4:0]   : SM0_ADDR (0)
+    io_ro_32 addr;
+
+    _REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR
+    // Read to see the instruction currently addressed by state machine 0's program counter
+    // 0x0000ffff [15:0]  : SM0_INSTR (0)
+    io_rw_32 instr;
+
+    _REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL
+    // State machine pin control
+    // 0xe0000000 [31:29] : SIDESET_COUNT (0): The number of MSBs of the Delay/Side-set instruction field which are used...
+    // 0x1c000000 [28:26] : SET_COUNT (0x5): The number of pins asserted by a SET
+    // 0x03f00000 [25:20] : OUT_COUNT (0): The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction
+    // 0x000f8000 [19:15] : IN_BASE (0): The pin which is mapped to the least-significant bit of a state machine's IN data bus
+    // 0x00007c00 [14:10] : SIDESET_BASE (0): The lowest-numbered pin that will be affected by a side-set operation
+    // 0x000003e0 [9:5]   : SET_BASE (0): The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction
+    // 0x0000001f [4:0]   : OUT_BASE (0): The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV...
+    io_rw_32 pinctrl;
+} pio_sm_hw_t;
+
 typedef struct {
+    _REG_(PIO_CTRL_OFFSET) // PIO_CTRL
+    // PIO control register
+    // 0x00000f00 [11:8]  : CLKDIV_RESTART (0): Restart a state machine's clock divider from an initial phase of 0
+    // 0x000000f0 [7:4]   : SM_RESTART (0): Write 1 to instantly clear internal SM state which may be otherwise difficult...
+    // 0x0000000f [3:0]   : SM_ENABLE (0): Enable/disable each of the four state machines by writing 1/0 to each of these four bits
     io_rw_32 ctrl;
+
+    _REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT
+    // FIFO status register
+    // 0x0f000000 [27:24] : TXEMPTY (0xf): State machine TX FIFO is empty
+    // 0x000f0000 [19:16] : TXFULL (0): State machine TX FIFO is full
+    // 0x00000f00 [11:8]  : RXEMPTY (0xf): State machine RX FIFO is empty
+    // 0x0000000f [3:0]   : RXFULL (0): State machine RX FIFO is full
     io_ro_32 fstat;
+
+    _REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG
+    // FIFO debug register
+    // 0x0f000000 [27:24] : TXSTALL (0): State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with...
+    // 0x000f0000 [19:16] : TXOVER (0): TX FIFO overflow (i
+    // 0x00000f00 [11:8]  : RXUNDER (0): RX FIFO underflow (i
+    // 0x0000000f [3:0]   : RXSTALL (0): State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with...
     io_rw_32 fdebug;
+
+    _REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL
+    // FIFO levels
+    // 0xf0000000 [31:28] : RX3 (0)
+    // 0x0f000000 [27:24] : TX3 (0)
+    // 0x00f00000 [23:20] : RX2 (0)
+    // 0x000f0000 [19:16] : TX2 (0)
+    // 0x0000f000 [15:12] : RX1 (0)
+    // 0x00000f00 [11:8]  : TX1 (0)
+    // 0x000000f0 [7:4]   : RX0 (0)
+    // 0x0000000f [3:0]   : TX0 (0)
     io_ro_32 flevel;
-    io_wo_32 txf[NUM_PIO_STATE_MACHINES];
-    io_ro_32 rxf[NUM_PIO_STATE_MACHINES];
+
+    _REG_(PIO_TXF0_OFFSET) // PIO_TXF0
+    // (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes)
+    //
+    // Direct write access to the TX FIFO for this state machine
+    io_wo_32 txf[NUM_PIO_STATE_MACHINES]; // 4
+
+    _REG_(PIO_RXF0_OFFSET) // PIO_RXF0
+    // (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes)
+    //
+    // Direct read access to the RX FIFO for this state machine
+    io_ro_32 rxf[NUM_PIO_STATE_MACHINES]; // 4
+
+    _REG_(PIO_IRQ_OFFSET) // PIO_IRQ
+    // State machine IRQ flags register
+    // 0x000000ff [7:0]   : IRQ (0)
     io_rw_32 irq;
+
+    _REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE
+    // Writing a 1 to each of these bits will forcibly assert the corresponding IRQ
+    // 0x000000ff [7:0]   : IRQ_FORCE (0)
     io_wo_32 irq_force;
+
+    _REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS
+    // There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities
     io_rw_32 input_sync_bypass;
-    io_rw_32 dbg_padout;
-    io_rw_32 dbg_padoe;
-    io_rw_32 dbg_cfginfo;
-    io_wo_32 instr_mem[32];
-    struct pio_sm_hw {
-        io_rw_32 clkdiv;
-        io_rw_32 execctrl;
-        io_rw_32 shiftctrl;
-        io_ro_32 addr;
-        io_rw_32 instr;
-        io_rw_32 pinctrl;
-    } sm[NUM_PIO_STATE_MACHINES];
-    io_rw_32 intr;
+
+    _REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT
+    // Read to sample the pad output values PIO is currently driving to the GPIOs
+    io_ro_32 dbg_padout;
+
+    _REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE
+    // Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs
+    io_ro_32 dbg_padoe;
+
+    _REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO
+    // The PIO hardware has some free parameters that may vary between chip products
+    // 0x003f0000 [21:16] : IMEM_SIZE (0): The size of the instruction memory, measured in units of one instruction
+    // 0x00000f00 [11:8]  : SM_COUNT (0): The number of state machines this PIO instance is equipped with
+    // 0x0000003f [5:0]   : FIFO_DEPTH (0): The depth of the state machine TX/RX FIFOs, measured in words
+    io_ro_32 dbg_cfginfo;
+
+    _REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0
+    // (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes)
+    //
+    // Write-only access to instruction memory location 0
+    // 0x0000ffff [15:0]  : INSTR_MEM0 (0)
+    io_wo_32 instr_mem[PIO_INSTRUCTION_COUNT]; // 32
+
+    pio_sm_hw_t sm[NUM_PIO_STATE_MACHINES]; // 4
+
+    _REG_(PIO_INTR_OFFSET) // PIO_INTR
+    // Raw Interrupts
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
+    io_ro_32 intr;
+
+    _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE
+    // Interrupt Enable for irq0
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
     io_rw_32 inte0;
+
+    _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF
+    // Interrupt Force for irq0
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
     io_rw_32 intf0;
+
+    _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS
+    // Interrupt status after masking & forcing for irq0
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
     io_ro_32 ints0;
+
+    _REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE
+    // Interrupt Enable for irq1
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
     io_rw_32 inte1;
+
+    _REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF
+    // Interrupt Force for irq1
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
     io_rw_32 intf1;
+
+    _REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS
+    // Interrupt status after masking & forcing for irq1
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
     io_ro_32 ints1;
 } pio_hw_t;
 
 #define pio0_hw ((pio_hw_t *const)PIO0_BASE)
 #define pio1_hw ((pio_hw_t *const)PIO1_BASE)
 
+static_assert( NUM_PIO_STATE_MACHINES == 4, "");
+static_assert( PIO_INSTRUCTION_COUNT == 32, "");
+
 #endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/pll.h b/src/rp2040/hardware_structs/include/hardware/structs/pll.h
index 4d5b5b78c..5a506e3e9 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/pll.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/pll.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,11 +12,40 @@
 #include "hardware/address_mapped.h"
 #include "hardware/regs/pll.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pll
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/pll.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 /// \tag::pll_hw[]
 typedef struct {
+    _REG_(PLL_CS_OFFSET) // PLL_CS
+    // Control and Status
+    // 0x80000000 [31]    : LOCK (0): PLL is locked
+    // 0x00000100 [8]     : BYPASS (0): Passes the reference clock to the output instead of the divided VCO
+    // 0x0000003f [5:0]   : REFDIV (1): Divides the PLL input reference clock
     io_rw_32 cs;
+
+    _REG_(PLL_PWR_OFFSET) // PLL_PWR
+    // Controls the PLL power modes
+    // 0x00000020 [5]     : VCOPD (1): PLL VCO powerdown
+    // 0x00000008 [3]     : POSTDIVPD (1): PLL post divider powerdown
+    // 0x00000004 [2]     : DSMPD (1): PLL DSM powerdown
+    // 0x00000001 [0]     : PD (1): PLL powerdown
     io_rw_32 pwr;
+
+    _REG_(PLL_FBDIV_INT_OFFSET) // PLL_FBDIV_INT
+    // Feedback divisor
+    // 0x00000fff [11:0]  : FBDIV_INT (0): see ctrl reg description for constraints
     io_rw_32 fbdiv_int;
+
+    _REG_(PLL_PRIM_OFFSET) // PLL_PRIM
+    // Controls the PLL post dividers for the primary output
+    // 0x00070000 [18:16] : POSTDIV1 (0x7): divide by 1-7
+    // 0x00007000 [14:12] : POSTDIV2 (0x7): divide by 1-7
     io_rw_32 prim;
 } pll_hw_t;
 
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/psm.h b/src/rp2040/hardware_structs/include/hardware/structs/psm.h
index cc9fb97e0..cdfb2e385 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/psm.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/psm.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,14 +10,100 @@
 #define _HARDWARE_STRUCTS_PSM_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/psm.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_psm
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/psm.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(PSM_FRCE_ON_OFFSET) // PSM_FRCE_ON
+    // Force block out of reset (i
+    // 0x00010000 [16]    : proc1 (0)
+    // 0x00008000 [15]    : proc0 (0)
+    // 0x00004000 [14]    : sio (0)
+    // 0x00002000 [13]    : vreg_and_chip_reset (0)
+    // 0x00001000 [12]    : xip (0)
+    // 0x00000800 [11]    : sram5 (0)
+    // 0x00000400 [10]    : sram4 (0)
+    // 0x00000200 [9]     : sram3 (0)
+    // 0x00000100 [8]     : sram2 (0)
+    // 0x00000080 [7]     : sram1 (0)
+    // 0x00000040 [6]     : sram0 (0)
+    // 0x00000020 [5]     : rom (0)
+    // 0x00000010 [4]     : busfabric (0)
+    // 0x00000008 [3]     : resets (0)
+    // 0x00000004 [2]     : clocks (0)
+    // 0x00000002 [1]     : xosc (0)
+    // 0x00000001 [0]     : rosc (0)
     io_rw_32 frce_on;
+
+    _REG_(PSM_FRCE_OFF_OFFSET) // PSM_FRCE_OFF
+    // Force into reset (i
+    // 0x00010000 [16]    : proc1 (0)
+    // 0x00008000 [15]    : proc0 (0)
+    // 0x00004000 [14]    : sio (0)
+    // 0x00002000 [13]    : vreg_and_chip_reset (0)
+    // 0x00001000 [12]    : xip (0)
+    // 0x00000800 [11]    : sram5 (0)
+    // 0x00000400 [10]    : sram4 (0)
+    // 0x00000200 [9]     : sram3 (0)
+    // 0x00000100 [8]     : sram2 (0)
+    // 0x00000080 [7]     : sram1 (0)
+    // 0x00000040 [6]     : sram0 (0)
+    // 0x00000020 [5]     : rom (0)
+    // 0x00000010 [4]     : busfabric (0)
+    // 0x00000008 [3]     : resets (0)
+    // 0x00000004 [2]     : clocks (0)
+    // 0x00000002 [1]     : xosc (0)
+    // 0x00000001 [0]     : rosc (0)
     io_rw_32 frce_off;
+
+    _REG_(PSM_WDSEL_OFFSET) // PSM_WDSEL
+    // Set to 1 if this peripheral should be reset when the watchdog fires
+    // 0x00010000 [16]    : proc1 (0)
+    // 0x00008000 [15]    : proc0 (0)
+    // 0x00004000 [14]    : sio (0)
+    // 0x00002000 [13]    : vreg_and_chip_reset (0)
+    // 0x00001000 [12]    : xip (0)
+    // 0x00000800 [11]    : sram5 (0)
+    // 0x00000400 [10]    : sram4 (0)
+    // 0x00000200 [9]     : sram3 (0)
+    // 0x00000100 [8]     : sram2 (0)
+    // 0x00000080 [7]     : sram1 (0)
+    // 0x00000040 [6]     : sram0 (0)
+    // 0x00000020 [5]     : rom (0)
+    // 0x00000010 [4]     : busfabric (0)
+    // 0x00000008 [3]     : resets (0)
+    // 0x00000004 [2]     : clocks (0)
+    // 0x00000002 [1]     : xosc (0)
+    // 0x00000001 [0]     : rosc (0)
     io_rw_32 wdsel;
-    io_rw_32 done;
+
+    _REG_(PSM_DONE_OFFSET) // PSM_DONE
+    // Indicates the peripheral's registers are ready to access
+    // 0x00010000 [16]    : proc1 (0)
+    // 0x00008000 [15]    : proc0 (0)
+    // 0x00004000 [14]    : sio (0)
+    // 0x00002000 [13]    : vreg_and_chip_reset (0)
+    // 0x00001000 [12]    : xip (0)
+    // 0x00000800 [11]    : sram5 (0)
+    // 0x00000400 [10]    : sram4 (0)
+    // 0x00000200 [9]     : sram3 (0)
+    // 0x00000100 [8]     : sram2 (0)
+    // 0x00000080 [7]     : sram1 (0)
+    // 0x00000040 [6]     : sram0 (0)
+    // 0x00000020 [5]     : rom (0)
+    // 0x00000010 [4]     : busfabric (0)
+    // 0x00000008 [3]     : resets (0)
+    // 0x00000004 [2]     : clocks (0)
+    // 0x00000002 [1]     : xosc (0)
+    // 0x00000001 [0]     : rosc (0)
+    io_ro_32 done;
 } psm_hw_t;
 
 #define psm_hw ((psm_hw_t *const)PSM_BASE)
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/pwm.h b/src/rp2040/hardware_structs/include/hardware/structs/pwm.h
index 549956109..fd9a75ca2 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/pwm.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/pwm.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,26 +10,117 @@
 #define _HARDWARE_STRUCTS_PWM_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/pwm.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pwm
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/pwm.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct pwm_slice_hw {
+    _REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR
+    // Control and status register
+    // 0x00000080 [7]     : PH_ADV (0): Advance the phase of the counter by 1 count, while it is running
+    // 0x00000040 [6]     : PH_RET (0): Retard the phase of the counter by 1 count, while it is running
+    // 0x00000030 [5:4]   : DIVMODE (0)
+    // 0x00000008 [3]     : B_INV (0): Invert output B
+    // 0x00000004 [2]     : A_INV (0): Invert output A
+    // 0x00000002 [1]     : PH_CORRECT (0): 1: Enable phase-correct modulation
+    // 0x00000001 [0]     : EN (0): Enable the PWM channel
     io_rw_32 csr;
+
+    _REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV
+    // INT and FRAC form a fixed-point fractional number
+    // 0x00000ff0 [11:4]  : INT (1)
+    // 0x0000000f [3:0]   : FRAC (0)
     io_rw_32 div;
+
+    _REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR
+    // Direct access to the PWM counter
+    // 0x0000ffff [15:0]  : CH0_CTR (0)
     io_rw_32 ctr;
+
+    _REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC
+    // Counter compare values
+    // 0xffff0000 [31:16] : B (0)
+    // 0x0000ffff [15:0]  : A (0)
     io_rw_32 cc;
+
+    _REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP
+    // Counter wrap value
+    // 0x0000ffff [15:0]  : CH0_TOP (0xffff)
     io_rw_32 top;
 } pwm_slice_hw_t;
 
 typedef struct {
-    pwm_slice_hw_t slice[NUM_PWM_SLICES];
+    pwm_slice_hw_t slice[NUM_PWM_SLICES]; // 8
+
+    _REG_(PWM_EN_OFFSET) // PWM_EN
+    // This register aliases the CSR_EN bits for all channels
+    // 0x00000080 [7]     : CH7 (0)
+    // 0x00000040 [6]     : CH6 (0)
+    // 0x00000020 [5]     : CH5 (0)
+    // 0x00000010 [4]     : CH4 (0)
+    // 0x00000008 [3]     : CH3 (0)
+    // 0x00000004 [2]     : CH2 (0)
+    // 0x00000002 [1]     : CH1 (0)
+    // 0x00000001 [0]     : CH0 (0)
     io_rw_32 en;
+
+    _REG_(PWM_INTR_OFFSET) // PWM_INTR
+    // Raw Interrupts
+    // 0x00000080 [7]     : CH7 (0)
+    // 0x00000040 [6]     : CH6 (0)
+    // 0x00000020 [5]     : CH5 (0)
+    // 0x00000010 [4]     : CH4 (0)
+    // 0x00000008 [3]     : CH3 (0)
+    // 0x00000004 [2]     : CH2 (0)
+    // 0x00000002 [1]     : CH1 (0)
+    // 0x00000001 [0]     : CH0 (0)
     io_rw_32 intr;
+
+    _REG_(PWM_INTE_OFFSET) // PWM_INTE
+    // Interrupt Enable
+    // 0x00000080 [7]     : CH7 (0)
+    // 0x00000040 [6]     : CH6 (0)
+    // 0x00000020 [5]     : CH5 (0)
+    // 0x00000010 [4]     : CH4 (0)
+    // 0x00000008 [3]     : CH3 (0)
+    // 0x00000004 [2]     : CH2 (0)
+    // 0x00000002 [1]     : CH1 (0)
+    // 0x00000001 [0]     : CH0 (0)
     io_rw_32 inte;
+
+    _REG_(PWM_INTF_OFFSET) // PWM_INTF
+    // Interrupt Force
+    // 0x00000080 [7]     : CH7 (0)
+    // 0x00000040 [6]     : CH6 (0)
+    // 0x00000020 [5]     : CH5 (0)
+    // 0x00000010 [4]     : CH4 (0)
+    // 0x00000008 [3]     : CH3 (0)
+    // 0x00000004 [2]     : CH2 (0)
+    // 0x00000002 [1]     : CH1 (0)
+    // 0x00000001 [0]     : CH0 (0)
     io_rw_32 intf;
-    io_rw_32 ints;
+
+    _REG_(PWM_INTS_OFFSET) // PWM_INTS
+    // Interrupt status after masking & forcing
+    // 0x00000080 [7]     : CH7 (0)
+    // 0x00000040 [6]     : CH6 (0)
+    // 0x00000020 [5]     : CH5 (0)
+    // 0x00000010 [4]     : CH4 (0)
+    // 0x00000008 [3]     : CH3 (0)
+    // 0x00000004 [2]     : CH2 (0)
+    // 0x00000002 [1]     : CH1 (0)
+    // 0x00000001 [0]     : CH0 (0)
+    io_ro_32 ints;
 } pwm_hw_t;
 
 #define pwm_hw ((pwm_hw_t *const)PWM_BASE)
 
+static_assert( NUM_PWM_SLICES == 8, "");
+
 #endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/resets.h b/src/rp2040/hardware_structs/include/hardware/structs/resets.h
index a96ddebd7..bc1c10c5e 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/resets.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/resets.h
@@ -1,19 +1,113 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
+
 #ifndef _HARDWARE_STRUCTS_RESETS_H
 #define _HARDWARE_STRUCTS_RESETS_H
 
 #include "hardware/address_mapped.h"
 #include "hardware/regs/resets.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_resets
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/resets.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 /// \tag::resets_hw[]
 typedef struct {
+    _REG_(RESETS_RESET_OFFSET) // RESETS_RESET
+    // Reset control
+    // 0x01000000 [24]    : usbctrl (1)
+    // 0x00800000 [23]    : uart1 (1)
+    // 0x00400000 [22]    : uart0 (1)
+    // 0x00200000 [21]    : timer (1)
+    // 0x00100000 [20]    : tbman (1)
+    // 0x00080000 [19]    : sysinfo (1)
+    // 0x00040000 [18]    : syscfg (1)
+    // 0x00020000 [17]    : spi1 (1)
+    // 0x00010000 [16]    : spi0 (1)
+    // 0x00008000 [15]    : rtc (1)
+    // 0x00004000 [14]    : pwm (1)
+    // 0x00002000 [13]    : pll_usb (1)
+    // 0x00001000 [12]    : pll_sys (1)
+    // 0x00000800 [11]    : pio1 (1)
+    // 0x00000400 [10]    : pio0 (1)
+    // 0x00000200 [9]     : pads_qspi (1)
+    // 0x00000100 [8]     : pads_bank0 (1)
+    // 0x00000080 [7]     : jtag (1)
+    // 0x00000040 [6]     : io_qspi (1)
+    // 0x00000020 [5]     : io_bank0 (1)
+    // 0x00000010 [4]     : i2c1 (1)
+    // 0x00000008 [3]     : i2c0 (1)
+    // 0x00000004 [2]     : dma (1)
+    // 0x00000002 [1]     : busctrl (1)
+    // 0x00000001 [0]     : adc (1)
     io_rw_32 reset;
+
+    _REG_(RESETS_WDSEL_OFFSET) // RESETS_WDSEL
+    // Watchdog select
+    // 0x01000000 [24]    : usbctrl (0)
+    // 0x00800000 [23]    : uart1 (0)
+    // 0x00400000 [22]    : uart0 (0)
+    // 0x00200000 [21]    : timer (0)
+    // 0x00100000 [20]    : tbman (0)
+    // 0x00080000 [19]    : sysinfo (0)
+    // 0x00040000 [18]    : syscfg (0)
+    // 0x00020000 [17]    : spi1 (0)
+    // 0x00010000 [16]    : spi0 (0)
+    // 0x00008000 [15]    : rtc (0)
+    // 0x00004000 [14]    : pwm (0)
+    // 0x00002000 [13]    : pll_usb (0)
+    // 0x00001000 [12]    : pll_sys (0)
+    // 0x00000800 [11]    : pio1 (0)
+    // 0x00000400 [10]    : pio0 (0)
+    // 0x00000200 [9]     : pads_qspi (0)
+    // 0x00000100 [8]     : pads_bank0 (0)
+    // 0x00000080 [7]     : jtag (0)
+    // 0x00000040 [6]     : io_qspi (0)
+    // 0x00000020 [5]     : io_bank0 (0)
+    // 0x00000010 [4]     : i2c1 (0)
+    // 0x00000008 [3]     : i2c0 (0)
+    // 0x00000004 [2]     : dma (0)
+    // 0x00000002 [1]     : busctrl (0)
+    // 0x00000001 [0]     : adc (0)
     io_rw_32 wdsel;
-    io_rw_32 reset_done;
+
+    _REG_(RESETS_RESET_DONE_OFFSET) // RESETS_RESET_DONE
+    // Reset done
+    // 0x01000000 [24]    : usbctrl (0)
+    // 0x00800000 [23]    : uart1 (0)
+    // 0x00400000 [22]    : uart0 (0)
+    // 0x00200000 [21]    : timer (0)
+    // 0x00100000 [20]    : tbman (0)
+    // 0x00080000 [19]    : sysinfo (0)
+    // 0x00040000 [18]    : syscfg (0)
+    // 0x00020000 [17]    : spi1 (0)
+    // 0x00010000 [16]    : spi0 (0)
+    // 0x00008000 [15]    : rtc (0)
+    // 0x00004000 [14]    : pwm (0)
+    // 0x00002000 [13]    : pll_usb (0)
+    // 0x00001000 [12]    : pll_sys (0)
+    // 0x00000800 [11]    : pio1 (0)
+    // 0x00000400 [10]    : pio0 (0)
+    // 0x00000200 [9]     : pads_qspi (0)
+    // 0x00000100 [8]     : pads_bank0 (0)
+    // 0x00000080 [7]     : jtag (0)
+    // 0x00000040 [6]     : io_qspi (0)
+    // 0x00000020 [5]     : io_bank0 (0)
+    // 0x00000010 [4]     : i2c1 (0)
+    // 0x00000008 [3]     : i2c0 (0)
+    // 0x00000004 [2]     : dma (0)
+    // 0x00000002 [1]     : busctrl (0)
+    // 0x00000001 [0]     : adc (0)
+    io_ro_32 reset_done;
 } resets_hw_t;
 
 #define resets_hw ((resets_hw_t *const)RESETS_BASE)
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/rosc.h b/src/rp2040/hardware_structs/include/hardware/structs/rosc.h
index 10543937c..114c6029f 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/rosc.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/rosc.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,20 +10,75 @@
 #define _HARDWARE_STRUCTS_ROSC_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/rosc.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rosc
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/rosc.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL
+    // Ring Oscillator control
+    // 0x00fff000 [23:12] : ENABLE (0): On power-up this field is initialised to ENABLE
+    // 0x00000fff [11:0]  : FREQ_RANGE (0xaa0): Controls the number of delay stages in the ROSC ring
     io_rw_32 ctrl;
+
+    _REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA
+    // The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage
+    // 0xffff0000 [31:16] : PASSWD (0): Set to 0x9696 to apply the settings
+    // 0x00007000 [14:12] : DS3 (0): Stage 3 drive strength
+    // 0x00000700 [10:8]  : DS2 (0): Stage 2 drive strength
+    // 0x00000070 [6:4]   : DS1 (0): Stage 1 drive strength
+    // 0x00000007 [2:0]   : DS0 (0): Stage 0 drive strength
     io_rw_32 freqa;
+
+    _REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB
+    // For a detailed description see freqa register
+    // 0xffff0000 [31:16] : PASSWD (0): Set to 0x9696 to apply the settings
+    // 0x00007000 [14:12] : DS7 (0): Stage 7 drive strength
+    // 0x00000700 [10:8]  : DS6 (0): Stage 6 drive strength
+    // 0x00000070 [6:4]   : DS5 (0): Stage 5 drive strength
+    // 0x00000007 [2:0]   : DS4 (0): Stage 4 drive strength
     io_rw_32 freqb;
+
+    _REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT
+    // Ring Oscillator pause control
     io_rw_32 dormant;
+
+    _REG_(ROSC_DIV_OFFSET) // ROSC_DIV
+    // Controls the output divider
+    // 0x00000fff [11:0]  : DIV (0): set to 0xaa0 + div where
     io_rw_32 div;
+
+    _REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE
+    // Controls the phase shifted output
+    // 0x00000ff0 [11:4]  : PASSWD (0): set to 0xaa
+    // 0x00000008 [3]     : ENABLE (1): enable the phase-shifted output
+    // 0x00000004 [2]     : FLIP (0): invert the phase-shifted output
+    // 0x00000003 [1:0]   : SHIFT (0): phase shift the phase-shifted output by SHIFT input clocks
     io_rw_32 phase;
+
+    _REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS
+    // Ring Oscillator Status
+    // 0x80000000 [31]    : STABLE (0): Oscillator is running and stable
+    // 0x01000000 [24]    : BADWRITE (0): An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or...
+    // 0x00010000 [16]    : DIV_RUNNING (0): post-divider is running
+    // 0x00001000 [12]    : ENABLED (0): Oscillator is enabled but not necessarily running and stable
     io_rw_32 status;
-    io_rw_32 randombit;
+
+    _REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT
+    // This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or...
+    // 0x00000001 [0]     : RANDOMBIT (1)
+    io_ro_32 randombit;
+
+    _REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT
+    // A down counter running at the ROSC frequency which counts to zero and stops
+    // 0x000000ff [7:0]   : COUNT (0)
     io_rw_32 count;
-    io_rw_32 dftx;
 } rosc_hw_t;
 
 #define rosc_hw ((rosc_hw_t *const)ROSC_BASE)
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/rtc.h b/src/rp2040/hardware_structs/include/hardware/structs/rtc.h
index 276bd7a24..794a0e07a 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/rtc.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/rtc.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,22 +10,103 @@
 #define _HARDWARE_STRUCTS_RTC_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/rtc.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rtc
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/rtc.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(RTC_CLKDIV_M1_OFFSET) // RTC_CLKDIV_M1
+    // Divider minus 1 for the 1 second counter
+    // 0x0000ffff [15:0]  : CLKDIV_M1 (0)
     io_rw_32 clkdiv_m1;
+
+    _REG_(RTC_SETUP_0_OFFSET) // RTC_SETUP_0
+    // RTC setup register 0
+    // 0x00fff000 [23:12] : YEAR (0): Year
+    // 0x00000f00 [11:8]  : MONTH (0): Month (1
+    // 0x0000001f [4:0]   : DAY (0): Day of the month (1
     io_rw_32 setup_0;
+
+    _REG_(RTC_SETUP_1_OFFSET) // RTC_SETUP_1
+    // RTC setup register 1
+    // 0x07000000 [26:24] : DOTW (0): Day of the week: 1-Monday
+    // 0x001f0000 [20:16] : HOUR (0): Hours
+    // 0x00003f00 [13:8]  : MIN (0): Minutes
+    // 0x0000003f [5:0]   : SEC (0): Seconds
     io_rw_32 setup_1;
+
+    _REG_(RTC_CTRL_OFFSET) // RTC_CTRL
+    // RTC Control and status
+    // 0x00000100 [8]     : FORCE_NOTLEAPYEAR (0): If set, leapyear is forced off
+    // 0x00000010 [4]     : LOAD (0): Load RTC
+    // 0x00000002 [1]     : RTC_ACTIVE (0): RTC enabled (running)
+    // 0x00000001 [0]     : RTC_ENABLE (0): Enable RTC
     io_rw_32 ctrl;
+
+    _REG_(RTC_IRQ_SETUP_0_OFFSET) // RTC_IRQ_SETUP_0
+    // Interrupt setup register 0
+    // 0x20000000 [29]    : MATCH_ACTIVE (0)
+    // 0x10000000 [28]    : MATCH_ENA (0): Global match enable
+    // 0x04000000 [26]    : YEAR_ENA (0): Enable year matching
+    // 0x02000000 [25]    : MONTH_ENA (0): Enable month matching
+    // 0x01000000 [24]    : DAY_ENA (0): Enable day matching
+    // 0x00fff000 [23:12] : YEAR (0): Year
+    // 0x00000f00 [11:8]  : MONTH (0): Month (1
+    // 0x0000001f [4:0]   : DAY (0): Day of the month (1
     io_rw_32 irq_setup_0;
+
+    _REG_(RTC_IRQ_SETUP_1_OFFSET) // RTC_IRQ_SETUP_1
+    // Interrupt setup register 1
+    // 0x80000000 [31]    : DOTW_ENA (0): Enable day of the week matching
+    // 0x40000000 [30]    : HOUR_ENA (0): Enable hour matching
+    // 0x20000000 [29]    : MIN_ENA (0): Enable minute matching
+    // 0x10000000 [28]    : SEC_ENA (0): Enable second matching
+    // 0x07000000 [26:24] : DOTW (0): Day of the week
+    // 0x001f0000 [20:16] : HOUR (0): Hours
+    // 0x00003f00 [13:8]  : MIN (0): Minutes
+    // 0x0000003f [5:0]   : SEC (0): Seconds
     io_rw_32 irq_setup_1;
-    io_rw_32 rtc_1;
-    io_rw_32 rtc_0;
-    io_rw_32 intr;
+
+    _REG_(RTC_RTC_1_OFFSET) // RTC_RTC_1
+    // RTC register 1
+    // 0x00fff000 [23:12] : YEAR (0): Year
+    // 0x00000f00 [11:8]  : MONTH (0): Month (1
+    // 0x0000001f [4:0]   : DAY (0): Day of the month (1
+    io_ro_32 rtc_1;
+
+    _REG_(RTC_RTC_0_OFFSET) // RTC_RTC_0
+    // RTC register 0
+    // 0x07000000 [26:24] : DOTW (0): Day of the week
+    // 0x001f0000 [20:16] : HOUR (0): Hours
+    // 0x00003f00 [13:8]  : MIN (0): Minutes
+    // 0x0000003f [5:0]   : SEC (0): Seconds
+    io_ro_32 rtc_0;
+
+    _REG_(RTC_INTR_OFFSET) // RTC_INTR
+    // Raw Interrupts
+    // 0x00000001 [0]     : RTC (0)
+    io_ro_32 intr;
+
+    _REG_(RTC_INTE_OFFSET) // RTC_INTE
+    // Interrupt Enable
+    // 0x00000001 [0]     : RTC (0)
     io_rw_32 inte;
+
+    _REG_(RTC_INTF_OFFSET) // RTC_INTF
+    // Interrupt Force
+    // 0x00000001 [0]     : RTC (0)
     io_rw_32 intf;
-    io_rw_32 ints;
+
+    _REG_(RTC_INTS_OFFSET) // RTC_INTS
+    // Interrupt status after masking & forcing
+    // 0x00000001 [0]     : RTC (0)
+    io_ro_32 ints;
 } rtc_hw_t;
 
 #define rtc_hw ((rtc_hw_t *const)RTC_BASE)
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/scb.h b/src/rp2040/hardware_structs/include/hardware/structs/scb.h
index b48a87254..42569c7e9 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/scb.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/scb.h
@@ -1,22 +1,67 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
+
 #ifndef _HARDWARE_STRUCTS_SCB_H
 #define _HARDWARE_STRUCTS_SCB_H
 
 #include "hardware/address_mapped.h"
 #include "hardware/regs/m0plus.h"
 
-// SCB == System Control Block
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID
+    // Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor...
+    // 0xff000000 [31:24] : IMPLEMENTER (0x41): Implementor code: 0x41 = ARM
+    // 0x00f00000 [23:20] : VARIANT (0): Major revision number n in the rnpm revision status:
+    // 0x000f0000 [19:16] : ARCHITECTURE (0xc): Constant that defines the architecture of the processor:
+    // 0x0000fff0 [15:4]  : PARTNO (0xc60): Number of processor within family: 0xC60 = Cortex-M0+
+    // 0x0000000f [3:0]   : REVISION (1): Minor revision number m in the rnpm revision status:
     io_ro_32 cpuid;
+
+    _REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR
+    // Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending...
+    // 0x80000000 [31]    : NMIPENDSET (0): Setting this bit will activate an NMI
+    // 0x10000000 [28]    : PENDSVSET (0): PendSV set-pending bit
+    // 0x08000000 [27]    : PENDSVCLR (0): PendSV clear-pending bit
+    // 0x04000000 [26]    : PENDSTSET (0): SysTick exception set-pending bit
+    // 0x02000000 [25]    : PENDSTCLR (0): SysTick exception clear-pending bit
+    // 0x00800000 [23]    : ISRPREEMPT (0): The system can only access this bit when the core is halted
+    // 0x00400000 [22]    : ISRPENDING (0): External interrupt pending flag
+    // 0x001ff000 [20:12] : VECTPENDING (0): Indicates the exception number for the highest priority pending exception: 0 =...
+    // 0x000001ff [8:0]   : VECTACTIVE (0): Active exception number field
     io_rw_32 icsr;
+
+    _REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR
+    // The VTOR holds the vector table offset address
+    // 0xffffff00 [31:8]  : TBLOFF (0): Bits [31:8] of the indicate the vector table offset address
     io_rw_32 vtor;
+
+    _REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR
+    // Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state...
+    // 0xffff0000 [31:16] : VECTKEY (0): Register key:
+    // 0x00008000 [15]    : ENDIANESS (0): Data endianness implemented:
+    // 0x00000004 [2]     : SYSRESETREQ (0): Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be...
+    // 0x00000002 [1]     : VECTCLRACTIVE (0): Clears all active state information for fixed and configurable exceptions
     io_rw_32 aircr;
+
+    _REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR
+    // System Control Register
+    // 0x00000010 [4]     : SEVONPEND (0): Send Event on Pending bit:
+    // 0x00000004 [2]     : SLEEPDEEP (0): Controls whether the processor uses sleep or deep sleep as its low power mode:
+    // 0x00000002 [1]     : SLEEPONEXIT (0): Indicates sleep-on-exit when returning from Handler mode to Thread mode:
     io_rw_32 scr;
-    // ...
 } armv6m_scb_t;
 
 #define scb_hw ((armv6m_scb_t *const)(PPB_BASE + M0PLUS_CPUID_OFFSET))
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/sio.h b/src/rp2040/hardware_structs/include/hardware/structs/sio.h
index bc277afca..00b7e7e89 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/sio.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/sio.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,51 +13,164 @@
 #include "hardware/regs/sio.h"
 #include "hardware/structs/interp.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(SIO_CPUID_OFFSET) // SIO_CPUID
+    // Processor core identifier
     io_ro_32 cpuid;
+
+    _REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN
+    // Input value for GPIO pins
+    // 0x3fffffff [29:0]  : GPIO_IN (0): Input value for GPIO0
     io_ro_32 gpio_in;
+
+    _REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN
+    // Input value for QSPI pins
+    // 0x0000003f [5:0]   : GPIO_HI_IN (0): Input value on QSPI IO in order 0
     io_ro_32 gpio_hi_in;
-    uint32_t _pad;
 
+    uint32_t _pad0;
+
+    _REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT
+    // GPIO output value
+    // 0x3fffffff [29:0]  : GPIO_OUT (0): Set output level (1/0 -> high/low) for GPIO0
     io_rw_32 gpio_out;
+
+    _REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET
+    // GPIO output value set
+    // 0x3fffffff [29:0]  : GPIO_OUT_SET (0): Perform an atomic bit-set on GPIO_OUT, i
     io_wo_32 gpio_set;
+
+    _REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR
+    // GPIO output value clear
+    // 0x3fffffff [29:0]  : GPIO_OUT_CLR (0): Perform an atomic bit-clear on GPIO_OUT, i
     io_wo_32 gpio_clr;
+
+    _REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR
+    // GPIO output value XOR
+    // 0x3fffffff [29:0]  : GPIO_OUT_XOR (0): Perform an atomic bitwise XOR on GPIO_OUT, i
     io_wo_32 gpio_togl;
 
-    io_wo_32 gpio_oe;
+    _REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE
+    // GPIO output enable
+    // 0x3fffffff [29:0]  : GPIO_OE (0): Set output enable (1/0 -> output/input) for GPIO0
+    io_rw_32 gpio_oe;
+
+    _REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET
+    // GPIO output enable set
+    // 0x3fffffff [29:0]  : GPIO_OE_SET (0): Perform an atomic bit-set on GPIO_OE, i
     io_wo_32 gpio_oe_set;
+
+    _REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR
+    // GPIO output enable clear
+    // 0x3fffffff [29:0]  : GPIO_OE_CLR (0): Perform an atomic bit-clear on GPIO_OE, i
     io_wo_32 gpio_oe_clr;
+
+    _REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR
+    // GPIO output enable XOR
+    // 0x3fffffff [29:0]  : GPIO_OE_XOR (0): Perform an atomic bitwise XOR on GPIO_OE, i
     io_wo_32 gpio_oe_togl;
 
+    _REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT
+    // QSPI output value
+    // 0x0000003f [5:0]   : GPIO_HI_OUT (0): Set output level (1/0 -> high/low) for QSPI IO0
     io_rw_32 gpio_hi_out;
+
+    _REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET
+    // QSPI output value set
+    // 0x0000003f [5:0]   : GPIO_HI_OUT_SET (0): Perform an atomic bit-set on GPIO_HI_OUT, i
     io_wo_32 gpio_hi_set;
+
+    _REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR
+    // QSPI output value clear
+    // 0x0000003f [5:0]   : GPIO_HI_OUT_CLR (0): Perform an atomic bit-clear on GPIO_HI_OUT, i
     io_wo_32 gpio_hi_clr;
+
+    _REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR
+    // QSPI output value XOR
+    // 0x0000003f [5:0]   : GPIO_HI_OUT_XOR (0): Perform an atomic bitwise XOR on GPIO_HI_OUT, i
     io_wo_32 gpio_hi_togl;
 
-    io_wo_32 gpio_hi_oe;
+    _REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE
+    // QSPI output enable
+    // 0x0000003f [5:0]   : GPIO_HI_OE (0): Set output enable (1/0 -> output/input) for QSPI IO0
+    io_rw_32 gpio_hi_oe;
+
+    _REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET
+    // QSPI output enable set
+    // 0x0000003f [5:0]   : GPIO_HI_OE_SET (0): Perform an atomic bit-set on GPIO_HI_OE, i
     io_wo_32 gpio_hi_oe_set;
+
+    _REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR
+    // QSPI output enable clear
+    // 0x0000003f [5:0]   : GPIO_HI_OE_CLR (0): Perform an atomic bit-clear on GPIO_HI_OE, i
     io_wo_32 gpio_hi_oe_clr;
+
+    _REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR
+    // QSPI output enable XOR
+    // 0x0000003f [5:0]   : GPIO_HI_OE_XOR (0): Perform an atomic bitwise XOR on GPIO_HI_OE, i
     io_wo_32 gpio_hi_oe_togl;
 
+    _REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST
+    // Status register for inter-core FIFOs (mailboxes)
+    // 0x00000008 [3]     : ROE (0): Sticky flag indicating the RX FIFO was read when empty
+    // 0x00000004 [2]     : WOF (0): Sticky flag indicating the TX FIFO was written when full
+    // 0x00000002 [1]     : RDY (1): Value is 1 if this core's TX FIFO is not full (i
+    // 0x00000001 [0]     : VLD (0): Value is 1 if this core's RX FIFO is not empty (i
     io_rw_32 fifo_st;
+
+    _REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR
+    // Write access to this core's TX FIFO
     io_wo_32 fifo_wr;
+
+    _REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD
+    // Read access to this core's RX FIFO
     io_ro_32 fifo_rd;
+
+    _REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST
+    // Spinlock state
     io_ro_32 spinlock_st;
 
+    _REG_(SIO_DIV_UDIVIDEND_OFFSET) // SIO_DIV_UDIVIDEND
+    // Divider unsigned dividend
     io_rw_32 div_udividend;
+
+    _REG_(SIO_DIV_UDIVISOR_OFFSET) // SIO_DIV_UDIVISOR
+    // Divider unsigned divisor
     io_rw_32 div_udivisor;
+
+    _REG_(SIO_DIV_SDIVIDEND_OFFSET) // SIO_DIV_SDIVIDEND
+    // Divider signed dividend
     io_rw_32 div_sdividend;
+
+    _REG_(SIO_DIV_SDIVISOR_OFFSET) // SIO_DIV_SDIVISOR
+    // Divider signed divisor
     io_rw_32 div_sdivisor;
 
+    _REG_(SIO_DIV_QUOTIENT_OFFSET) // SIO_DIV_QUOTIENT
+    // Divider result quotient
     io_rw_32 div_quotient;
-    io_rw_32 div_remainder;
-    io_rw_32 div_csr;
 
-    uint32_t _pad2;
+    _REG_(SIO_DIV_REMAINDER_OFFSET) // SIO_DIV_REMAINDER
+    // Divider result remainder
+    io_rw_32 div_remainder;
 
+    _REG_(SIO_DIV_CSR_OFFSET) // SIO_DIV_CSR
+    // Control and status register for divider
+    // 0x00000002 [1]     : DIRTY (0): Changes to 1 when any register is written, and back to 0 when QUOTIENT is read
+    // 0x00000001 [0]     : READY (1): Reads as 0 when a calculation is in progress, 1 otherwise
+    io_ro_32 div_csr;
+    uint32_t _pad1;
     interp_hw_t interp[2];
 } sio_hw_t;
 
-#define sio_hw ((sio_hw_t *)SIO_BASE)
+#define sio_hw ((sio_hw_t *const)SIO_BASE)
 
 #endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/spi.h b/src/rp2040/hardware_structs/include/hardware/structs/spi.h
index 5b3b2bab5..f7fffb83c 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/spi.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/spi.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,16 +12,85 @@
 #include "hardware/address_mapped.h"
 #include "hardware/regs/spi.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_spi
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/spi.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(SPI_SSPCR0_OFFSET) // SPI_SSPCR0
+    // Control register 0, SSPCR0 on page 3-4
+    // 0x0000ff00 [15:8]  : SCR (0): Serial clock rate
+    // 0x00000080 [7]     : SPH (0): SSPCLKOUT phase, applicable to Motorola SPI frame format only
+    // 0x00000040 [6]     : SPO (0): SSPCLKOUT polarity, applicable to Motorola SPI frame format only
+    // 0x00000030 [5:4]   : FRF (0): Frame format: 00 Motorola SPI frame format
+    // 0x0000000f [3:0]   : DSS (0): Data Size Select: 0000 Reserved, undefined operation
     io_rw_32 cr0;
+
+    _REG_(SPI_SSPCR1_OFFSET) // SPI_SSPCR1
+    // Control register 1, SSPCR1 on page 3-5
+    // 0x00000008 [3]     : SOD (0): Slave-mode output disable
+    // 0x00000004 [2]     : MS (0): Master or slave mode select
+    // 0x00000002 [1]     : SSE (0): Synchronous serial port enable: 0 SSP operation disabled
+    // 0x00000001 [0]     : LBM (0): Loop back mode: 0 Normal serial port operation enabled
     io_rw_32 cr1;
+
+    _REG_(SPI_SSPDR_OFFSET) // SPI_SSPDR
+    // Data register, SSPDR on page 3-6
+    // 0x0000ffff [15:0]  : DATA (0): Transmit/Receive FIFO: Read Receive FIFO
     io_rw_32 dr;
-    io_rw_32 sr;
+
+    _REG_(SPI_SSPSR_OFFSET) // SPI_SSPSR
+    // Status register, SSPSR on page 3-7
+    // 0x00000010 [4]     : BSY (0): PrimeCell SSP busy flag, RO: 0 SSP is idle
+    // 0x00000008 [3]     : RFF (0): Receive FIFO full, RO: 0 Receive FIFO is not full
+    // 0x00000004 [2]     : RNE (0): Receive FIFO not empty, RO: 0 Receive FIFO is empty
+    // 0x00000002 [1]     : TNF (1): Transmit FIFO not full, RO: 0 Transmit FIFO is full
+    // 0x00000001 [0]     : TFE (1): Transmit FIFO empty, RO: 0 Transmit FIFO is not empty
+    io_ro_32 sr;
+
+    _REG_(SPI_SSPCPSR_OFFSET) // SPI_SSPCPSR
+    // Clock prescale register, SSPCPSR on page 3-8
+    // 0x000000ff [7:0]   : CPSDVSR (0): Clock prescale divisor
     io_rw_32 cpsr;
+
+    _REG_(SPI_SSPIMSC_OFFSET) // SPI_SSPIMSC
+    // Interrupt mask set or clear register, SSPIMSC on page 3-9
+    // 0x00000008 [3]     : TXIM (0): Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked
+    // 0x00000004 [2]     : RXIM (0): Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked
+    // 0x00000002 [1]     : RTIM (0): Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout...
+    // 0x00000001 [0]     : RORIM (0): Receive overrun interrupt mask: 0 Receive FIFO written to while full condition...
     io_rw_32 imsc;
-    io_rw_32 ris;
-    io_rw_32 mis;
+
+    _REG_(SPI_SSPRIS_OFFSET) // SPI_SSPRIS
+    // Raw interrupt status register, SSPRIS on page 3-10
+    // 0x00000008 [3]     : TXRIS (1): Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt
+    // 0x00000004 [2]     : RXRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt
+    // 0x00000002 [1]     : RTRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt
+    // 0x00000001 [0]     : RORRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt
+    io_ro_32 ris;
+
+    _REG_(SPI_SSPMIS_OFFSET) // SPI_SSPMIS
+    // Masked interrupt status register, SSPMIS on page 3-11
+    // 0x00000008 [3]     : TXMIS (0): Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
+    // 0x00000004 [2]     : RXMIS (0): Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
+    // 0x00000002 [1]     : RTMIS (0): Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
+    // 0x00000001 [0]     : RORMIS (0): Gives the receive over run masked interrupt status, after masking, of the...
+    io_ro_32 mis;
+
+    _REG_(SPI_SSPICR_OFFSET) // SPI_SSPICR
+    // Interrupt clear register, SSPICR on page 3-11
+    // 0x00000002 [1]     : RTIC (0): Clears the SSPRTINTR interrupt
+    // 0x00000001 [0]     : RORIC (0): Clears the SSPRORINTR interrupt
     io_rw_32 icr;
+
+    _REG_(SPI_SSPDMACR_OFFSET) // SPI_SSPDMACR
+    // DMA control register, SSPDMACR on page 3-12
+    // 0x00000002 [1]     : TXDMAE (0): Transmit DMA Enable
+    // 0x00000001 [0]     : RXDMAE (0): Receive DMA Enable
     io_rw_32 dmacr;
 } spi_hw_t;
 
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/ssi.h b/src/rp2040/hardware_structs/include/hardware/structs/ssi.h
index 80779fe6b..0ab18beb5 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/ssi.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/ssi.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,40 +10,201 @@
 #define _HARDWARE_STRUCTS_SSI_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/ssi.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_ssi
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/ssi.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(SSI_CTRLR0_OFFSET) // SSI_CTRLR0
+    // Control register 0
+    // 0x01000000 [24]    : SSTE (0): Slave select toggle enable
+    // 0x00600000 [22:21] : SPI_FRF (0): SPI frame format
+    // 0x001f0000 [20:16] : DFS_32 (0): Data frame size in 32b transfer mode
+    // 0x0000f000 [15:12] : CFS (0): Control frame size
+    // 0x00000800 [11]    : SRL (0): Shift register loop (test mode)
+    // 0x00000400 [10]    : SLV_OE (0): Slave output enable
+    // 0x00000300 [9:8]   : TMOD (0): Transfer mode
+    // 0x00000080 [7]     : SCPOL (0): Serial clock polarity
+    // 0x00000040 [6]     : SCPH (0): Serial clock phase
+    // 0x00000030 [5:4]   : FRF (0): Frame format
+    // 0x0000000f [3:0]   : DFS (0): Data frame size
     io_rw_32 ctrlr0;
+
+    _REG_(SSI_CTRLR1_OFFSET) // SSI_CTRLR1
+    // Master Control register 1
+    // 0x0000ffff [15:0]  : NDF (0): Number of data frames
     io_rw_32 ctrlr1;
+
+    _REG_(SSI_SSIENR_OFFSET) // SSI_SSIENR
+    // SSI Enable
+    // 0x00000001 [0]     : SSI_EN (0): SSI enable
     io_rw_32 ssienr;
+
+    _REG_(SSI_MWCR_OFFSET) // SSI_MWCR
+    // Microwire Control
+    // 0x00000004 [2]     : MHS (0): Microwire handshaking
+    // 0x00000002 [1]     : MDD (0): Microwire control
+    // 0x00000001 [0]     : MWMOD (0): Microwire transfer mode
     io_rw_32 mwcr;
+
+    _REG_(SSI_SER_OFFSET) // SSI_SER
+    // Slave enable
+    // 0x00000001 [0]     : SER (0): For each bit:
     io_rw_32 ser;
+
+    _REG_(SSI_BAUDR_OFFSET) // SSI_BAUDR
+    // Baud rate
+    // 0x0000ffff [15:0]  : SCKDV (0): SSI clock divider
     io_rw_32 baudr;
+
+    _REG_(SSI_TXFTLR_OFFSET) // SSI_TXFTLR
+    // TX FIFO threshold level
+    // 0x000000ff [7:0]   : TFT (0): Transmit FIFO threshold
     io_rw_32 txftlr;
+
+    _REG_(SSI_RXFTLR_OFFSET) // SSI_RXFTLR
+    // RX FIFO threshold level
+    // 0x000000ff [7:0]   : RFT (0): Receive FIFO threshold
     io_rw_32 rxftlr;
-    io_rw_32 txflr;
-    io_rw_32 rxflr;
-    io_rw_32 sr;
+
+    _REG_(SSI_TXFLR_OFFSET) // SSI_TXFLR
+    // TX FIFO level
+    // 0x000000ff [7:0]   : TFTFL (0): Transmit FIFO level
+    io_ro_32 txflr;
+
+    _REG_(SSI_RXFLR_OFFSET) // SSI_RXFLR
+    // RX FIFO level
+    // 0x000000ff [7:0]   : RXTFL (0): Receive FIFO level
+    io_ro_32 rxflr;
+
+    _REG_(SSI_SR_OFFSET) // SSI_SR
+    // Status register
+    // 0x00000040 [6]     : DCOL (0): Data collision error
+    // 0x00000020 [5]     : TXE (0): Transmission error
+    // 0x00000010 [4]     : RFF (0): Receive FIFO full
+    // 0x00000008 [3]     : RFNE (0): Receive FIFO not empty
+    // 0x00000004 [2]     : TFE (0): Transmit FIFO empty
+    // 0x00000002 [1]     : TFNF (0): Transmit FIFO not full
+    // 0x00000001 [0]     : BUSY (0): SSI busy flag
+    io_ro_32 sr;
+
+    _REG_(SSI_IMR_OFFSET) // SSI_IMR
+    // Interrupt mask
+    // 0x00000020 [5]     : MSTIM (0): Multi-master contention interrupt mask
+    // 0x00000010 [4]     : RXFIM (0): Receive FIFO full interrupt mask
+    // 0x00000008 [3]     : RXOIM (0): Receive FIFO overflow interrupt mask
+    // 0x00000004 [2]     : RXUIM (0): Receive FIFO underflow interrupt mask
+    // 0x00000002 [1]     : TXOIM (0): Transmit FIFO overflow interrupt mask
+    // 0x00000001 [0]     : TXEIM (0): Transmit FIFO empty interrupt mask
     io_rw_32 imr;
-    io_rw_32 isr;
-    io_rw_32 risr;
-    io_rw_32 txoicr;
-    io_rw_32 rxoicr;
-    io_rw_32 rxuicr;
-    io_rw_32 msticr;
-    io_rw_32 icr;
+
+    _REG_(SSI_ISR_OFFSET) // SSI_ISR
+    // Interrupt status
+    // 0x00000020 [5]     : MSTIS (0): Multi-master contention interrupt status
+    // 0x00000010 [4]     : RXFIS (0): Receive FIFO full interrupt status
+    // 0x00000008 [3]     : RXOIS (0): Receive FIFO overflow interrupt status
+    // 0x00000004 [2]     : RXUIS (0): Receive FIFO underflow interrupt status
+    // 0x00000002 [1]     : TXOIS (0): Transmit FIFO overflow interrupt status
+    // 0x00000001 [0]     : TXEIS (0): Transmit FIFO empty interrupt status
+    io_ro_32 isr;
+
+    _REG_(SSI_RISR_OFFSET) // SSI_RISR
+    // Raw interrupt status
+    // 0x00000020 [5]     : MSTIR (0): Multi-master contention raw interrupt status
+    // 0x00000010 [4]     : RXFIR (0): Receive FIFO full raw interrupt status
+    // 0x00000008 [3]     : RXOIR (0): Receive FIFO overflow raw interrupt status
+    // 0x00000004 [2]     : RXUIR (0): Receive FIFO underflow raw interrupt status
+    // 0x00000002 [1]     : TXOIR (0): Transmit FIFO overflow raw interrupt status
+    // 0x00000001 [0]     : TXEIR (0): Transmit FIFO empty raw interrupt status
+    io_ro_32 risr;
+
+    _REG_(SSI_TXOICR_OFFSET) // SSI_TXOICR
+    // TX FIFO overflow interrupt clear
+    // 0x00000001 [0]     : TXOICR (0): Clear-on-read transmit FIFO overflow interrupt
+    io_ro_32 txoicr;
+
+    _REG_(SSI_RXOICR_OFFSET) // SSI_RXOICR
+    // RX FIFO overflow interrupt clear
+    // 0x00000001 [0]     : RXOICR (0): Clear-on-read receive FIFO overflow interrupt
+    io_ro_32 rxoicr;
+
+    _REG_(SSI_RXUICR_OFFSET) // SSI_RXUICR
+    // RX FIFO underflow interrupt clear
+    // 0x00000001 [0]     : RXUICR (0): Clear-on-read receive FIFO underflow interrupt
+    io_ro_32 rxuicr;
+
+    _REG_(SSI_MSTICR_OFFSET) // SSI_MSTICR
+    // Multi-master interrupt clear
+    // 0x00000001 [0]     : MSTICR (0): Clear-on-read multi-master contention interrupt
+    io_ro_32 msticr;
+
+    _REG_(SSI_ICR_OFFSET) // SSI_ICR
+    // Interrupt clear
+    // 0x00000001 [0]     : ICR (0): Clear-on-read all active interrupts
+    io_ro_32 icr;
+
+    _REG_(SSI_DMACR_OFFSET) // SSI_DMACR
+    // DMA control
+    // 0x00000002 [1]     : TDMAE (0): Transmit DMA enable
+    // 0x00000001 [0]     : RDMAE (0): Receive DMA enable
     io_rw_32 dmacr;
+
+    _REG_(SSI_DMATDLR_OFFSET) // SSI_DMATDLR
+    // DMA TX data level
+    // 0x000000ff [7:0]   : DMATDL (0): Transmit data watermark level
     io_rw_32 dmatdlr;
+
+    _REG_(SSI_DMARDLR_OFFSET) // SSI_DMARDLR
+    // DMA RX data level
+    // 0x000000ff [7:0]   : DMARDL (0): Receive data watermark level (DMARDLR+1)
     io_rw_32 dmardlr;
-    io_rw_32 idr;
-    io_rw_32 ssi_version_id;
+
+    _REG_(SSI_IDR_OFFSET) // SSI_IDR
+    // Identification register
+    // 0xffffffff [31:0]  : IDCODE (0x51535049): Peripheral dentification code
+    io_ro_32 idr;
+
+    _REG_(SSI_SSI_VERSION_ID_OFFSET) // SSI_SSI_VERSION_ID
+    // Version ID
+    // 0xffffffff [31:0]  : SSI_COMP_VERSION (0x3430312a): SNPS component version (format X
+    io_ro_32 ssi_version_id;
+
+    _REG_(SSI_DR0_OFFSET) // SSI_DR0
+    // Data Register 0 (of 36)
+    // 0xffffffff [31:0]  : DR (0): First data register of 36
     io_rw_32 dr0;
-    uint32_t _pad[(0xf0 - 0x60) / 4 - 1];
+
+    uint32_t _pad0[35];
+
+    _REG_(SSI_RX_SAMPLE_DLY_OFFSET) // SSI_RX_SAMPLE_DLY
+    // RX sample delay
+    // 0x000000ff [7:0]   : RSD (0): RXD sample delay (in SCLK cycles)
     io_rw_32 rx_sample_dly;
+
+    _REG_(SSI_SPI_CTRLR0_OFFSET) // SSI_SPI_CTRLR0
+    // SPI control
+    // 0xff000000 [31:24] : XIP_CMD (0x3): SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)
+    // 0x00040000 [18]    : SPI_RXDS_EN (0): Read data strobe enable
+    // 0x00020000 [17]    : INST_DDR_EN (0): Instruction DDR transfer enable
+    // 0x00010000 [16]    : SPI_DDR_EN (0): SPI DDR transfer enable
+    // 0x0000f800 [15:11] : WAIT_CYCLES (0): Wait cycles between control frame transmit and data reception (in SCLK cycles)
+    // 0x00000300 [9:8]   : INST_L (0): Instruction length (0/4/8/16b)
+    // 0x0000003c [5:2]   : ADDR_L (0): Address length (0b-60b in 4b increments)
+    // 0x00000003 [1:0]   : TRANS_TYPE (0): Address and instruction transfer format
     io_rw_32 spi_ctrlr0;
+
+    _REG_(SSI_TXD_DRIVE_EDGE_OFFSET) // SSI_TXD_DRIVE_EDGE
+    // TX drive edge
+    // 0x000000ff [7:0]   : TDE (0): TXD drive edge
     io_rw_32 txd_drive_edge;
 } ssi_hw_t;
 
 #define ssi_hw ((ssi_hw_t *const)XIP_SSI_BASE)
+
 #endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/syscfg.h b/src/rp2040/hardware_structs/include/hardware/structs/syscfg.h
index 0bfc7293c..52218fb1a 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/syscfg.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/syscfg.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,16 +10,65 @@
 #define _HARDWARE_STRUCTS_SYSCFG_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/syscfg.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_syscfg
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/syscfg.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(SYSCFG_PROC0_NMI_MASK_OFFSET) // SYSCFG_PROC0_NMI_MASK
+    // Processor core 0 NMI source mask
     io_rw_32 proc0_nmi_mask;
+
+    _REG_(SYSCFG_PROC1_NMI_MASK_OFFSET) // SYSCFG_PROC1_NMI_MASK
+    // Processor core 1 NMI source mask
     io_rw_32 proc1_nmi_mask;
+
+    _REG_(SYSCFG_PROC_CONFIG_OFFSET) // SYSCFG_PROC_CONFIG
+    // Configuration for processors
+    // 0xf0000000 [31:28] : PROC1_DAP_INSTID (1): Configure proc1 DAP instance ID
+    // 0x0f000000 [27:24] : PROC0_DAP_INSTID (0): Configure proc0 DAP instance ID
+    // 0x00000002 [1]     : PROC1_HALTED (0): Indication that proc1 has halted
+    // 0x00000001 [0]     : PROC0_HALTED (0): Indication that proc0 has halted
     io_rw_32 proc_config;
+
+    _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS
+    // For each bit, if 1, bypass the input synchronizer between that GPIO
+    // 0x3fffffff [29:0]  : PROC_IN_SYNC_BYPASS (0)
     io_rw_32 proc_in_sync_bypass;
+
+    _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS_HI
+    // For each bit, if 1, bypass the input synchronizer between that GPIO
+    // 0x0000003f [5:0]   : PROC_IN_SYNC_BYPASS_HI (0)
     io_rw_32 proc_in_sync_bypass_hi;
+
+    _REG_(SYSCFG_DBGFORCE_OFFSET) // SYSCFG_DBGFORCE
+    // Directly control the SWD debug port of either processor
+    // 0x00000080 [7]     : PROC1_ATTACH (0): Attach processor 1 debug port to syscfg controls, and disconnect it from...
+    // 0x00000040 [6]     : PROC1_SWCLK (1): Directly drive processor 1 SWCLK, if PROC1_ATTACH is set
+    // 0x00000020 [5]     : PROC1_SWDI (1): Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set
+    // 0x00000010 [4]     : PROC1_SWDO (0): Observe the value of processor 1 SWDIO output
+    // 0x00000008 [3]     : PROC0_ATTACH (0): Attach processor 0 debug port to syscfg controls, and disconnect it from...
+    // 0x00000004 [2]     : PROC0_SWCLK (1): Directly drive processor 0 SWCLK, if PROC0_ATTACH is set
+    // 0x00000002 [1]     : PROC0_SWDI (1): Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set
+    // 0x00000001 [0]     : PROC0_SWDO (0): Observe the value of processor 0 SWDIO output
     io_rw_32 dbgforce;
+
+    _REG_(SYSCFG_MEMPOWERDOWN_OFFSET) // SYSCFG_MEMPOWERDOWN
+    // Control power downs to memories
+    // 0x00000080 [7]     : ROM (0)
+    // 0x00000040 [6]     : USB (0)
+    // 0x00000020 [5]     : SRAM5 (0)
+    // 0x00000010 [4]     : SRAM4 (0)
+    // 0x00000008 [3]     : SRAM3 (0)
+    // 0x00000004 [2]     : SRAM2 (0)
+    // 0x00000002 [1]     : SRAM1 (0)
+    // 0x00000001 [0]     : SRAM0 (0)
     io_rw_32 mempowerdown;
 } syscfg_hw_t;
 
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/systick.h b/src/rp2040/hardware_structs/include/hardware/structs/systick.h
index 24673fbc7..a859feae9 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/systick.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/systick.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,10 +12,38 @@
 #include "hardware/address_mapped.h"
 #include "hardware/regs/m0plus.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(M0PLUS_SYST_CSR_OFFSET) // M0PLUS_SYST_CSR
+    // Use the SysTick Control and Status Register to enable the SysTick features
+    // 0x00010000 [16]    : COUNTFLAG (0): Returns 1 if timer counted to 0 since last time this was read
+    // 0x00000004 [2]     : CLKSOURCE (0): SysTick clock source
+    // 0x00000002 [1]     : TICKINT (0): Enables SysTick exception request:
+    // 0x00000001 [0]     : ENABLE (0): Enable SysTick counter:
     io_rw_32 csr;
+
+    _REG_(M0PLUS_SYST_RVR_OFFSET) // M0PLUS_SYST_RVR
+    // Use the SysTick Reload Value Register to specify the start value to load into the current value register when the...
+    // 0x00ffffff [23:0]  : RELOAD (0): Value to load into the SysTick Current Value Register when the counter reaches 0
     io_rw_32 rvr;
+
+    _REG_(M0PLUS_SYST_CVR_OFFSET) // M0PLUS_SYST_CVR
+    // Use the SysTick Current Value Register to find the current value in the register
+    // 0x00ffffff [23:0]  : CURRENT (0): Reads return the current value of the SysTick counter
     io_rw_32 cvr;
+
+    _REG_(M0PLUS_SYST_CALIB_OFFSET) // M0PLUS_SYST_CALIB
+    // Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply
+    // 0x80000000 [31]    : NOREF (0): If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the...
+    // 0x40000000 [30]    : SKEW (0): If reads as 1, the calibration value for 10ms is inexact (due to clock frequency)
+    // 0x00ffffff [23:0]  : TENMS (0): An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock...
     io_ro_32 calib;
 } systick_hw_t;
 
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/timer.h b/src/rp2040/hardware_structs/include/hardware/structs/timer.h
index e051a0697..c7c706692 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/timer.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/timer.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,28 +10,98 @@
 #define _HARDWARE_STRUCTS_TIMER_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/timer.h"
 
-#define NUM_TIMERS 4
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_timer
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/timer.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
 
 typedef struct {
+    _REG_(TIMER_TIMEHW_OFFSET) // TIMER_TIMEHW
+    // Write to bits 63:32 of time
     io_wo_32 timehw;
+
+    _REG_(TIMER_TIMELW_OFFSET) // TIMER_TIMELW
+    // Write to bits 31:0 of time
     io_wo_32 timelw;
+
+    _REG_(TIMER_TIMEHR_OFFSET) // TIMER_TIMEHR
+    // Read from bits 63:32 of time
     io_ro_32 timehr;
+
+    _REG_(TIMER_TIMELR_OFFSET) // TIMER_TIMELR
+    // Read from bits 31:0 of time
     io_ro_32 timelr;
-    io_rw_32 alarm[NUM_TIMERS];
+
+    _REG_(TIMER_ALARM0_OFFSET) // TIMER_ALARM0
+    // (Description copied from array index 0 register TIMER_ALARM0 applies similarly to other array indexes)
+    //
+    // Arm alarm 0, and configure the time it will fire
+    io_rw_32 alarm[NUM_TIMERS]; // 4
+
+    _REG_(TIMER_ARMED_OFFSET) // TIMER_ARMED
+    // Indicates the armed/disarmed status of each alarm
+    // 0x0000000f [3:0]   : ARMED (0)
     io_rw_32 armed;
+
+    _REG_(TIMER_TIMERAWH_OFFSET) // TIMER_TIMERAWH
+    // Raw read from bits 63:32 of time (no side effects)
     io_ro_32 timerawh;
+
+    _REG_(TIMER_TIMERAWL_OFFSET) // TIMER_TIMERAWL
+    // Raw read from bits 31:0 of time (no side effects)
     io_ro_32 timerawl;
+
+    _REG_(TIMER_DBGPAUSE_OFFSET) // TIMER_DBGPAUSE
+    // Set bits high to enable pause when the corresponding debug ports are active
+    // 0x00000004 [2]     : DBG1 (1): Pause when processor 1 is in debug mode
+    // 0x00000002 [1]     : DBG0 (1): Pause when processor 0 is in debug mode
     io_rw_32 dbgpause;
+
+    _REG_(TIMER_PAUSE_OFFSET) // TIMER_PAUSE
+    // Set high to pause the timer
+    // 0x00000001 [0]     : PAUSE (0)
     io_rw_32 pause;
+
+    _REG_(TIMER_INTR_OFFSET) // TIMER_INTR
+    // Raw Interrupts
+    // 0x00000008 [3]     : ALARM_3 (0)
+    // 0x00000004 [2]     : ALARM_2 (0)
+    // 0x00000002 [1]     : ALARM_1 (0)
+    // 0x00000001 [0]     : ALARM_0 (0)
     io_rw_32 intr;
+
+    _REG_(TIMER_INTE_OFFSET) // TIMER_INTE
+    // Interrupt Enable
+    // 0x00000008 [3]     : ALARM_3 (0)
+    // 0x00000004 [2]     : ALARM_2 (0)
+    // 0x00000002 [1]     : ALARM_1 (0)
+    // 0x00000001 [0]     : ALARM_0 (0)
     io_rw_32 inte;
+
+    _REG_(TIMER_INTF_OFFSET) // TIMER_INTF
+    // Interrupt Force
+    // 0x00000008 [3]     : ALARM_3 (0)
+    // 0x00000004 [2]     : ALARM_2 (0)
+    // 0x00000002 [1]     : ALARM_1 (0)
+    // 0x00000001 [0]     : ALARM_0 (0)
     io_rw_32 intf;
+
+    _REG_(TIMER_INTS_OFFSET) // TIMER_INTS
+    // Interrupt status after masking & forcing
+    // 0x00000008 [3]     : ALARM_3 (0)
+    // 0x00000004 [2]     : ALARM_2 (0)
+    // 0x00000002 [1]     : ALARM_1 (0)
+    // 0x00000001 [0]     : ALARM_0 (0)
     io_ro_32 ints;
 } timer_hw_t;
 
 #define timer_hw ((timer_hw_t *const)TIMER_BASE)
 
+static_assert( NUM_TIMERS == 4, "");
+
 #endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/uart.h b/src/rp2040/hardware_structs/include/hardware/structs/uart.h
index 42fe8e88b..09af33e43 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/uart.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/uart.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,22 +12,162 @@
 #include "hardware/address_mapped.h"
 #include "hardware/regs/uart.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_uart
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/uart.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(UART_UARTDR_OFFSET) // UART_UARTDR
+    // Data Register, UARTDR
+    // 0x00000800 [11]    : OE (0): Overrun error
+    // 0x00000400 [10]    : BE (0): Break error
+    // 0x00000200 [9]     : PE (0): Parity error
+    // 0x00000100 [8]     : FE (0): Framing error
+    // 0x000000ff [7:0]   : DATA (0): Receive (read) data character
     io_rw_32 dr;
+
+    _REG_(UART_UARTRSR_OFFSET) // UART_UARTRSR
+    // Receive Status Register/Error Clear Register, UARTRSR/UARTECR
+    // 0x00000008 [3]     : OE (0): Overrun error
+    // 0x00000004 [2]     : BE (0): Break error
+    // 0x00000002 [1]     : PE (0): Parity error
+    // 0x00000001 [0]     : FE (0): Framing error
     io_rw_32 rsr;
+
     uint32_t _pad0[4];
-    io_rw_32 fr;
+
+    _REG_(UART_UARTFR_OFFSET) // UART_UARTFR
+    // Flag Register, UARTFR
+    // 0x00000100 [8]     : RI (0): Ring indicator
+    // 0x00000080 [7]     : TXFE (1): Transmit FIFO empty
+    // 0x00000040 [6]     : RXFF (0): Receive FIFO full
+    // 0x00000020 [5]     : TXFF (0): Transmit FIFO full
+    // 0x00000010 [4]     : RXFE (1): Receive FIFO empty
+    // 0x00000008 [3]     : BUSY (0): UART busy
+    // 0x00000004 [2]     : DCD (0): Data carrier detect
+    // 0x00000002 [1]     : DSR (0): Data set ready
+    // 0x00000001 [0]     : CTS (0): Clear to send
+    io_ro_32 fr;
+
     uint32_t _pad1;
+
+    _REG_(UART_UARTILPR_OFFSET) // UART_UARTILPR
+    // IrDA Low-Power Counter Register, UARTILPR
+    // 0x000000ff [7:0]   : ILPDVSR (0): 8-bit low-power divisor value
     io_rw_32 ilpr;
+
+    _REG_(UART_UARTIBRD_OFFSET) // UART_UARTIBRD
+    // Integer Baud Rate Register, UARTIBRD
+    // 0x0000ffff [15:0]  : BAUD_DIVINT (0): The integer baud rate divisor
     io_rw_32 ibrd;
+
+    _REG_(UART_UARTFBRD_OFFSET) // UART_UARTFBRD
+    // Fractional Baud Rate Register, UARTFBRD
+    // 0x0000003f [5:0]   : BAUD_DIVFRAC (0): The fractional baud rate divisor
     io_rw_32 fbrd;
+
+    _REG_(UART_UARTLCR_H_OFFSET) // UART_UARTLCR_H
+    // Line Control Register, UARTLCR_H
+    // 0x00000080 [7]     : SPS (0): Stick parity select
+    // 0x00000060 [6:5]   : WLEN (0): Word length
+    // 0x00000010 [4]     : FEN (0): Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become...
+    // 0x00000008 [3]     : STP2 (0): Two stop bits select
+    // 0x00000004 [2]     : EPS (0): Even parity select
+    // 0x00000002 [1]     : PEN (0): Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 =...
+    // 0x00000001 [0]     : BRK (0): Send break
     io_rw_32 lcr_h;
+
+    _REG_(UART_UARTCR_OFFSET) // UART_UARTCR
+    // Control Register, UARTCR
+    // 0x00008000 [15]    : CTSEN (0): CTS hardware flow control enable
+    // 0x00004000 [14]    : RTSEN (0): RTS hardware flow control enable
+    // 0x00002000 [13]    : OUT2 (0): This bit is the complement of the UART Out2 (nUARTOut2) modem status output
+    // 0x00001000 [12]    : OUT1 (0): This bit is the complement of the UART Out1 (nUARTOut1) modem status output
+    // 0x00000800 [11]    : RTS (0): Request to send
+    // 0x00000400 [10]    : DTR (0): Data transmit ready
+    // 0x00000200 [9]     : RXE (1): Receive enable
+    // 0x00000100 [8]     : TXE (1): Transmit enable
+    // 0x00000080 [7]     : LBE (0): Loopback enable
+    // 0x00000004 [2]     : SIRLP (0): SIR low-power IrDA mode
+    // 0x00000002 [1]     : SIREN (0): SIR enable: 0 = IrDA SIR ENDEC is disabled
+    // 0x00000001 [0]     : UARTEN (0): UART enable: 0 = UART is disabled
     io_rw_32 cr;
+
+    _REG_(UART_UARTIFLS_OFFSET) // UART_UARTIFLS
+    // Interrupt FIFO Level Select Register, UARTIFLS
+    // 0x00000038 [5:3]   : RXIFLSEL (0x2): Receive interrupt FIFO level select
+    // 0x00000007 [2:0]   : TXIFLSEL (0x2): Transmit interrupt FIFO level select
     io_rw_32 ifls;
+
+    _REG_(UART_UARTIMSC_OFFSET) // UART_UARTIMSC
+    // Interrupt Mask Set/Clear Register, UARTIMSC
+    // 0x00000400 [10]    : OEIM (0): Overrun error interrupt mask
+    // 0x00000200 [9]     : BEIM (0): Break error interrupt mask
+    // 0x00000100 [8]     : PEIM (0): Parity error interrupt mask
+    // 0x00000080 [7]     : FEIM (0): Framing error interrupt mask
+    // 0x00000040 [6]     : RTIM (0): Receive timeout interrupt mask
+    // 0x00000020 [5]     : TXIM (0): Transmit interrupt mask
+    // 0x00000010 [4]     : RXIM (0): Receive interrupt mask
+    // 0x00000008 [3]     : DSRMIM (0): nUARTDSR modem interrupt mask
+    // 0x00000004 [2]     : DCDMIM (0): nUARTDCD modem interrupt mask
+    // 0x00000002 [1]     : CTSMIM (0): nUARTCTS modem interrupt mask
+    // 0x00000001 [0]     : RIMIM (0): nUARTRI modem interrupt mask
     io_rw_32 imsc;
-    io_rw_32 ris;
-    io_rw_32 mis;
+
+    _REG_(UART_UARTRIS_OFFSET) // UART_UARTRIS
+    // Raw Interrupt Status Register, UARTRIS
+    // 0x00000400 [10]    : OERIS (0): Overrun error interrupt status
+    // 0x00000200 [9]     : BERIS (0): Break error interrupt status
+    // 0x00000100 [8]     : PERIS (0): Parity error interrupt status
+    // 0x00000080 [7]     : FERIS (0): Framing error interrupt status
+    // 0x00000040 [6]     : RTRIS (0): Receive timeout interrupt status
+    // 0x00000020 [5]     : TXRIS (0): Transmit interrupt status
+    // 0x00000010 [4]     : RXRIS (0): Receive interrupt status
+    // 0x00000008 [3]     : DSRRMIS (0): nUARTDSR modem interrupt status
+    // 0x00000004 [2]     : DCDRMIS (0): nUARTDCD modem interrupt status
+    // 0x00000002 [1]     : CTSRMIS (0): nUARTCTS modem interrupt status
+    // 0x00000001 [0]     : RIRMIS (0): nUARTRI modem interrupt status
+    io_ro_32 ris;
+
+    _REG_(UART_UARTMIS_OFFSET) // UART_UARTMIS
+    // Masked Interrupt Status Register, UARTMIS
+    // 0x00000400 [10]    : OEMIS (0): Overrun error masked interrupt status
+    // 0x00000200 [9]     : BEMIS (0): Break error masked interrupt status
+    // 0x00000100 [8]     : PEMIS (0): Parity error masked interrupt status
+    // 0x00000080 [7]     : FEMIS (0): Framing error masked interrupt status
+    // 0x00000040 [6]     : RTMIS (0): Receive timeout masked interrupt status
+    // 0x00000020 [5]     : TXMIS (0): Transmit masked interrupt status
+    // 0x00000010 [4]     : RXMIS (0): Receive masked interrupt status
+    // 0x00000008 [3]     : DSRMMIS (0): nUARTDSR modem masked interrupt status
+    // 0x00000004 [2]     : DCDMMIS (0): nUARTDCD modem masked interrupt status
+    // 0x00000002 [1]     : CTSMMIS (0): nUARTCTS modem masked interrupt status
+    // 0x00000001 [0]     : RIMMIS (0): nUARTRI modem masked interrupt status
+    io_ro_32 mis;
+
+    _REG_(UART_UARTICR_OFFSET) // UART_UARTICR
+    // Interrupt Clear Register, UARTICR
+    // 0x00000400 [10]    : OEIC (0): Overrun error interrupt clear
+    // 0x00000200 [9]     : BEIC (0): Break error interrupt clear
+    // 0x00000100 [8]     : PEIC (0): Parity error interrupt clear
+    // 0x00000080 [7]     : FEIC (0): Framing error interrupt clear
+    // 0x00000040 [6]     : RTIC (0): Receive timeout interrupt clear
+    // 0x00000020 [5]     : TXIC (0): Transmit interrupt clear
+    // 0x00000010 [4]     : RXIC (0): Receive interrupt clear
+    // 0x00000008 [3]     : DSRMIC (0): nUARTDSR modem interrupt clear
+    // 0x00000004 [2]     : DCDMIC (0): nUARTDCD modem interrupt clear
+    // 0x00000002 [1]     : CTSMIC (0): nUARTCTS modem interrupt clear
+    // 0x00000001 [0]     : RIMIC (0): nUARTRI modem interrupt clear
     io_rw_32 icr;
+
+    _REG_(UART_UARTDMACR_OFFSET) // UART_UARTDMACR
+    // DMA Control Register, UARTDMACR
+    // 0x00000004 [2]     : DMAONERR (0): DMA on error
+    // 0x00000002 [1]     : TXDMAE (0): Transmit DMA enable
+    // 0x00000001 [0]     : RXDMAE (0): Receive DMA enable
     io_rw_32 dmacr;
 } uart_hw_t;
 
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/usb.h b/src/rp2040/hardware_structs/include/hardware/structs/usb.h
index 0254e61df..c9455d065 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/usb.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/usb.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,6 +12,14 @@
 #include "hardware/address_mapped.h"
 #include "hardware/regs/usb.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_usb
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/usb.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 // 0-15
 #define USB_NUM_ENDPOINTS 16
 
@@ -39,10 +49,10 @@
 #define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28)
 #define EP_CTRL_INTERRUPT_ON_NAK (1u << 16)
 #define EP_CTRL_INTERRUPT_ON_STALL (1u << 17)
-#define EP_CTRL_BUFFER_TYPE_LSB 26
-#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16
+#define EP_CTRL_BUFFER_TYPE_LSB 26u
+#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16u
 
-#define USB_DPRAM_SIZE 4096
+#define USB_DPRAM_SIZE 4096u
 
 // PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb
 // Allow user to claim some of the USB RAM for themselves
@@ -112,38 +122,457 @@ static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, "");
 static_assert(offsetof(usb_host_dpram_t, epx_data) == 0x180, "");
 
 typedef struct {
+    _REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP
+    // Device address and endpoint control
+    // 0x000f0000 [19:16] : ENDPOINT (0): Device endpoint to send data to
+    // 0x0000007f [6:0]   : ADDRESS (0): In device mode, the address that the device should respond to
     io_rw_32 dev_addr_ctrl;
-    io_rw_32 int_ep_addr_ctrl[USB_HOST_INTERRUPT_ENDPOINTS];
+
+    _REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP1
+    // (Description copied from array index 0 register USB_ADDR_ENDP1 applies similarly to other array indexes)
+    //
+    // Interrupt endpoint 1
+    // 0x04000000 [26]    : INTEP_PREAMBLE (0): Interrupt EP requires preamble (is a low speed device on a full speed hub)
+    // 0x02000000 [25]    : INTEP_DIR (0): Direction of the interrupt endpoint
+    // 0x000f0000 [19:16] : ENDPOINT (0): Endpoint number of the interrupt endpoint
+    // 0x0000007f [6:0]   : ADDRESS (0): Device address
+    io_rw_32 int_ep_addr_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; // 15
+
+    _REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL
+    // Main control register
+    // 0x80000000 [31]    : SIM_TIMING (0): Reduced timings for simulation
+    // 0x00000002 [1]     : HOST_NDEVICE (0): Device mode = 0, Host mode = 1
+    // 0x00000001 [0]     : CONTROLLER_EN (0): Enable controller
     io_rw_32 main_ctrl;
-    io_rw_32 sof_rw;
+
+    _REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR
+    // Set the SOF (Start of Frame) frame number in the host controller
+    // 0x000007ff [10:0]  : COUNT (0)
+    io_wo_32 sof_rw;
+
+    _REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD
+    // Read the last SOF (Start of Frame) frame number seen
+    // 0x000007ff [10:0]  : COUNT (0)
     io_ro_32 sof_rd;
+
+    _REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL
+    // SIE control register
+    // 0x80000000 [31]    : EP0_INT_STALL (0): Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL
+    // 0x40000000 [30]    : EP0_DOUBLE_BUF (0): Device: EP0 single buffered = 0, double buffered = 1
+    // 0x20000000 [29]    : EP0_INT_1BUF (0): Device: Set bit in BUFF_STATUS for every buffer completed on EP0
+    // 0x10000000 [28]    : EP0_INT_2BUF (0): Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0
+    // 0x08000000 [27]    : EP0_INT_NAK (0): Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK
+    // 0x04000000 [26]    : DIRECT_EN (0): Direct bus drive enable
+    // 0x02000000 [25]    : DIRECT_DP (0): Direct control of DP
+    // 0x01000000 [24]    : DIRECT_DM (0): Direct control of DM
+    // 0x00040000 [18]    : TRANSCEIVER_PD (0): Power down bus transceiver
+    // 0x00020000 [17]    : RPU_OPT (0): Device: Pull-up strength (0=1K2, 1=2k3)
+    // 0x00010000 [16]    : PULLUP_EN (0): Device: Enable pull up resistor
+    // 0x00008000 [15]    : PULLDOWN_EN (0): Host: Enable pull down resistors
+    // 0x00002000 [13]    : RESET_BUS (0): Host: Reset bus
+    // 0x00001000 [12]    : RESUME (0): Device: Remote wakeup
+    // 0x00000800 [11]    : VBUS_EN (0): Host: Enable VBUS
+    // 0x00000400 [10]    : KEEP_ALIVE_EN (0): Host: Enable keep alive packet (for low speed bus)
+    // 0x00000200 [9]     : SOF_EN (0): Host: Enable SOF generation (for full speed bus)
+    // 0x00000100 [8]     : SOF_SYNC (0): Host: Delay packet(s) until after SOF
+    // 0x00000040 [6]     : PREAMBLE_EN (0): Host: Preable enable for LS device on FS hub
+    // 0x00000010 [4]     : STOP_TRANS (0): Host: Stop transaction
+    // 0x00000008 [3]     : RECEIVE_DATA (0): Host: Receive transaction (IN to host)
+    // 0x00000004 [2]     : SEND_DATA (0): Host: Send transaction (OUT from host)
+    // 0x00000002 [1]     : SEND_SETUP (0): Host: Send Setup packet
+    // 0x00000001 [0]     : START_TRANS (0): Host: Start transaction
     io_rw_32 sie_ctrl;
+
+    _REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS
+    // SIE status register
+    // 0x80000000 [31]    : DATA_SEQ_ERROR (0): Data Sequence Error
+    // 0x40000000 [30]    : ACK_REC (0): ACK received
+    // 0x20000000 [29]    : STALL_REC (0): Host: STALL received
+    // 0x10000000 [28]    : NAK_REC (0): Host: NAK received
+    // 0x08000000 [27]    : RX_TIMEOUT (0): RX timeout is raised by both the host and device if an ACK is not received in...
+    // 0x04000000 [26]    : RX_OVERFLOW (0): RX overflow is raised by the Serial RX engine if the incoming data is too fast
+    // 0x02000000 [25]    : BIT_STUFF_ERROR (0): Bit Stuff Error
+    // 0x01000000 [24]    : CRC_ERROR (0): CRC Error
+    // 0x00080000 [19]    : BUS_RESET (0): Device: bus reset received
+    // 0x00040000 [18]    : TRANS_COMPLETE (0): Transaction complete
+    // 0x00020000 [17]    : SETUP_REC (0): Device: Setup packet received
+    // 0x00010000 [16]    : CONNECTED (0): Device: connected
+    // 0x00000800 [11]    : RESUME (0): Host: Device has initiated a remote resume
+    // 0x00000400 [10]    : VBUS_OVER_CURR (0): VBUS over current detected
+    // 0x00000300 [9:8]   : SPEED (0): Host: device speed
+    // 0x00000010 [4]     : SUSPENDED (0): Bus in suspended state
+    // 0x0000000c [3:2]   : LINE_STATE (0): USB bus line state
+    // 0x00000001 [0]     : VBUS_DETECTED (0): Device: VBUS Detected
     io_rw_32 sie_status;
+
+    _REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL
+    // interrupt endpoint control register
+    // 0x0000fffe [15:1]  : INT_EP_ACTIVE (0): Host: Enable interrupt endpoint 1 -> 15
     io_rw_32 int_ep_ctrl;
+
+    _REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS
+    // Buffer status register
+    // 0x80000000 [31]    : EP15_OUT (0)
+    // 0x40000000 [30]    : EP15_IN (0)
+    // 0x20000000 [29]    : EP14_OUT (0)
+    // 0x10000000 [28]    : EP14_IN (0)
+    // 0x08000000 [27]    : EP13_OUT (0)
+    // 0x04000000 [26]    : EP13_IN (0)
+    // 0x02000000 [25]    : EP12_OUT (0)
+    // 0x01000000 [24]    : EP12_IN (0)
+    // 0x00800000 [23]    : EP11_OUT (0)
+    // 0x00400000 [22]    : EP11_IN (0)
+    // 0x00200000 [21]    : EP10_OUT (0)
+    // 0x00100000 [20]    : EP10_IN (0)
+    // 0x00080000 [19]    : EP9_OUT (0)
+    // 0x00040000 [18]    : EP9_IN (0)
+    // 0x00020000 [17]    : EP8_OUT (0)
+    // 0x00010000 [16]    : EP8_IN (0)
+    // 0x00008000 [15]    : EP7_OUT (0)
+    // 0x00004000 [14]    : EP7_IN (0)
+    // 0x00002000 [13]    : EP6_OUT (0)
+    // 0x00001000 [12]    : EP6_IN (0)
+    // 0x00000800 [11]    : EP5_OUT (0)
+    // 0x00000400 [10]    : EP5_IN (0)
+    // 0x00000200 [9]     : EP4_OUT (0)
+    // 0x00000100 [8]     : EP4_IN (0)
+    // 0x00000080 [7]     : EP3_OUT (0)
+    // 0x00000040 [6]     : EP3_IN (0)
+    // 0x00000020 [5]     : EP2_OUT (0)
+    // 0x00000010 [4]     : EP2_IN (0)
+    // 0x00000008 [3]     : EP1_OUT (0)
+    // 0x00000004 [2]     : EP1_IN (0)
+    // 0x00000002 [1]     : EP0_OUT (0)
+    // 0x00000001 [0]     : EP0_IN (0)
     io_rw_32 buf_status;
-    io_rw_32 buf_cpu_should_handle; // for double buff
+
+    _REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE
+    // Which of the double buffers should be handled
+    // 0x80000000 [31]    : EP15_OUT (0)
+    // 0x40000000 [30]    : EP15_IN (0)
+    // 0x20000000 [29]    : EP14_OUT (0)
+    // 0x10000000 [28]    : EP14_IN (0)
+    // 0x08000000 [27]    : EP13_OUT (0)
+    // 0x04000000 [26]    : EP13_IN (0)
+    // 0x02000000 [25]    : EP12_OUT (0)
+    // 0x01000000 [24]    : EP12_IN (0)
+    // 0x00800000 [23]    : EP11_OUT (0)
+    // 0x00400000 [22]    : EP11_IN (0)
+    // 0x00200000 [21]    : EP10_OUT (0)
+    // 0x00100000 [20]    : EP10_IN (0)
+    // 0x00080000 [19]    : EP9_OUT (0)
+    // 0x00040000 [18]    : EP9_IN (0)
+    // 0x00020000 [17]    : EP8_OUT (0)
+    // 0x00010000 [16]    : EP8_IN (0)
+    // 0x00008000 [15]    : EP7_OUT (0)
+    // 0x00004000 [14]    : EP7_IN (0)
+    // 0x00002000 [13]    : EP6_OUT (0)
+    // 0x00001000 [12]    : EP6_IN (0)
+    // 0x00000800 [11]    : EP5_OUT (0)
+    // 0x00000400 [10]    : EP5_IN (0)
+    // 0x00000200 [9]     : EP4_OUT (0)
+    // 0x00000100 [8]     : EP4_IN (0)
+    // 0x00000080 [7]     : EP3_OUT (0)
+    // 0x00000040 [6]     : EP3_IN (0)
+    // 0x00000020 [5]     : EP2_OUT (0)
+    // 0x00000010 [4]     : EP2_IN (0)
+    // 0x00000008 [3]     : EP1_OUT (0)
+    // 0x00000004 [2]     : EP1_IN (0)
+    // 0x00000002 [1]     : EP0_OUT (0)
+    // 0x00000001 [0]     : EP0_IN (0)
+    io_ro_32 buf_cpu_should_handle;
+
+    _REG_(USB_EP_ABORT_OFFSET) // USB_EP_ABORT
+    // Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer
+    // 0x80000000 [31]    : EP15_OUT (0)
+    // 0x40000000 [30]    : EP15_IN (0)
+    // 0x20000000 [29]    : EP14_OUT (0)
+    // 0x10000000 [28]    : EP14_IN (0)
+    // 0x08000000 [27]    : EP13_OUT (0)
+    // 0x04000000 [26]    : EP13_IN (0)
+    // 0x02000000 [25]    : EP12_OUT (0)
+    // 0x01000000 [24]    : EP12_IN (0)
+    // 0x00800000 [23]    : EP11_OUT (0)
+    // 0x00400000 [22]    : EP11_IN (0)
+    // 0x00200000 [21]    : EP10_OUT (0)
+    // 0x00100000 [20]    : EP10_IN (0)
+    // 0x00080000 [19]    : EP9_OUT (0)
+    // 0x00040000 [18]    : EP9_IN (0)
+    // 0x00020000 [17]    : EP8_OUT (0)
+    // 0x00010000 [16]    : EP8_IN (0)
+    // 0x00008000 [15]    : EP7_OUT (0)
+    // 0x00004000 [14]    : EP7_IN (0)
+    // 0x00002000 [13]    : EP6_OUT (0)
+    // 0x00001000 [12]    : EP6_IN (0)
+    // 0x00000800 [11]    : EP5_OUT (0)
+    // 0x00000400 [10]    : EP5_IN (0)
+    // 0x00000200 [9]     : EP4_OUT (0)
+    // 0x00000100 [8]     : EP4_IN (0)
+    // 0x00000080 [7]     : EP3_OUT (0)
+    // 0x00000040 [6]     : EP3_IN (0)
+    // 0x00000020 [5]     : EP2_OUT (0)
+    // 0x00000010 [4]     : EP2_IN (0)
+    // 0x00000008 [3]     : EP1_OUT (0)
+    // 0x00000004 [2]     : EP1_IN (0)
+    // 0x00000002 [1]     : EP0_OUT (0)
+    // 0x00000001 [0]     : EP0_IN (0)
     io_rw_32 abort;
+
+    _REG_(USB_EP_ABORT_DONE_OFFSET) // USB_EP_ABORT_DONE
+    // Device only: Used in conjunction with `EP_ABORT`
+    // 0x80000000 [31]    : EP15_OUT (0)
+    // 0x40000000 [30]    : EP15_IN (0)
+    // 0x20000000 [29]    : EP14_OUT (0)
+    // 0x10000000 [28]    : EP14_IN (0)
+    // 0x08000000 [27]    : EP13_OUT (0)
+    // 0x04000000 [26]    : EP13_IN (0)
+    // 0x02000000 [25]    : EP12_OUT (0)
+    // 0x01000000 [24]    : EP12_IN (0)
+    // 0x00800000 [23]    : EP11_OUT (0)
+    // 0x00400000 [22]    : EP11_IN (0)
+    // 0x00200000 [21]    : EP10_OUT (0)
+    // 0x00100000 [20]    : EP10_IN (0)
+    // 0x00080000 [19]    : EP9_OUT (0)
+    // 0x00040000 [18]    : EP9_IN (0)
+    // 0x00020000 [17]    : EP8_OUT (0)
+    // 0x00010000 [16]    : EP8_IN (0)
+    // 0x00008000 [15]    : EP7_OUT (0)
+    // 0x00004000 [14]    : EP7_IN (0)
+    // 0x00002000 [13]    : EP6_OUT (0)
+    // 0x00001000 [12]    : EP6_IN (0)
+    // 0x00000800 [11]    : EP5_OUT (0)
+    // 0x00000400 [10]    : EP5_IN (0)
+    // 0x00000200 [9]     : EP4_OUT (0)
+    // 0x00000100 [8]     : EP4_IN (0)
+    // 0x00000080 [7]     : EP3_OUT (0)
+    // 0x00000040 [6]     : EP3_IN (0)
+    // 0x00000020 [5]     : EP2_OUT (0)
+    // 0x00000010 [4]     : EP2_IN (0)
+    // 0x00000008 [3]     : EP1_OUT (0)
+    // 0x00000004 [2]     : EP1_IN (0)
+    // 0x00000002 [1]     : EP0_OUT (0)
+    // 0x00000001 [0]     : EP0_IN (0)
     io_rw_32 abort_done;
+
+    _REG_(USB_EP_STALL_ARM_OFFSET) // USB_EP_STALL_ARM
+    // Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0
+    // 0x00000002 [1]     : EP0_OUT (0)
+    // 0x00000001 [0]     : EP0_IN (0)
     io_rw_32 ep_stall_arm;
+
+    _REG_(USB_NAK_POLL_OFFSET) // USB_NAK_POLL
+    // Used by the host controller
+    // 0x03ff0000 [25:16] : DELAY_FS (0x10): NAK polling interval for a full speed device
+    // 0x000003ff [9:0]   : DELAY_LS (0x10): NAK polling interval for a low speed device
     io_rw_32 nak_poll;
+
+    _REG_(USB_EP_STATUS_STALL_NAK_OFFSET) // USB_EP_STATUS_STALL_NAK
+    // Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set
+    // 0x80000000 [31]    : EP15_OUT (0)
+    // 0x40000000 [30]    : EP15_IN (0)
+    // 0x20000000 [29]    : EP14_OUT (0)
+    // 0x10000000 [28]    : EP14_IN (0)
+    // 0x08000000 [27]    : EP13_OUT (0)
+    // 0x04000000 [26]    : EP13_IN (0)
+    // 0x02000000 [25]    : EP12_OUT (0)
+    // 0x01000000 [24]    : EP12_IN (0)
+    // 0x00800000 [23]    : EP11_OUT (0)
+    // 0x00400000 [22]    : EP11_IN (0)
+    // 0x00200000 [21]    : EP10_OUT (0)
+    // 0x00100000 [20]    : EP10_IN (0)
+    // 0x00080000 [19]    : EP9_OUT (0)
+    // 0x00040000 [18]    : EP9_IN (0)
+    // 0x00020000 [17]    : EP8_OUT (0)
+    // 0x00010000 [16]    : EP8_IN (0)
+    // 0x00008000 [15]    : EP7_OUT (0)
+    // 0x00004000 [14]    : EP7_IN (0)
+    // 0x00002000 [13]    : EP6_OUT (0)
+    // 0x00001000 [12]    : EP6_IN (0)
+    // 0x00000800 [11]    : EP5_OUT (0)
+    // 0x00000400 [10]    : EP5_IN (0)
+    // 0x00000200 [9]     : EP4_OUT (0)
+    // 0x00000100 [8]     : EP4_IN (0)
+    // 0x00000080 [7]     : EP3_OUT (0)
+    // 0x00000040 [6]     : EP3_IN (0)
+    // 0x00000020 [5]     : EP2_OUT (0)
+    // 0x00000010 [4]     : EP2_IN (0)
+    // 0x00000008 [3]     : EP1_OUT (0)
+    // 0x00000004 [2]     : EP1_IN (0)
+    // 0x00000002 [1]     : EP0_OUT (0)
+    // 0x00000001 [0]     : EP0_IN (0)
     io_rw_32 ep_nak_stall_status;
+
+    _REG_(USB_USB_MUXING_OFFSET) // USB_USB_MUXING
+    // Where to connect the USB controller
+    // 0x00000008 [3]     : SOFTCON (0)
+    // 0x00000004 [2]     : TO_DIGITAL_PAD (0)
+    // 0x00000002 [1]     : TO_EXTPHY (0)
+    // 0x00000001 [0]     : TO_PHY (0)
     io_rw_32 muxing;
+
+    _REG_(USB_USB_PWR_OFFSET) // USB_USB_PWR
+    // Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO
+    // 0x00000020 [5]     : OVERCURR_DETECT_EN (0)
+    // 0x00000010 [4]     : OVERCURR_DETECT (0)
+    // 0x00000008 [3]     : VBUS_DETECT_OVERRIDE_EN (0)
+    // 0x00000004 [2]     : VBUS_DETECT (0)
+    // 0x00000002 [1]     : VBUS_EN_OVERRIDE_EN (0)
+    // 0x00000001 [0]     : VBUS_EN (0)
     io_rw_32 pwr;
+
+    _REG_(USB_USBPHY_DIRECT_OFFSET) // USB_USBPHY_DIRECT
+    // This register allows for direct control of the USB phy
+    // 0x00400000 [22]    : DM_OVV (0): DM over voltage
+    // 0x00200000 [21]    : DP_OVV (0): DP over voltage
+    // 0x00100000 [20]    : DM_OVCN (0): DM overcurrent
+    // 0x00080000 [19]    : DP_OVCN (0): DP overcurrent
+    // 0x00040000 [18]    : RX_DM (0): DPM pin state
+    // 0x00020000 [17]    : RX_DP (0): DPP pin state
+    // 0x00010000 [16]    : RX_DD (0): Differential RX
+    // 0x00008000 [15]    : TX_DIFFMODE (0): TX_DIFFMODE=0: Single ended mode
+    // 0x00004000 [14]    : TX_FSSLEW (0): TX_FSSLEW=0: Low speed slew rate
+    // 0x00002000 [13]    : TX_PD (0): TX power down override (if override enable is set)
+    // 0x00001000 [12]    : RX_PD (0): RX power down override (if override enable is set)
+    // 0x00000800 [11]    : TX_DM (0): Output data
+    // 0x00000400 [10]    : TX_DP (0): Output data
+    // 0x00000200 [9]     : TX_DM_OE (0): Output enable
+    // 0x00000100 [8]     : TX_DP_OE (0): Output enable
+    // 0x00000040 [6]     : DM_PULLDN_EN (0): DM pull down enable
+    // 0x00000020 [5]     : DM_PULLUP_EN (0): DM pull up enable
+    // 0x00000010 [4]     : DM_PULLUP_HISEL (0): Enable the second DM pull up resistor
+    // 0x00000004 [2]     : DP_PULLDN_EN (0): DP pull down enable
+    // 0x00000002 [1]     : DP_PULLUP_EN (0): DP pull up enable
+    // 0x00000001 [0]     : DP_PULLUP_HISEL (0): Enable the second DP pull up resistor
     io_rw_32 phy_direct;
+
+    _REG_(USB_USBPHY_DIRECT_OVERRIDE_OFFSET) // USB_USBPHY_DIRECT_OVERRIDE
+    // Override enable for each control in usbphy_direct
+    // 0x00008000 [15]    : TX_DIFFMODE_OVERRIDE_EN (0)
+    // 0x00001000 [12]    : DM_PULLUP_OVERRIDE_EN (0)
+    // 0x00000800 [11]    : TX_FSSLEW_OVERRIDE_EN (0)
+    // 0x00000400 [10]    : TX_PD_OVERRIDE_EN (0)
+    // 0x00000200 [9]     : RX_PD_OVERRIDE_EN (0)
+    // 0x00000100 [8]     : TX_DM_OVERRIDE_EN (0)
+    // 0x00000080 [7]     : TX_DP_OVERRIDE_EN (0)
+    // 0x00000040 [6]     : TX_DM_OE_OVERRIDE_EN (0)
+    // 0x00000020 [5]     : TX_DP_OE_OVERRIDE_EN (0)
+    // 0x00000010 [4]     : DM_PULLDN_EN_OVERRIDE_EN (0)
+    // 0x00000008 [3]     : DP_PULLDN_EN_OVERRIDE_EN (0)
+    // 0x00000004 [2]     : DP_PULLUP_EN_OVERRIDE_EN (0)
+    // 0x00000002 [1]     : DM_PULLUP_HISEL_OVERRIDE_EN (0)
+    // 0x00000001 [0]     : DP_PULLUP_HISEL_OVERRIDE_EN (0)
     io_rw_32 phy_direct_override;
+
+    _REG_(USB_USBPHY_TRIM_OFFSET) // USB_USBPHY_TRIM
+    // Used to adjust trim values of USB phy pull down resistors
+    // 0x00001f00 [12:8]  : DM_PULLDN_TRIM (0x1f): Value to drive to USB PHY
+    // 0x0000001f [4:0]   : DP_PULLDN_TRIM (0x1f): Value to drive to USB PHY
     io_rw_32 phy_trim;
-    io_rw_32 linestate_tuning;
-    io_rw_32 intr;
+
+    uint32_t _pad0;
+
+    _REG_(USB_INTR_OFFSET) // USB_INTR
+    // Raw Interrupts
+    // 0x00080000 [19]    : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
+    // 0x00040000 [18]    : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
+    // 0x00020000 [17]    : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
+    // 0x00010000 [16]    : SETUP_REQ (0): Device
+    // 0x00008000 [15]    : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
+    // 0x00004000 [14]    : DEV_SUSPEND (0): Set when the device suspend state changes
+    // 0x00002000 [13]    : DEV_CONN_DIS (0): Set when the device connection state changes
+    // 0x00001000 [12]    : BUS_RESET (0): Source: SIE_STATUS
+    // 0x00000800 [11]    : VBUS_DETECT (0): Source: SIE_STATUS
+    // 0x00000400 [10]    : STALL (0): Source: SIE_STATUS
+    // 0x00000200 [9]     : ERROR_CRC (0): Source: SIE_STATUS
+    // 0x00000100 [8]     : ERROR_BIT_STUFF (0): Source: SIE_STATUS
+    // 0x00000080 [7]     : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
+    // 0x00000040 [6]     : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
+    // 0x00000020 [5]     : ERROR_DATA_SEQ (0): Source: SIE_STATUS
+    // 0x00000010 [4]     : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
+    // 0x00000008 [3]     : TRANS_COMPLETE (0): Raised every time SIE_STATUS
+    // 0x00000004 [2]     : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
+    // 0x00000002 [1]     : HOST_RESUME (0): Host: raised when a device wakes up the host
+    // 0x00000001 [0]     : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
+    io_ro_32 intr;
+
+    _REG_(USB_INTE_OFFSET) // USB_INTE
+    // Interrupt Enable
+    // 0x00080000 [19]    : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
+    // 0x00040000 [18]    : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
+    // 0x00020000 [17]    : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
+    // 0x00010000 [16]    : SETUP_REQ (0): Device
+    // 0x00008000 [15]    : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
+    // 0x00004000 [14]    : DEV_SUSPEND (0): Set when the device suspend state changes
+    // 0x00002000 [13]    : DEV_CONN_DIS (0): Set when the device connection state changes
+    // 0x00001000 [12]    : BUS_RESET (0): Source: SIE_STATUS
+    // 0x00000800 [11]    : VBUS_DETECT (0): Source: SIE_STATUS
+    // 0x00000400 [10]    : STALL (0): Source: SIE_STATUS
+    // 0x00000200 [9]     : ERROR_CRC (0): Source: SIE_STATUS
+    // 0x00000100 [8]     : ERROR_BIT_STUFF (0): Source: SIE_STATUS
+    // 0x00000080 [7]     : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
+    // 0x00000040 [6]     : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
+    // 0x00000020 [5]     : ERROR_DATA_SEQ (0): Source: SIE_STATUS
+    // 0x00000010 [4]     : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
+    // 0x00000008 [3]     : TRANS_COMPLETE (0): Raised every time SIE_STATUS
+    // 0x00000004 [2]     : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
+    // 0x00000002 [1]     : HOST_RESUME (0): Host: raised when a device wakes up the host
+    // 0x00000001 [0]     : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
     io_rw_32 inte;
+
+    _REG_(USB_INTF_OFFSET) // USB_INTF
+    // Interrupt Force
+    // 0x00080000 [19]    : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
+    // 0x00040000 [18]    : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
+    // 0x00020000 [17]    : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
+    // 0x00010000 [16]    : SETUP_REQ (0): Device
+    // 0x00008000 [15]    : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
+    // 0x00004000 [14]    : DEV_SUSPEND (0): Set when the device suspend state changes
+    // 0x00002000 [13]    : DEV_CONN_DIS (0): Set when the device connection state changes
+    // 0x00001000 [12]    : BUS_RESET (0): Source: SIE_STATUS
+    // 0x00000800 [11]    : VBUS_DETECT (0): Source: SIE_STATUS
+    // 0x00000400 [10]    : STALL (0): Source: SIE_STATUS
+    // 0x00000200 [9]     : ERROR_CRC (0): Source: SIE_STATUS
+    // 0x00000100 [8]     : ERROR_BIT_STUFF (0): Source: SIE_STATUS
+    // 0x00000080 [7]     : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
+    // 0x00000040 [6]     : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
+    // 0x00000020 [5]     : ERROR_DATA_SEQ (0): Source: SIE_STATUS
+    // 0x00000010 [4]     : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
+    // 0x00000008 [3]     : TRANS_COMPLETE (0): Raised every time SIE_STATUS
+    // 0x00000004 [2]     : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
+    // 0x00000002 [1]     : HOST_RESUME (0): Host: raised when a device wakes up the host
+    // 0x00000001 [0]     : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
     io_rw_32 intf;
-    io_rw_32 ints;
-} usb_hw_t;
 
-check_hw_layout(usb_hw_t, ints, USB_INTS_OFFSET);
+    _REG_(USB_INTS_OFFSET) // USB_INTS
+    // Interrupt status after masking & forcing
+    // 0x00080000 [19]    : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
+    // 0x00040000 [18]    : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
+    // 0x00020000 [17]    : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
+    // 0x00010000 [16]    : SETUP_REQ (0): Device
+    // 0x00008000 [15]    : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
+    // 0x00004000 [14]    : DEV_SUSPEND (0): Set when the device suspend state changes
+    // 0x00002000 [13]    : DEV_CONN_DIS (0): Set when the device connection state changes
+    // 0x00001000 [12]    : BUS_RESET (0): Source: SIE_STATUS
+    // 0x00000800 [11]    : VBUS_DETECT (0): Source: SIE_STATUS
+    // 0x00000400 [10]    : STALL (0): Source: SIE_STATUS
+    // 0x00000200 [9]     : ERROR_CRC (0): Source: SIE_STATUS
+    // 0x00000100 [8]     : ERROR_BIT_STUFF (0): Source: SIE_STATUS
+    // 0x00000080 [7]     : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
+    // 0x00000040 [6]     : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
+    // 0x00000020 [5]     : ERROR_DATA_SEQ (0): Source: SIE_STATUS
+    // 0x00000010 [4]     : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
+    // 0x00000008 [3]     : TRANS_COMPLETE (0): Raised every time SIE_STATUS
+    // 0x00000004 [2]     : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
+    // 0x00000002 [1]     : HOST_RESUME (0): Host: raised when a device wakes up the host
+    // 0x00000001 [0]     : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
+    io_ro_32 ints;
+} usb_hw_t;
 
-#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE)
+#define usb_hw ((usb_hw_t *const)USBCTRL_REGS_BASE)
 
 #define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE)
 #define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE)
 
+static_assert( USB_HOST_INTERRUPT_ENDPOINTS == 15, "");
+
 #endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h b/src/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h
index 9956d6831..554d9e447 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,12 +10,37 @@
 #define _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/vreg_and_chip_reset.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_vreg_and_chip_reset
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/vreg_and_chip_reset.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(VREG_AND_CHIP_RESET_VREG_OFFSET) // VREG_AND_CHIP_RESET_VREG
+    // Voltage regulator control and status
+    // 0x00001000 [12]    : ROK (0): regulation status
+    // 0x000000f0 [7:4]   : VSEL (0xb): output voltage select
+    // 0x00000002 [1]     : HIZ (0): high impedance mode select
+    // 0x00000001 [0]     : EN (1): enable
     io_rw_32 vreg;
+
+    _REG_(VREG_AND_CHIP_RESET_BOD_OFFSET) // VREG_AND_CHIP_RESET_BOD
+    // brown-out detection control
+    // 0x000000f0 [7:4]   : VSEL (0x9): threshold select
+    // 0x00000001 [0]     : EN (1): enable
     io_rw_32 bod;
+
+    _REG_(VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET) // VREG_AND_CHIP_RESET_CHIP_RESET
+    // Chip reset control and status
+    // 0x01000000 [24]    : PSM_RESTART_FLAG (0): This is set by psm_restart from the debugger
+    // 0x00100000 [20]    : HAD_PSM_RESTART (0): Last reset was from the debug port
+    // 0x00010000 [16]    : HAD_RUN (0): Last reset was from the RUN pin
+    // 0x00000100 [8]     : HAD_POR (0): Last reset was from the power-on reset or brown-out detection blocks
     io_rw_32 chip_reset;
 } vreg_and_chip_reset_hw_t;
 
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/watchdog.h b/src/rp2040/hardware_structs/include/hardware/structs/watchdog.h
index 2cf05f19d..9579700b6 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/watchdog.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/watchdog.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,14 +10,50 @@
 #define _HARDWARE_STRUCTS_WATCHDOG_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/watchdog.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_watchdog
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/watchdog.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(WATCHDOG_CTRL_OFFSET) // WATCHDOG_CTRL
+    // Watchdog control
+    // 0x80000000 [31]    : TRIGGER (0): Trigger a watchdog reset
+    // 0x40000000 [30]    : ENABLE (0): When not enabled the watchdog timer is paused
+    // 0x04000000 [26]    : PAUSE_DBG1 (1): Pause the watchdog timer when processor 1 is in debug mode
+    // 0x02000000 [25]    : PAUSE_DBG0 (1): Pause the watchdog timer when processor 0 is in debug mode
+    // 0x01000000 [24]    : PAUSE_JTAG (1): Pause the watchdog timer when JTAG is accessing the bus fabric
+    // 0x00ffffff [23:0]  : TIME (0): Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will...
     io_rw_32 ctrl;
+
+    _REG_(WATCHDOG_LOAD_OFFSET) // WATCHDOG_LOAD
+    // Load the watchdog timer
+    // 0x00ffffff [23:0]  : LOAD (0)
     io_wo_32 load;
+
+    _REG_(WATCHDOG_REASON_OFFSET) // WATCHDOG_REASON
+    // Logs the reason for the last reset
+    // 0x00000002 [1]     : FORCE (0)
+    // 0x00000001 [0]     : TIMER (0)
     io_ro_32 reason;
+
+    _REG_(WATCHDOG_SCRATCH0_OFFSET) // WATCHDOG_SCRATCH0
+    // (Description copied from array index 0 register WATCHDOG_SCRATCH0 applies similarly to other array indexes)
+    //
+    // Scratch register
     io_rw_32 scratch[8];
+
+    _REG_(WATCHDOG_TICK_OFFSET) // WATCHDOG_TICK
+    // Controls the tick generator
+    // 0x000ff800 [19:11] : COUNT (0): Count down timer: the remaining number clk_tick cycles before the next tick is generated
+    // 0x00000400 [10]    : RUNNING (0): Is the tick generator running?
+    // 0x00000200 [9]     : ENABLE (1): start / stop tick generation
+    // 0x000001ff [8:0]   : CYCLES (0): Total number of clk_tick cycles before the next tick
     io_rw_32 tick;
 } watchdog_hw_t;
 
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h b/src/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h
index bfa5b1c0c..21885e867 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h
@@ -1,29 +1,72 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
+
 #ifndef _HARDWARE_STRUCTS_XIP_CTRL_H
 #define _HARDWARE_STRUCTS_XIP_CTRL_H
 
 #include "hardware/address_mapped.h"
 #include "hardware/regs/xip.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xip
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/xip.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(XIP_CTRL_OFFSET) // XIP_CTRL
+    // Cache control
+    // 0x00000008 [3]     : POWER_DOWN (0): When 1, the cache memories are powered down
+    // 0x00000002 [1]     : ERR_BADWRITE (1): When 1, writes to any alias other than 0x0 (caching, allocating)
+    // 0x00000001 [0]     : EN (1): When 1, enable the cache
     io_rw_32 ctrl;
+
+    _REG_(XIP_FLUSH_OFFSET) // XIP_FLUSH
+    // Cache Flush control
+    // 0x00000001 [0]     : FLUSH (0): Write 1 to flush the cache
     io_rw_32 flush;
-    io_rw_32 stat;
+
+    _REG_(XIP_STAT_OFFSET) // XIP_STAT
+    // Cache Status
+    // 0x00000004 [2]     : FIFO_FULL (0): When 1, indicates the XIP streaming FIFO is completely full
+    // 0x00000002 [1]     : FIFO_EMPTY (1): When 1, indicates the XIP streaming FIFO is completely empty
+    // 0x00000001 [0]     : FLUSH_READY (0): Reads as 0 while a cache flush is in progress, and 1 otherwise
+    io_ro_32 stat;
+
+    _REG_(XIP_CTR_HIT_OFFSET) // XIP_CTR_HIT
+    // Cache Hit counter
     io_rw_32 ctr_hit;
+
+    _REG_(XIP_CTR_ACC_OFFSET) // XIP_CTR_ACC
+    // Cache Access counter
     io_rw_32 ctr_acc;
+
+    _REG_(XIP_STREAM_ADDR_OFFSET) // XIP_STREAM_ADDR
+    // FIFO stream address
+    // 0xfffffffc [31:2]  : STREAM_ADDR (0): The address of the next word to be streamed from flash to the streaming FIFO
     io_rw_32 stream_addr;
+
+    _REG_(XIP_STREAM_CTR_OFFSET) // XIP_STREAM_CTR
+    // FIFO stream control
+    // 0x003fffff [21:0]  : STREAM_CTR (0): Write a nonzero value to start a streaming read
     io_rw_32 stream_ctr;
-    io_rw_32 stream_fifo;
-} xip_ctrl_hw_t;
 
-#define XIP_STAT_FIFO_FULL     0x4u
-#define XIP_STAT_FIFO_EMPTY    0x2u
-#define XIP_STAT_FLUSH_RDY     0x1u
+    _REG_(XIP_STREAM_FIFO_OFFSET) // XIP_STREAM_FIFO
+    // FIFO stream data
+    io_ro_32 stream_fifo;
+} xip_ctrl_hw_t;
 
 #define xip_ctrl_hw ((xip_ctrl_hw_t *const)XIP_CTRL_BASE)
 
+#define XIP_STAT_FIFO_FULL XIP_STAT_FIFO_FULL_BITS
+#define XIP_STAT_FIFO_EMPTY XIP_STAT_FIFO_EMPTY_BITS
+#define XIP_STAT_FLUSH_RDY XIP_STAT_FLUSH_READY_BITS
+
 #endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/xosc.h b/src/rp2040/hardware_structs/include/hardware/structs/xosc.h
index 698e6a2ff..0ff4db487 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/xosc.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/xosc.h
@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,16 +10,47 @@
 #define _HARDWARE_STRUCTS_XOSC_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/xosc.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xosc
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/xosc.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 /// \tag::xosc_hw[]
 typedef struct {
+    _REG_(XOSC_CTRL_OFFSET) // XOSC_CTRL
+    // Crystal Oscillator Control
+    // 0x00fff000 [23:12] : ENABLE (0): On power-up this field is initialised to DISABLE and the chip runs from the ROSC
+    // 0x00000fff [11:0]  : FREQ_RANGE (0): Frequency range
     io_rw_32 ctrl;
+
+    _REG_(XOSC_STATUS_OFFSET) // XOSC_STATUS
+    // Crystal Oscillator Status
+    // 0x80000000 [31]    : STABLE (0): Oscillator is running and stable
+    // 0x01000000 [24]    : BADWRITE (0): An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT
+    // 0x00001000 [12]    : ENABLED (0): Oscillator is enabled but not necessarily running and stable, resets to 0
+    // 0x00000003 [1:0]   : FREQ_RANGE (0): The current frequency range setting, always reads 0
     io_rw_32 status;
+
+    _REG_(XOSC_DORMANT_OFFSET) // XOSC_DORMANT
+    // Crystal Oscillator pause control
     io_rw_32 dormant;
+
+    _REG_(XOSC_STARTUP_OFFSET) // XOSC_STARTUP
+    // Controls the startup delay
+    // 0x00100000 [20]    : X4 (0): Multiplies the startup_delay by 4
+    // 0x00003fff [13:0]  : DELAY (0xc4): in multiples of 256*xtal_period
     io_rw_32 startup;
-    io_rw_32 _reserved[3];
+
+    uint32_t _pad0[3];
+
+    _REG_(XOSC_COUNT_OFFSET) // XOSC_COUNT
+    // A down counter running at the xosc frequency which counts to zero and stops
+    // 0x000000ff [7:0]   : COUNT (0)
     io_rw_32 count;
 } xosc_hw_t;
 
diff --git a/src/rp2_common.cmake b/src/rp2_common.cmake
index 76126602f..c04e55144 100644
--- a/src/rp2_common.cmake
+++ b/src/rp2_common.cmake
@@ -3,17 +3,17 @@
 enable_language(ASM)
 
 function(pico_add_hex_output TARGET)
-    add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Oihex ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} ${TARGET}.hex)
+    add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${TARGET}> $<IF:$<BOOL:$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>>,$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>,$<TARGET_PROPERTY:${TARGET},NAME>>.hex)
 endfunction()
 
 function(pico_add_bin_output TARGET)
-    add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Obinary ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} ${TARGET}.bin)
+    add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${TARGET}> $<IF:$<BOOL:$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>>,$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>,$<TARGET_PROPERTY:${TARGET},NAME>>.bin)
 endfunction()
 
 function(pico_add_dis_output TARGET)
     add_custom_command(TARGET ${TARGET} POST_BUILD
-            COMMAND ${CMAKE_OBJDUMP} -h ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} >${TARGET}.dis
-            COMMAND ${CMAKE_OBJDUMP} -d ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} >>${TARGET}.dis
+            COMMAND ${CMAKE_OBJDUMP} -h $<TARGET_FILE:${TARGET}> >$<IF:$<BOOL:$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>>,$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>,$<TARGET_PROPERTY:${TARGET},NAME>>.dis
+            COMMAND ${CMAKE_OBJDUMP} -d $<TARGET_FILE:${TARGET}> >>$<IF:$<BOOL:$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>>,$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>,$<TARGET_PROPERTY:${TARGET},NAME>>.dis
             )
 endfunction()
 
@@ -36,8 +36,8 @@ function(pico_add_extra_outputs TARGET)
 
         add_custom_command(TARGET ${TARGET}_symlinked POST_BUILD
                 COMMAND rm -f "${PICO_SYMLINK_ELF_AS_FILENAME}"
-                COMMAND ln -s -r ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} "${PICO_SYMLINK_ELF_AS_FILENAME}"
-                COMMENT "Symlinking from ${PICO_SYMLINK_ELF_AS_FILENAME} to ${TARGET}${CMAKE_EXECUTABLE_SUFFIX}"
+                COMMAND ln -s -r $<TARGET_FILE:${TARGET}> "${PICO_SYMLINK_ELF_AS_FILENAME}"
+                COMMENT "Symlinking from ${PICO_SYMLINK_ELF_AS_FILENAME} to ${TARGET}"
                 )
     endif ()
     # PICO_CMAKE_CONFIG: PICO_NO_UF2, Disable UF2 output, type=bool, default=0, group=build
diff --git a/src/rp2_common/CMakeLists.txt b/src/rp2_common/CMakeLists.txt
index 0277c8d49..4ca55becb 100644
--- a/src/rp2_common/CMakeLists.txt
+++ b/src/rp2_common/CMakeLists.txt
@@ -72,5 +72,6 @@ endif()
 set(CMAKE_EXECUTABLE_SUFFIX "${CMAKE_EXECUTABLE_SUFFIX}" PARENT_SCOPE)
 
 pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR})
+pico_add_doxygen_exclude(${CMAKE_CURRENT_LIST_DIR}/cmsis)
 
 pico_promote_common_scope_vars()
\ No newline at end of file
diff --git a/src/rp2_common/boot_stage2/CMakeLists.txt b/src/rp2_common/boot_stage2/CMakeLists.txt
index 73c3e3e94..a2f3960d8 100644
--- a/src/rp2_common/boot_stage2/CMakeLists.txt
+++ b/src/rp2_common/boot_stage2/CMakeLists.txt
@@ -4,7 +4,7 @@
 if (DEFINED ENV{PICO_DEFAULT_BOOT_STAGE2_FILE})
     set(PICO_DEFAULT_BOOT_STAGE2_FILE $ENV{PICO_DEFAULT_BOOT_STAGE2_FILE})
     message("Using PICO_DEFAULT_BOOT_STAGE2_FILE from environment ('${PICO_DEFAULT_BOOT_STAGE2_FILE}')")
-elif (PICO_DEFAULT_BOOT_STAGE2_FILE)
+elseif (PICO_DEFAULT_BOOT_STAGE2_FILE)
     # explicitly set, so cache it
     set(PICO_DEFAULT_BOOT_STAGE2_FILE "${PICO_DEFAULT_BOOT_STAGE2_FILE}" CACHE STRING "boot stage 2 source file" FORCE)
 endif()
@@ -25,6 +25,7 @@ endif()
 if (NOT EXISTS ${PICO_DEFAULT_BOOT_STAGE2_FILE})
     message(FATAL_ERROR "Specified boot stage 2 source '${PICO_DEFAULT_BOOT_STAGE2_FILE}' does not exist.")
 endif()
+pico_register_common_scope_var(PICO_DEFAULT_BOOT_STAGE2_FILE)
 
 # needed by function below
 set(PICO_BOOT_STAGE2_DIR "${CMAKE_CURRENT_LIST_DIR}" CACHE INTERNAL "")
@@ -98,3 +99,9 @@ endmacro()
 
 pico_define_boot_stage2(bs2_default ${PICO_DEFAULT_BOOT_STAGE2_FILE})
 
+# Create a new boot stage 2 target using the default implementation for the current build (PICO_BOARD derived)
+function(pico_clone_default_boot_stage2 NAME)
+    pico_define_boot_stage2(${NAME} ${PICO_DEFAULT_BOOT_STAGE2_FILE})
+endfunction()
+
+pico_promote_common_scope_vars()
\ No newline at end of file
diff --git a/src/rp2_common/hardware_adc/include/hardware/adc.h b/src/rp2_common/hardware_adc/include/hardware/adc.h
index 35586a634..be82025a5 100644
--- a/src/rp2_common/hardware_adc/include/hardware/adc.h
+++ b/src/rp2_common/hardware_adc/include/hardware/adc.h
@@ -19,7 +19,7 @@
  * The RP2040 has an internal analogue-digital converter (ADC) with the following features:
  * - SAR ADC
  * - 500 kS/s (Using an independent 48MHz clock)
- * - 12 bit (9.5 ENOB)
+ * - 12 bit (8.7 ENOB)
  * - 5 input mux:
  *  - 4 inputs that are available on package pins shared with GPIO[29:26]
  *  - 1 input is dedicated to the internal temperature sensor
@@ -28,7 +28,7 @@
  * - DMA interface
  *
  * Although there is only one ADC you can specify the input to it using the adc_select_input() function.
- * In round robin mode (adc_rrobin()) will use that input and move to the next one after a read.
+ * In round robin mode (adc_set_round_robin()), the ADC will use that input and move to the next one after a read.
  *
  * User ADC inputs are on 0-3 (GPIO 26-29), the temperature sensor is on input 4.
  *
@@ -62,7 +62,7 @@ void adc_init(void);
 /*! \brief  Initialise the gpio for use as an ADC pin
  *  \ingroup hardware_adc
  *
- * Prepare a GPIO for use with ADC, by disabling all digital functions.
+ * Prepare a GPIO for use with ADC by disabling all digital functions.
  *
  * \param gpio The GPIO number to use. Allowable GPIO numbers are 26 to 29 inclusive.
  */
@@ -167,7 +167,7 @@ static inline void adc_set_clkdiv(float clkdiv) {
 /*! \brief Setup the ADC FIFO
  *  \ingroup hardware_adc
  *
- * FIFO is 4 samples long, if a conversion is completed and the FIFO is full the result is dropped.
+ * FIFO is 4 samples long, if a conversion is completed and the FIFO is full, the result is dropped.
  *
  * \param en Enables write each conversion result to the FIFO
  * \param dreq_en Enable DMA requests when FIFO contains data
@@ -193,7 +193,7 @@ static inline void adc_set_clkdiv(float clkdiv) {
 /*! \brief Check FIFO empty state
  *  \ingroup hardware_adc
  *
- * \return Returns true if the fifo is empty
+ * \return Returns true if the FIFO is empty
  */
 static inline bool adc_fifo_is_empty(void) {
     return !!(adc_hw->fcs & ADC_FCS_EMPTY_BITS);
@@ -231,7 +231,7 @@ static inline uint16_t adc_fifo_get_blocking(void) {
 /*! \brief Drain the ADC FIFO
  *  \ingroup hardware_adc
  *
- * Will wait for any conversion to complete then drain the FIFO discarding any results.
+ * Will wait for any conversion to complete then drain the FIFO, discarding any results.
  */
 static inline void adc_fifo_drain(void) {
     // Potentially there is still a conversion in progress -- wait for this to complete before draining
diff --git a/src/rp2_common/hardware_base/include/hardware/address_mapped.h b/src/rp2_common/hardware_base/include/hardware/address_mapped.h
index b58f1e50d..a3b958413 100644
--- a/src/rp2_common/hardware_base/include/hardware/address_mapped.h
+++ b/src/rp2_common/hardware_base/include/hardware/address_mapped.h
@@ -55,6 +55,11 @@ extern "C" {
 #define check_hw_layout(type, member, offset) static_assert(offsetof(type, member) == (offset), "hw offset mismatch")
 #define check_hw_size(type, size) static_assert(sizeof(type) == (size), "hw size mismatch")
 
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS, Enable/disable assertions in memory address aliasing macros, type=bool, default=0, group=hardware_base
+#ifndef PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS
+#define PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS 0
+#endif
+
 typedef volatile uint32_t io_rw_32;
 typedef const volatile uint32_t io_ro_32;
 typedef volatile uint32_t io_wo_32;
@@ -68,15 +73,44 @@ typedef volatile uint8_t io_wo_8;
 typedef volatile uint8_t *const ioptr;
 typedef ioptr const const_ioptr;
 
+// A non-functional (empty) helper macro to help IDEs follow links from the autogenerated
+// hardware struct headers in hardware/structs/xxx.h to the raw register definitions
+// in hardware/regs/xxx.h. A preprocessor define such as TIMER_TIMEHW_OFFSET (a timer register offset)
+// is not generally clickable (in an IDE) if placed in a C comment, so _REG_(TIMER_TIMEHW_OFFSET) is
+// included outside of a comment instead
+#define _REG_(x)
+
+// Helper method used by hw_alias macros to optionally check input validity
+#define hw_alias_check_addr(addr) ((uintptr_t)(addr))
+// can't use the following impl as it breaks existing static declarations using hw_alias, so would be a backwards incompatibility
+//static __force_inline uint32_t hw_alias_check_addr(volatile void *addr) {
+//    uint32_t rc = (uintptr_t)addr;
+//    invalid_params_if(ADDRESS_ALIAS, rc < 0x40000000); // catch likely non HW pointer types
+//    return rc;
+//}
+
+// Helper method used by xip_alias macros to optionally check input validity
+static __force_inline uint32_t xip_alias_check_addr(const void *addr) {
+    uint32_t rc = (uintptr_t)addr;
+    valid_params_if(ADDRESS_ALIAS, rc >= XIP_MAIN_BASE && rc < XIP_NOALLOC_BASE);
+    return rc;
+}
+
 // Untyped conversion alias pointer generation macros
-#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS | (uintptr_t)(addr)))
-#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS | (uintptr_t)(addr)))
-#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS | (uintptr_t)(addr)))
+#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS | hw_alias_check_addr(addr)))
+#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS | hw_alias_check_addr(addr)))
+#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS | hw_alias_check_addr(addr)))
+#define xip_noalloc_alias_untyped(addr) ((void *)(XIP_NOALLOC_BASE | xip_alias_check_addr(addr)))
+#define xip_nocache_alias_untyped(addr) ((void *)(XIP_NOCACHE_BASE | xip_alias_check_addr(addr)))
+#define xip_nocache_noalloc_alias_untyped(addr) ((void *)(XIP_NOCACHE_NOALLOC_BASE | xip_alias_check_addr(addr)))
 
 // Typed conversion alias pointer generation macros
 #define hw_set_alias(p) ((typeof(p))hw_set_alias_untyped(p))
 #define hw_clear_alias(p) ((typeof(p))hw_clear_alias_untyped(p))
 #define hw_xor_alias(p) ((typeof(p))hw_xor_alias_untyped(p))
+#define xip_noalloc_alias(p) ((typeof(p))xip_noalloc_alias_untyped(p))
+#define xip_nocache_alias(p) ((typeof(p))xip_nocache_alias_untyped(p))
+#define xip_nocache_noalloc_alias(p) ((typeof(p))xip_nocache_noalloc_alias_untyped(p))
 
 /*! \brief Atomically set the specified bits to 1 in a HW register
  *  \ingroup hardware_base
diff --git a/src/rp2_common/hardware_dma/dma.c b/src/rp2_common/hardware_dma/dma.c
index 230fa1681..90fde06b4 100644
--- a/src/rp2_common/hardware_dma/dma.c
+++ b/src/rp2_common/hardware_dma/dma.c
@@ -18,6 +18,7 @@ static_assert(__builtin_offsetof(dma_hw_t, ch[1].ctrl_trig) == DMA_CH1_CTRL_TRIG
 
 static_assert(NUM_DMA_CHANNELS <= 16, "");
 static uint16_t _claimed;
+static uint8_t _timer_claimed;
 
 void dma_channel_claim(uint channel) {
     check_dma_channel_param(channel);
@@ -44,6 +45,25 @@ bool dma_channel_is_claimed(uint channel) {
     return hw_is_claimed((uint8_t *) &_claimed, channel);
 }
 
+void dma_timer_claim(uint timer) {
+    check_dma_timer_param(timer);
+    hw_claim_or_assert(&_timer_claimed, timer, "DMA timer %d is already claimed");
+}
+
+void dma_timer_unclaim(uint timer) {
+    check_dma_timer_param(timer);
+    hw_claim_clear(&_timer_claimed, timer);
+}
+
+int dma_claim_unused_timer(bool required) {
+    return hw_claim_unused_from_range(&_timer_claimed, required, 0, NUM_DMA_TIMERS-1, "No DMA timers are available");
+}
+
+bool dma_timer_is_claimed(uint timer) {
+    check_dma_timer_param(timer);
+    return hw_is_claimed(&_timer_claimed, timer);
+}
+
 #ifndef NDEBUG
 
 void print_dma_ctrl(dma_channel_hw_t *channel) {
diff --git a/src/rp2_common/hardware_dma/include/hardware/dma.h b/src/rp2_common/hardware_dma/include/hardware/dma.h
index 526d63236..7c9406f31 100644
--- a/src/rp2_common/hardware_dma/include/hardware/dma.h
+++ b/src/rp2_common/hardware_dma/include/hardware/dma.h
@@ -54,6 +54,10 @@ static inline void check_dma_channel_param(__unused uint channel) {
 #endif
 }
 
+static inline void check_dma_timer_param(__unused uint timer_num) {
+    valid_params_if(DMA, timer_num < NUM_DMA_TIMERS);
+}
+
 inline static dma_channel_hw_t *dma_channel_hw_addr(uint channel) {
     check_dma_channel_param(channel);
     return &dma_hw->ch[channel];
@@ -715,6 +719,71 @@ inline static void dma_sniffer_disable(void) {
     dma_hw->sniff_ctrl = 0;
 }
 
+/*! \brief Mark a dma timer as used
+ *  \ingroup hardware_dma
+ *
+ * Method for cooperative claiming of hardware. Will cause a panic if the timer
+ * is already claimed. Use of this method by libraries detects accidental
+ * configurations that would fail in unpredictable ways.
+ *
+ * \param timer the dma timer
+ */
+void dma_timer_claim(uint timer);
+
+/*! \brief Mark a dma timer as no longer used
+ *  \ingroup hardware_dma
+ *
+ * Method for cooperative claiming of hardware.
+ *
+ * \param timer the dma timer to release
+ */
+void dma_timer_unclaim(uint timer);
+
+/*! \brief Claim a free dma timer
+ *  \ingroup hardware_dma
+ *
+ * \param required if true the function will panic if none are available
+ * \return the dma timer number or -1 if required was false, and none were free
+ */
+int dma_claim_unused_timer(bool required);
+
+/*! \brief Determine if a dma timer is claimed
+ *  \ingroup hardware_dma
+ *
+ * \param timer the dma timer
+ * \return true if the timer is claimed, false otherwise
+ * \see dma_timer_claim
+ */
+bool dma_timer_is_claimed(uint timer);
+
+/*! \brief Set the divider for the given DMA timer
+ *  \ingroup hardware_dma
+ *
+ * The timer will run at the system_clock_freq * numerator / denominator, so this is the speed
+ * that data elements will be transferred at via a DMA channel using this timer as a DREQ
+ *
+ * \param timer the dma timer
+ * \param numerator the fraction's numerator
+ * \param denominator the fraction's denominator
+ */
+static inline void dma_timer_set_fraction(uint timer, uint16_t numerator, uint16_t denominator) {
+    check_dma_timer_param(timer);
+    dma_hw->timer[timer] = (((uint32_t)numerator) << DMA_TIMER0_X_LSB) | (((uint32_t)denominator) << DMA_TIMER0_Y_LSB);
+}
+
+/*! \brief Return the DREQ number for a given DMA timer
+ *  \ingroup hardware_dma
+ *
+ * \param timer_num DMA timer number 0-3
+ */
+static inline uint dma_get_timer_dreq(uint timer_num) {
+    static_assert(DREQ_DMA_TIMER1 == DREQ_DMA_TIMER0 + 1, "");
+    static_assert(DREQ_DMA_TIMER2 == DREQ_DMA_TIMER0 + 2, "");
+    static_assert(DREQ_DMA_TIMER3 == DREQ_DMA_TIMER0 + 3, "");
+    check_dma_timer_param(timer_num);
+    return DREQ_DMA_TIMER0 + timer_num;
+}
+
 #ifndef NDEBUG
 void print_dma_ctrl(dma_channel_hw_t *channel);
 #endif
diff --git a/src/rp2_common/hardware_exception/include/hardware/exception.h b/src/rp2_common/hardware_exception/include/hardware/exception.h
index 0b805d77d..005168bcd 100644
--- a/src/rp2_common/hardware_exception/include/hardware/exception.h
+++ b/src/rp2_common/hardware_exception/include/hardware/exception.h
@@ -16,7 +16,7 @@
  *
  * Methods for setting processor exception handlers
  *
- * Exceptions are identified by a \ref exception_num which is a number from -15 to -1; these are the numbers relative to
+ * Exceptions are identified by a \ref exception_number which is a number from -15 to -1; these are the numbers relative to
  * the index of the first IRQ vector in the vector table. (i.e. vector table index is exception_num plus 16)
  *
  * There is one set of exception handlers per core, so the exception handlers for each core as set by these methods are independent.
@@ -85,11 +85,11 @@ exception_handler_t exception_set_exclusive_handler(enum exception_number num, e
  * prior to the call to exception_set_exclusive_handler(), so that exception_set_exclusive_handler()
  * may be called again in the future.
  *
- * \param num Exception number \ref exception_nums
+ * \param num Exception number \ref exception_number
  * \param original_handler The original handler returned from \ref exception_set_exclusive_handler
  * \see exception_set_exclusive_handler()
  */
-void exception_restore_handler(enum exception_number, exception_handler_t original_handler);
+void exception_restore_handler(enum exception_number num, exception_handler_t original_handler);
 
 /*! \brief Get the current exception handler for the specified exception from the currently installed vector table
  * of the execution core
diff --git a/src/rp2_common/hardware_flash/flash.c b/src/rp2_common/hardware_flash/flash.c
index dc9d8334b..56993026b 100644
--- a/src/rp2_common/hardware_flash/flash.c
+++ b/src/rp2_common/hardware_flash/flash.c
@@ -50,7 +50,7 @@ static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)(void) {}
 
 static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)(void) {
     // Set up XIP for 03h read on bus access (slow but generic)
-    void (*flash_enter_cmd_xip)(void) = (void(*)(void))rom_func_lookup(rom_table_code('C', 'X'));
+    rom_flash_enter_cmd_xip_fn flash_enter_cmd_xip = (rom_flash_enter_cmd_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_ENTER_CMD_XIP);
     assert(flash_enter_cmd_xip);
     flash_enter_cmd_xip();
 }
@@ -66,11 +66,10 @@ void __no_inline_not_in_flash_func(flash_range_erase)(uint32_t flash_offs, size_
 #endif
     invalid_params_if(FLASH, flash_offs & (FLASH_SECTOR_SIZE - 1));
     invalid_params_if(FLASH, count & (FLASH_SECTOR_SIZE - 1));
-    void (*connect_internal_flash)(void) = (void(*)(void))rom_func_lookup(rom_table_code('I', 'F'));
-    void (*flash_exit_xip)(void) = (void(*)(void))rom_func_lookup(rom_table_code('E', 'X'));
-    void (*flash_range_erase)(uint32_t, size_t, uint32_t, uint8_t) =
-        (void(*)(uint32_t, size_t, uint32_t, uint8_t))rom_func_lookup(rom_table_code('R', 'E'));
-    void (*flash_flush_cache)(void) = (void(*)(void))rom_func_lookup(rom_table_code('F', 'C'));
+    rom_connect_internal_flash_fn connect_internal_flash = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH);
+    rom_flash_exit_xip_fn flash_exit_xip = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP);
+    rom_flash_range_erase_fn flash_range_erase = (rom_flash_range_erase_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_ERASE);
+    rom_flash_flush_cache_fn flash_flush_cache = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE);
     assert(connect_internal_flash && flash_exit_xip && flash_range_erase && flash_flush_cache);
     flash_init_boot2_copyout();
 
@@ -90,11 +89,10 @@ void __no_inline_not_in_flash_func(flash_range_program)(uint32_t flash_offs, con
 #endif
     invalid_params_if(FLASH, flash_offs & (FLASH_PAGE_SIZE - 1));
     invalid_params_if(FLASH, count & (FLASH_PAGE_SIZE - 1));
-    void (*connect_internal_flash)(void) = (void(*)(void))rom_func_lookup(rom_table_code('I', 'F'));
-    void (*flash_exit_xip)(void) = (void(*)(void))rom_func_lookup(rom_table_code('E', 'X'));
-    void (*flash_range_program)(uint32_t, const uint8_t*, size_t) =
-        (void(*)(uint32_t, const uint8_t*, size_t))rom_func_lookup(rom_table_code('R', 'P'));
-    void (*flash_flush_cache)(void) = (void(*)(void))rom_func_lookup(rom_table_code('F', 'C'));
+    rom_connect_internal_flash_fn connect_internal_flash = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH);
+    rom_flash_exit_xip_fn flash_exit_xip = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP);
+    rom_flash_range_program_fn flash_range_program = (rom_flash_range_program_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_PROGRAM);
+    rom_flash_flush_cache_fn flash_flush_cache = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE);
     assert(connect_internal_flash && flash_exit_xip && flash_range_program && flash_flush_cache);
     flash_init_boot2_copyout();
 
@@ -124,9 +122,9 @@ static void __no_inline_not_in_flash_func(flash_cs_force)(bool high) {
 }
 
 void __no_inline_not_in_flash_func(flash_do_cmd)(const uint8_t *txbuf, uint8_t *rxbuf, size_t count) {
-    void (*connect_internal_flash)(void) = (void(*)(void))rom_func_lookup(rom_table_code('I', 'F'));
-    void (*flash_exit_xip)(void) = (void(*)(void))rom_func_lookup(rom_table_code('E', 'X'));
-    void (*flash_flush_cache)(void) = (void(*)(void))rom_func_lookup(rom_table_code('F', 'C'));
+    rom_connect_internal_flash_fn connect_internal_flash = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH);
+    rom_flash_exit_xip_fn flash_exit_xip = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP);
+    rom_flash_flush_cache_fn flash_flush_cache = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE);
     assert(connect_internal_flash && flash_exit_xip && flash_flush_cache);
     flash_init_boot2_copyout();
     __compiler_memory_barrier();
diff --git a/src/rp2_common/hardware_gpio/gpio.c b/src/rp2_common/hardware_gpio/gpio.c
index 10b15026f..2816b9718 100644
--- a/src/rp2_common/hardware_gpio/gpio.c
+++ b/src/rp2_common/hardware_gpio/gpio.c
@@ -142,7 +142,7 @@ static void gpio_irq_handler(void) {
     io_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ?
                                            &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl;
     for (uint gpio = 0; gpio < NUM_BANK0_GPIOS; gpio++) {
-        io_rw_32 *status_reg = &irq_ctrl_base->ints[gpio / 8];
+        io_ro_32 *status_reg = &irq_ctrl_base->ints[gpio / 8];
         uint events = (*status_reg >> 4 * (gpio % 8)) & 0xf;
         if (events) {
             // TODO: If both cores care about this event then the second core won't get the irq?
diff --git a/src/rp2_common/hardware_gpio/include/hardware/gpio.h b/src/rp2_common/hardware_gpio/include/hardware/gpio.h
index e90be27a4..7037e85d9 100644
--- a/src/rp2_common/hardware_gpio/include/hardware/gpio.h
+++ b/src/rp2_common/hardware_gpio/include/hardware/gpio.h
@@ -178,6 +178,12 @@ enum gpio_drive_strength {
  */
 void gpio_set_function(uint gpio, enum gpio_function fn);
 
+/*! \brief Determine current GPIO function
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \return Which GPIO function is currently selected from list \ref gpio_function
+ */
 enum gpio_function gpio_get_function(uint gpio);
 
 /*! \brief Select up and down pulls on specific GPIO
@@ -401,7 +407,7 @@ void gpio_acknowledge_irq(uint gpio, uint32_t events);
 /*! \brief Initialise a GPIO for (enabled I/O and set func to GPIO_FUNC_SIO)
  *  \ingroup hardware_gpio
  *
- * Clear the output enable (i.e. set to input)
+ * Clear the output enable (i.e. set to input).
  * Clear any output value.
  *
  * \param gpio GPIO number
@@ -411,7 +417,7 @@ void gpio_init(uint gpio);
 /*! \brief Initialise multiple GPIOs (enabled I/O and set func to GPIO_FUNC_SIO)
  *  \ingroup hardware_gpio
  *
- * Clear the output enable (i.e. set to input)
+ * Clear the output enable (i.e. set to input).
  * Clear any output value.
  *
  * \param gpio_mask Mask with 1 bit per GPIO number to initialize
diff --git a/src/rp2_common/hardware_i2c/i2c.c b/src/rp2_common/hardware_i2c/i2c.c
index 9d2e93160..95bcfea11 100644
--- a/src/rp2_common/hardware_i2c/i2c.c
+++ b/src/rp2_common/hardware_i2c/i2c.c
@@ -115,16 +115,18 @@ void i2c_set_slave_mode(i2c_inst_t *i2c, bool slave, uint8_t addr) {
     invalid_params_if(I2C, addr >= 0x80); // 7-bit addresses
     invalid_params_if(I2C, i2c_reserved_addr(addr));
     i2c->hw->enable = 0;
+    uint32_t ctrl_set_if_master = I2C_IC_CON_MASTER_MODE_BITS | I2C_IC_CON_IC_SLAVE_DISABLE_BITS;
+    uint32_t ctrl_set_if_slave = I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS;
     if (slave) {
-        hw_clear_bits(&i2c->hw->con,
-                      I2C_IC_CON_MASTER_MODE_BITS |
-                      I2C_IC_CON_IC_SLAVE_DISABLE_BITS
+        hw_write_masked(&i2c->hw->con,
+            ctrl_set_if_slave,
+            ctrl_set_if_master | ctrl_set_if_slave
         );
         i2c->hw->sar = addr;
     } else {
-        hw_set_bits(&i2c->hw->con,
-                    I2C_IC_CON_MASTER_MODE_BITS |
-                    I2C_IC_CON_IC_SLAVE_DISABLE_BITS
+        hw_write_masked(&i2c->hw->con,
+            ctrl_set_if_master,
+            ctrl_set_if_master | ctrl_set_if_slave
         );
     }
     i2c->hw->enable = 1;
diff --git a/src/rp2_common/hardware_i2c/include/hardware/i2c.h b/src/rp2_common/hardware_i2c/include/hardware/i2c.h
index 5cce6f88e..23ff8f169 100644
--- a/src/rp2_common/hardware_i2c/include/hardware/i2c.h
+++ b/src/rp2_common/hardware_i2c/include/hardware/i2c.h
@@ -10,6 +10,7 @@
 #include "pico.h"
 #include "pico/time.h"
 #include "hardware/structs/i2c.h"
+#include "hardware/regs/dreq.h"
 
 // PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_I2C, Enable/disable assertions in the I2C module, type=bool, default=0, group=hardware_i2c
 #ifndef PARAM_ASSERTIONS_ENABLED_I2C
@@ -26,10 +27,12 @@ extern "C" {
  * I2C Controller API
  *
  * The I2C bus is a two-wire serial interface, consisting of a serial data line SDA and a serial clock SCL. These wires carry
- * information between the devices connected to the bus. Each device is recognized by a unique address and can operate as
+ * information between the devices connected to the bus. Each device is recognized by a unique 7-bit address and can operate as
  * either a “transmitter” or “receiver”, depending on the function of the device. Devices can also be considered as masters or
  * slaves when performing data transfers. A master is a device that initiates a data transfer on the bus and generates the
- * clock signals to permit that transfer. At that time, any device addressed is considered a slave.
+ * clock signals to permit that transfer. The first byte in the data transfer always contains the 7-bit address and
+ * a read/write bit in the LSB position. This API takes care of toggling the read/write bit. After this, any device addressed
+ * is considered a slave. 
  *
  * This API allows the controller to be set up as a master or a slave using the \ref i2c_set_slave_mode function.
  *
@@ -154,7 +157,7 @@ static inline i2c_hw_t *i2c_get_hw(i2c_inst_t *i2c) {
  *  \ingroup hardware_i2c
  *
  * \param i2c Either \ref i2c0 or \ref i2c1
- * \param addr Address of device to write to
+ * \param addr 7-bit address of device to write to
  * \param src Pointer to data to send
  * \param len Length of data in bytes to send
  * \param nostop  If true, master retains control of the bus at the end of the transfer (no Stop is issued),
@@ -171,7 +174,7 @@ int i2c_write_blocking_until(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src,
  *  \ingroup hardware_i2c
  *
  * \param i2c Either \ref i2c0 or \ref i2c1
- * \param addr Address of device to read from
+ * \param addr 7-bit address of device to read from
  * \param dst Pointer to buffer to receive data
  * \param len Length of data in bytes to receive
  * \param nostop  If true, master retains control of the bus at the end of the transfer (no Stop is issued),
@@ -185,7 +188,7 @@ int i2c_read_blocking_until(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t
  *  \ingroup hardware_i2c
  *
  * \param i2c Either \ref i2c0 or \ref i2c1
- * \param addr Address of device to write to
+ * \param addr 7-bit address of device to write to
  * \param src Pointer to data to send
  * \param len Length of data in bytes to send
  * \param nostop  If true, master retains control of the bus at the end of the transfer (no Stop is issued),
@@ -207,7 +210,7 @@ int i2c_write_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, const uint8_t *
  *  \ingroup hardware_i2c
  *
  * \param i2c Either \ref i2c0 or \ref i2c1
- * \param addr Address of device to read from
+ * \param addr 7-bit address of device to read from
  * \param dst Pointer to buffer to receive data
  * \param len Length of data in bytes to receive
  * \param nostop  If true, master retains control of the bus at the end of the transfer (no Stop is issued),
@@ -226,7 +229,7 @@ int i2c_read_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, si
  *  \ingroup hardware_i2c
  *
  * \param i2c Either \ref i2c0 or \ref i2c1
- * \param addr Address of device to write to
+ * \param addr 7-bit address of device to write to
  * \param src Pointer to data to send
  * \param len Length of data in bytes to send
  * \param nostop  If true, master retains control of the bus at the end of the transfer (no Stop is issued),
@@ -239,12 +242,12 @@ int i2c_write_blocking(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t
  *  \ingroup hardware_i2c
  *
  * \param i2c Either \ref i2c0 or \ref i2c1
- * \param addr Address of device to read from
+ * \param addr 7-bit address of device to read from
  * \param dst Pointer to buffer to receive data
  * \param len Length of data in bytes to receive
  * \param nostop  If true, master retains control of the bus at the end of the transfer (no Stop is issued),
  *           and the next transfer will begin with a Restart rather than a Start.
- * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged, no device present.
+ * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged or no device present.
  */
 int i2c_read_blocking(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop);
 
@@ -309,6 +312,19 @@ static inline void i2c_read_raw_blocking(i2c_inst_t *i2c, uint8_t *dst, size_t l
     }
 }
 
+/*! \brief Return the DREQ to use for pacing transfers to/from a particular I2C instance
+ *  \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param is_tx true for sending data to the I2C instance, false for receiving data from the I2C instance
+ */
+static inline uint i2c_get_dreq(i2c_inst_t *i2c, bool is_tx) {
+    static_assert(DREQ_I2C0_RX == DREQ_I2C0_TX + 1, "");
+    static_assert(DREQ_I2C1_RX == DREQ_I2C1_TX + 1, "");
+    static_assert(DREQ_I2C1_TX == DREQ_I2C0_TX + 2, "");
+    return DREQ_I2C0_TX + i2c_hw_index(i2c) * 2 + !is_tx;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/rp2_common/hardware_irq/include/hardware/irq.h b/src/rp2_common/hardware_irq/include/hardware/irq.h
index d82ad544b..424a49712 100644
--- a/src/rp2_common/hardware_irq/include/hardware/irq.h
+++ b/src/rp2_common/hardware_irq/include/hardware/irq.h
@@ -8,12 +8,12 @@
 #define _HARDWARE_IRQ_H_
 
 // These two config items are also used by assembler, so keeping separate
-// PICO_CONFIG: PICO_MAX_SHARED_IRQ_HANDLERS, Maximum Number of shared IRQ handers, default=4, advanced=true, group=hardware_irq
+// PICO_CONFIG: PICO_MAX_SHARED_IRQ_HANDLERS, Maximum number of shared IRQ handlers, default=4, advanced=true, group=hardware_irq
 #ifndef PICO_MAX_SHARED_IRQ_HANDLERS
 #define PICO_MAX_SHARED_IRQ_HANDLERS 4u
 #endif
 
-// PICO_CONFIG: PICO_DISABLE_SHARED_IRQ_HANDLERS, Disable shared IRQ handers, type=bool, default=0, group=hardware_irq
+// PICO_CONFIG: PICO_DISABLE_SHARED_IRQ_HANDLERS, Disable shared IRQ handlers, type=bool, default=0, group=hardware_irq
 #ifndef PICO_DISABLE_SHARED_IRQ_HANDLERS
 #define PICO_DISABLE_SHARED_IRQ_HANDLERS 0
 #endif
@@ -37,13 +37,13 @@
  * On the RP2040, only the lower 26 IRQ signals are connected on the NVIC; IRQs 26 to 31 are tied to zero (never firing).
  *
  * There is one NVIC per core, and each core's NVIC has the same hardware interrupt lines routed to it, with the exception of the IO interrupts
- * where there is one IO interrupt per bank, per core. These are completely independent, so for example, processor 0 can be
+ * where there is one IO interrupt per bank, per core. These are completely independent, so, for example, processor 0 can be
  * interrupted by GPIO 0 in bank 0, and processor 1 by GPIO 1 in the same bank.
  *
  * \note That all IRQ APIs affect the executing core only (i.e. the core calling the function).
  *
  * \note You should not enable the same (shared) IRQ number on both cores, as this will lead to race conditions
- * or starvation of one of the cores. Additionally don't forget that disabling interrupts on one core does not disable interrupts
+ * or starvation of one of the cores. Additionally, don't forget that disabling interrupts on one core does not disable interrupts
  * on the other core.
  *
  * There are three different ways to set handlers for an IRQ:
@@ -53,7 +53,7 @@
  *    you will not be able to change it using the above APIs at runtime). Using this method can cause link conflicts at runtime, and offers no runtime performance benefit (i.e, it should not generally be used).
  *
  * \note If an IRQ is enabled and fires with no handler installed, a breakpoint will be hit and the IRQ number will
- * be in r0.
+ * be in register r0.
  *
  * \section interrupt_nums Interrupt Numbers
  *
@@ -119,7 +119,11 @@ extern "C" {
  */
 typedef void (*irq_handler_t)(void);
 
-/*! \brief Set specified interrupts priority
+static inline void check_irq_param(__unused uint num) {
+    invalid_params_if(IRQ, num >= NUM_IRQS);
+}
+
+/*! \brief Set specified interrupt's priority
  *  \ingroup hardware_irq
  *
  * \param num Interrupt number
@@ -133,6 +137,21 @@ typedef void (*irq_handler_t)(void);
  */
 void irq_set_priority(uint num, uint8_t hardware_priority);
 
+/*! \brief Get specified interrupt's priority
+ *  \ingroup hardware_irq
+ *
+ * Numerically-lower values indicate a higher priority. Hardware priorities
+ * range from 0 (highest priority) to 255 (lowest priority) though only the
+ * top 2 bits are significant on ARM Cortex-M0+. To make it easier to specify
+ * higher or lower priorities than the default, all IRQ priorities are
+ * initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup.
+ * PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80
+ *
+ * \param num Interrupt number
+ * \return the IRQ priority
+ */
+uint irq_get_priority(uint num);
+
 /*! \brief Enable or disable a specific interrupt on the executing core
  *  \ingroup hardware_irq
  *
@@ -245,7 +264,7 @@ static inline void irq_clear(uint int_num) {
     *((volatile uint32_t *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = (1u << ((uint32_t) (int_num & 0x1F)));
 }
 
-/*! \brief Force an interrupt to pending on the executing core
+/*! \brief Force an interrupt to be pending on the executing core
  *  \ingroup hardware_irq
  *
  * This should generally not be used for IRQs connected to hardware.
diff --git a/src/rp2_common/hardware_irq/irq.c b/src/rp2_common/hardware_irq/irq.c
index e47b68dda..211f6d02b 100644
--- a/src/rp2_common/hardware_irq/irq.c
+++ b/src/rp2_common/hardware_irq/irq.c
@@ -33,10 +33,6 @@ static void set_raw_irq_handler_and_unlock(uint num, irq_handler_t handler, uint
     spin_unlock(spin_lock_instance(PICO_SPINLOCK_ID_IRQ), save);
 }
 
-static inline void check_irq_param(__unused uint num) {
-    invalid_params_if(IRQ, num >= NUM_IRQS);
-}
-
 void irq_set_enabled(uint num, bool enabled) {
     check_irq_param(num);
     irq_set_mask_enabled(1u << num, enabled);
@@ -63,7 +59,7 @@ void irq_set_pending(uint num) {
     *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISPR_OFFSET)) = 1u << num;
 }
 
-#if PICO_MAX_SHARED_IRQ_HANDLERS
+#if !PICO_DISABLE_SHARED_IRQ_HANDLERS
 // limited by 8 bit relative links (and reality)
 static_assert(PICO_MAX_SHARED_IRQ_HANDLERS >= 1 && PICO_MAX_SHARED_IRQ_HANDLERS < 0x7f, "");
 
@@ -92,11 +88,13 @@ extern struct irq_handler_chain_slot {
 } irq_handler_chain_slots[PICO_MAX_SHARED_IRQ_HANDLERS];
 
 static int8_t irq_hander_chain_free_slot_head;
-#endif
 
 static inline bool is_shared_irq_raw_handler(irq_handler_t raw_handler) {
     return (uintptr_t)raw_handler - (uintptr_t)irq_handler_chain_slots < sizeof(irq_handler_chain_slots);
 }
+#else
+#define is_shared_irq_raw_handler(h) false
+#endif
 
 irq_handler_t irq_get_vtable_handler(uint num) {
     check_irq_param(num);
@@ -133,6 +131,7 @@ irq_handler_t irq_get_exclusive_handler(uint num) {
 }
 
 
+#if !PICO_DISABLE_SHARED_IRQ_HANDLERS
 static uint16_t make_branch(uint16_t *from, void *to) {
     uint32_t ui_from = (uint32_t)from;
     uint32_t ui_to = (uint32_t)to;
@@ -160,37 +159,36 @@ static inline void *resolve_branch(uint16_t *inst) {
 // GCC produces horrible code for subtraction of pointers here, and it was bugging me
 static inline int8_t slot_diff(struct irq_handler_chain_slot *to, struct irq_handler_chain_slot *from) {
     static_assert(sizeof(struct irq_handler_chain_slot) == 12, "");
-    int32_t result;
+    int32_t result = 0xaaaa;
     // return (to - from);
     // note this implementation has limited range, but is fine for plenty more than -128->127 result
     asm (".syntax unified\n"
          "subs %1, %2\n"
          "adcs %1, %1\n" // * 2 (and + 1 if negative for rounding)
-         "ldr  %0, =0xaaaa\n"
          "muls %0, %1\n"
          "lsrs %0, 20\n"
-        : "=l" (result), "+l" (to)
-        : "l" (from)
-        :
-        );
+         : "+l" (result), "+l" (to)
+         : "l" (from)
+         :
+         );
     return (int8_t)result;
 }
 
 static inline int8_t get_slot_index(struct irq_handler_chain_slot *slot) {
     return slot_diff(slot, irq_handler_chain_slots);
 }
+#endif
 
 void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority) {
     check_irq_param(num);
-#if PICO_DISABLE_SHARED_IRQ_HANDLERS
-
-#endif
-#if PICO_NO_RAM_VECTOR_TABLE || !PICO_MAX_SHARED_IRQ_HANDLERS
+#if PICO_NO_RAM_VECTOR_TABLE
     panic_unsupported()
+#elif PICO_DISABLE_SHARED_IRQ_HANDLERS
+    irq_set_exclusive_handler(num, handler);
 #else
     spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ);
     uint32_t save = spin_lock_blocking(lock);
-    hard_assert(irq_hander_chain_free_slot_head >= 0);
+    hard_assert(irq_hander_chain_free_slot_head >= 0); // we must have a slot
     struct irq_handler_chain_slot *slot = &irq_handler_chain_slots[irq_hander_chain_free_slot_head];
     int8_t slot_index = irq_hander_chain_free_slot_head;
     irq_hander_chain_free_slot_head = slot->link;
@@ -261,7 +259,7 @@ void irq_remove_handler(uint num, irq_handler_t handler) {
     uint32_t save = spin_lock_blocking(lock);
     irq_handler_t vtable_handler = get_vtable()[16 + num];
     if (vtable_handler != __unhandled_user_irq && vtable_handler != handler) {
-#if !PICO_DISABLE_SHARED_IRQ_HANDLERS && PICO_MAX_SHARED_IRQ_HANDLERS
+#if !PICO_DISABLE_SHARED_IRQ_HANDLERS
         if (is_shared_irq_raw_handler(vtable_handler)) {
             // This is a bit tricky, as an executing IRQ handler doesn't take a lock.
 
@@ -361,7 +359,15 @@ void irq_set_priority(uint num, uint8_t hardware_priority) {
     *p = (*p & ~(0xffu << (8 * (num & 3u)))) | (((uint32_t) hardware_priority) << (8 * (num & 3u)));
 }
 
-#if !PICO_DISABLE_SHARED_IRQ_HANDLERS && PICO_MAX_SHARED_IRQ_HANDLERS
+uint irq_get_priority(uint num) {
+    check_irq_param(num);
+
+    // note that only 32 bit reads are supported
+    io_rw_32 *p = (io_rw_32 *)((PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET) + (num & ~3u));
+    return (uint8_t)(*p >> (8 * (num & 3u)));
+}
+
+#if !PICO_DISABLE_SHARED_IRQ_HANDLERS
 // used by irq_handler_chain.S to remove the last link in a handler chain after it executes
 // note this must be called only with the last slot in a chain (and during the exception)
 void irq_add_tail_to_free_list(struct irq_handler_chain_slot *slot) {
@@ -397,8 +403,11 @@ void irq_add_tail_to_free_list(struct irq_handler_chain_slot *slot) {
 
 void irq_init_priorities() {
 #if PICO_DEFAULT_IRQ_PRIORITY != 0
-    for (uint irq = 0; irq < NUM_IRQS; irq++) {
-        irq_set_priority(irq, PICO_DEFAULT_IRQ_PRIORITY);
+    static_assert(!(NUM_IRQS & 3), "");
+    uint32_t prio4 = (PICO_DEFAULT_IRQ_PRIORITY & 0xff) * 0x1010101u;
+    io_rw_32 * p = (io_rw_32 *)(PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET);
+    for (uint i = 0; i < NUM_IRQS / 4; i++) {
+        *p++ = prio4;
     }
 #endif
 }
diff --git a/src/rp2_common/hardware_irq/irq_handler_chain.S b/src/rp2_common/hardware_irq/irq_handler_chain.S
index 6a8a4b688..7d7be7d36 100644
--- a/src/rp2_common/hardware_irq/irq_handler_chain.S
+++ b/src/rp2_common/hardware_irq/irq_handler_chain.S
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include "hardware/platform_defs.h"
+#include "pico.h"
 #include "hardware/irq.h"
 
 #if !PICO_DISABLE_SHARED_IRQ_HANDLERS
diff --git a/src/rp2_common/hardware_pio/include/hardware/pio.h b/src/rp2_common/hardware_pio/include/hardware/pio.h
index 07d06694b..d2377ac84 100644
--- a/src/rp2_common/hardware_pio/include/hardware/pio.h
+++ b/src/rp2_common/hardware_pio/include/hardware/pio.h
@@ -25,7 +25,7 @@
  * Programmable I/O (PIO) API
  *
  * A programmable input/output block (PIO) is a versatile hardware interface which
- * can support a number of different IO standards. There are two PIO blocks in the RP2040
+ * can support a number of different IO standards. There are two PIO blocks in the RP2040.
  *
  * Each PIO is programmable in the same sense as a processor: the four state machines independently
  * execute short, sequential programs, to manipulate GPIOs and transfer data. Unlike a general
@@ -436,14 +436,19 @@ static inline void pio_gpio_init(PIO pio, uint pin) {
     gpio_set_function(pin, pio == pio0 ? GPIO_FUNC_PIO0 : GPIO_FUNC_PIO1);
 }
 
-/*! \brief Return the DREQ to use for pacing transfers to a particular state machine
+/*! \brief Return the DREQ to use for pacing transfers to/from a particular state machine FIFO
  *  \ingroup hardware_pio
  *
  * \param pio The PIO instance; either \ref pio0 or \ref pio1
  * \param sm State machine index (0..3)
- * \param is_tx true for sending data to the state machine, false for received data from the state machine
+ * \param is_tx true for sending data to the state machine, false for receiving data from the state machine
  */
 static inline uint pio_get_dreq(PIO pio, uint sm, bool is_tx) {
+    static_assert(DREQ_PIO0_TX1 == DREQ_PIO0_TX0 + 1, "");
+    static_assert(DREQ_PIO0_TX2 == DREQ_PIO0_TX0 + 2, "");
+    static_assert(DREQ_PIO0_TX3 == DREQ_PIO0_TX0 + 3, "");
+    static_assert(DREQ_PIO0_RX0 == DREQ_PIO0_TX0 + NUM_PIO_STATE_MACHINES, "");
+    static_assert(DREQ_PIO1_RX0 == DREQ_PIO1_TX0 + NUM_PIO_STATE_MACHINES, "");
     check_pio_param(pio);
     check_sm_param(sm);
     return sm + (is_tx ? 0 : NUM_PIO_STATE_MACHINES) + (pio == pio0 ? DREQ_PIO0_TX0 : DREQ_PIO1_TX0);
diff --git a/src/rp2_common/hardware_pio/include/hardware/pio_instructions.h b/src/rp2_common/hardware_pio/include/hardware/pio_instructions.h
index 07df65bea..366213580 100644
--- a/src/rp2_common/hardware_pio/include/hardware/pio_instructions.h
+++ b/src/rp2_common/hardware_pio/include/hardware/pio_instructions.h
@@ -9,7 +9,18 @@
 
 #include "pico.h"
 
-// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS, Enable/disable assertions in the PIO instructions, type=bool, default=0, group=hardware_pio
+/** \brief PIO instruction encoding 
+ *  \defgroup pio_instructions pio_instructions
+ *  \ingroup hardware_pio
+ * 
+ * Functions for generating PIO instruction encodings programmatically. In debug builds
+ *`PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS` can be set to 1 to enable validation of encoding function
+ * parameters.
+ *
+ * For fuller descriptions of the instructions in question see the "RP2040 Datasheet"
+ */
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS, Enable/disable assertions in the PIO instructions, type=bool, default=0, group=pio_instructions
 #ifndef PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS
 #define PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS 0
 #endif
@@ -44,6 +55,12 @@ enum pio_instr_bits {
 #define _PIO_INVALID_MOV_DEST 0u
 #endif
 
+/*! \brief Enumeration of values to pass for source/destination args for instruction encoding functions
+ *  \ingroup pio_instructions
+ *
+ * \note Not all values are suitable for all functions. Validity is only checked in debug mode when
+ * `PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS` is 1
+ */
 enum pio_src_dest {
     pio_pins = 0u,
     pio_x = 1u,
@@ -58,11 +75,11 @@ enum pio_src_dest {
     pio_exec_out = 7u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST,
 };
 
-inline static uint _pio_major_instr_bits(uint instr) {
+static inline uint _pio_major_instr_bits(uint instr) {
     return instr & 0xe000u;
 }
 
-inline static uint _pio_encode_instr_and_args(enum pio_instr_bits instr_bits, uint arg1, uint arg2) {
+static inline uint _pio_encode_instr_and_args(enum pio_instr_bits instr_bits, uint arg1, uint arg2) {
     valid_params_if(PIO_INSTRUCTIONS, arg1 <= 0x7);
 #if PARAM_ASSERTIONS_ENABLED(PIO_INSTRUCTIONS)
     uint32_t major = _pio_major_instr_bits(instr_bits);
@@ -75,100 +92,388 @@ inline static uint _pio_encode_instr_and_args(enum pio_instr_bits instr_bits, ui
     return instr_bits | (arg1 << 5u) | (arg2 & 0x1fu);
 }
 
-inline static uint _pio_encode_instr_and_src_dest(enum pio_instr_bits instr_bits, enum pio_src_dest dest, uint value) {
+static inline uint _pio_encode_instr_and_src_dest(enum pio_instr_bits instr_bits, enum pio_src_dest dest, uint value) {
     return _pio_encode_instr_and_args(instr_bits, dest & 7u, value);
 }
 
-inline static uint pio_encode_delay(uint cycles) {
+/*! \brief Encode just the delay slot bits of an instruction
+ *  \ingroup pio_instructions
+ *
+ * \note This function does not return a valid instruction encoding; instead it returns an encoding of the delay
+ * slot suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when
+ * combining the results of this function with the results of \ref pio_encode_sideset and \ref pio_encode_sideset_opt
+ * as they share the same bits within the instruction encoding.
+ *
+ * \param cycles the number of cycles 0-31 (or less if side set is being used)
+ * \return the delay slot bits to be ORed with an instruction encoding
+ */
+static inline uint pio_encode_delay(uint cycles) {
     // note that the maximum cycles will be smaller if sideset_bit_count > 0
     valid_params_if(PIO_INSTRUCTIONS, cycles <= 0x1f);
     return cycles << 8u;
 }
 
-inline static uint pio_encode_sideset(uint sideset_bit_count, uint value) {
+/*! \brief Encode just the side set bits of an instruction (in non optional side set mode)
+ *  \ingroup pio_instructions
+ *
+ * \note This function does not return a valid instruction encoding; instead it returns an encoding of the side set bits
+ * suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when
+ * combining the results of this function with the results of \ref pio_encode_delay as they share the same bits
+ * within the instruction encoding.
+ *
+ * \param sideset_bit_count number of side set bits as would be specified via `.sideset` in pioasm
+ * \param value the value to sideset on the pins
+ * \return the side set bits to be ORed with an instruction encoding
+ */
+static inline uint pio_encode_sideset(uint sideset_bit_count, uint value) {
     valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 1 && sideset_bit_count <= 5);
     valid_params_if(PIO_INSTRUCTIONS, value <= ((1u << sideset_bit_count) - 1));
     return value << (13u - sideset_bit_count);
 }
 
-inline static uint pio_encode_sideset_opt(uint sideset_bit_count, uint value) {
+/*! \brief Encode just the side set bits of an instruction (in optional -`opt` side set mode)
+ *  \ingroup pio_instructions
+ *
+ * \note This function does not return a valid instruction encoding; instead it returns an encoding of the side set bits
+ * suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when
+ * combining the results of this function with the results of \ref pio_encode_delay as they share the same bits
+ * within the instruction encoding.
+ *
+ * \param sideset_bit_count number of side set bits as would be specified via `.sideset <n> opt` in pioasm
+ * \param value the value to sideset on the pins
+ * \return the side set bits to be ORed with an instruction encoding
+ */
+static inline uint pio_encode_sideset_opt(uint sideset_bit_count, uint value) {
     valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 1 && sideset_bit_count <= 4);
     valid_params_if(PIO_INSTRUCTIONS, value <= ((1u << sideset_bit_count) - 1));
     return 0x1000u | value << (12u - sideset_bit_count);
 }
 
-inline static uint pio_encode_jmp(uint addr) {
+/*! \brief Encode an unconditional JMP instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp(uint addr) {
     return _pio_encode_instr_and_args(pio_instr_bits_jmp, 0, addr);
 }
 
-inline static uint _pio_encode_irq(bool relative, uint irq) {
+/*! \brief Encode a conditional JMP if scratch X zero instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP !X <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_not_x(uint addr) {
+    return _pio_encode_instr_and_args(pio_instr_bits_jmp, 1, addr);
+}
+
+/*! \brief Encode a conditional JMP if scratch X non-zero (and post-decrement X) instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP X-- <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_x_dec(uint addr) {
+    return _pio_encode_instr_and_args(pio_instr_bits_jmp, 2, addr);
+}
+
+/*! \brief Encode a conditional JMP if scratch Y zero instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP !Y <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_not_y(uint addr) {
+    return _pio_encode_instr_and_args(pio_instr_bits_jmp, 3, addr);
+}
+
+/*! \brief Encode a conditional JMP if scratch Y non-zero (and post-decrement Y) instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP Y-- <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_y_dec(uint addr) {
+    return _pio_encode_instr_and_args(pio_instr_bits_jmp, 4, addr);
+}
+
+/*! \brief Encode a conditional JMP if scratch X not equal scratch Y instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP X!=Y <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_x_ne_y(uint addr) {
+    return _pio_encode_instr_and_args(pio_instr_bits_jmp, 5, addr);
+}
+
+/*! \brief Encode a conditional JMP if input pin high instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP PIN <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_pin(uint addr) {
+    return _pio_encode_instr_and_args(pio_instr_bits_jmp, 6, addr);
+}
+
+/*! \brief Encode a conditional JMP if output shift register not empty instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP !OSRE <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_not_osre(uint addr) {
+    return _pio_encode_instr_and_args(pio_instr_bits_jmp, 7, addr);
+}
+
+static inline uint _pio_encode_irq(bool relative, uint irq) {
     valid_params_if(PIO_INSTRUCTIONS, irq <= 7);
     return (relative ? 0x10u : 0x0u) | irq;
 }
 
-inline static uint pio_encode_wait_gpio(bool polarity, uint pin) {
-    return _pio_encode_instr_and_args(pio_instr_bits_wait, 0u | (polarity ? 4u : 0u), pin);
+/*! \brief Encode a WAIT for GPIO pin instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `WAIT <polarity> GPIO <gpio>`
+ *
+ * \param polarity true for `WAIT 1`, false for `WAIT 0`
+ * \param gpio The real GPIO number 0-31
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_wait_gpio(bool polarity, uint gpio) {
+    return _pio_encode_instr_and_args(pio_instr_bits_wait, 0u | (polarity ? 4u : 0u), gpio);
 }
 
-inline static uint pio_encode_wait_pin(bool polarity, uint pin) {
+/*! \brief Encode a WAIT for pin instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `WAIT <polarity> PIN <pin>`
+ *
+ * \param polarity true for `WAIT 1`, false for `WAIT 0`
+ * \param pin The pin number 0-31 relative to the executing SM's input pin mapping
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_wait_pin(bool polarity, uint pin) {
     return _pio_encode_instr_and_args(pio_instr_bits_wait, 1u | (polarity ? 4u : 0u), pin);
 }
 
-inline static uint pio_encode_wait_irq(bool polarity, bool relative, uint irq) {
+/*! \brief Encode a WAIT for IRQ instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `WAIT <polarity> IRQ <irq> <relative>`
+ *
+ * \param polarity true for `WAIT 1`, false for `WAIT 0`
+ * \param relative true for a `WAIT IRQ <irq> REL`, false for regular `WAIT IRQ <irq>`
+ * \param irq the irq number 0-7
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_wait_irq(bool polarity, bool relative, uint irq) {
     valid_params_if(PIO_INSTRUCTIONS, irq <= 7);
     return _pio_encode_instr_and_args(pio_instr_bits_wait, 2u | (polarity ? 4u : 0u), _pio_encode_irq(relative, irq));
 }
 
-inline static uint pio_encode_in(enum pio_src_dest src, uint value) {
+/*! \brief Encode an IN instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `IN <src>, <count>`
+ *
+ * \param src The source to take data from
+ * \param count The number of bits 1-32
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_in(enum pio_src_dest src, uint count) {
     valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_IN_SRC));
-    return _pio_encode_instr_and_src_dest(pio_instr_bits_in, src, value);
+    return _pio_encode_instr_and_src_dest(pio_instr_bits_in, src, count);
 }
 
-inline static uint pio_encode_out(enum pio_src_dest dest, uint value) {
+/*! \brief Encode an OUT instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `OUT <src>, <count>`
+ *
+ * \param dest The destination to write data to
+ * \param count The number of bits 1-32
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_out(enum pio_src_dest dest, uint count) {
     valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_OUT_DEST));
-    return _pio_encode_instr_and_src_dest(pio_instr_bits_out, dest, value);
+    return _pio_encode_instr_and_src_dest(pio_instr_bits_out, dest, count);
 }
 
-inline static uint pio_encode_push(bool if_full, bool block) {
+/*! \brief Encode a PUSH instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `PUSH <if_full>, <block>`
+ *
+ * \param if_full true for `PUSH IF_FULL ...`, false for `PUSH ...`
+ * \param block true for `PUSH ... BLOCK`, false for `PUSH ...`
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_push(bool if_full, bool block) {
     return _pio_encode_instr_and_args(pio_instr_bits_push, (if_full ? 2u : 0u) | (block ? 1u : 0u), 0);
 }
 
-inline static uint pio_encode_pull(bool if_empty, bool block) {
+/*! \brief Encode a PULL instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `PULL <if_empty>, <block>`
+ *
+ * \param if_empty true for `PULL IF_EMPTY ...`, false for `PULL ...`
+ * \param block true for `PULL ... BLOCK`, false for `PULL ...`
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_pull(bool if_empty, bool block) {
     return _pio_encode_instr_and_args(pio_instr_bits_pull, (if_empty ? 2u : 0u) | (block ? 1u : 0u), 0);
 }
 
-inline static uint pio_encode_mov(enum pio_src_dest dest, enum pio_src_dest src) {
+/*! \brief Encode a MOV instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `MOV <dest>, <src>`
+ *
+ * \param dest The destination to write data to
+ * \param src The source to take data from
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_mov(enum pio_src_dest dest, enum pio_src_dest src) {
     valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST));
     valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC));
     return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, src & 7u);
 }
 
-inline static uint pio_encode_mov_not(enum pio_src_dest dest, enum pio_src_dest src) {
+/*! \brief Encode a MOV instruction with bit invert
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `MOV <dest>, ~<src>`
+ *
+ * \param dest The destination to write inverted data to
+ * \param src The source to take data from
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_mov_not(enum pio_src_dest dest, enum pio_src_dest src) {
     valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST));
     valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC));
     return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, (1u << 3u) | (src & 7u));
 }
 
-inline static uint pio_encode_mov_reverse(enum pio_src_dest dest, enum pio_src_dest src) {
+/*! \brief Encode a MOV instruction with bit reverse
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `MOV <dest>, ::<src>`
+ *
+ * \param dest The destination to write bit reversed data to
+ * \param src The source to take data from
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_mov_reverse(enum pio_src_dest dest, enum pio_src_dest src) {
     valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST));
     valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC));
     return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, (2u << 3u) | (src & 7u));
 }
 
-inline static uint pio_encode_irq_set(bool relative, uint irq) {
+/*! \brief Encode a IRQ SET instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `IRQ SET <irq> <relative>`
+ *
+ * \param relative true for a `IRQ SET <irq> REL`, false for regular `IRQ SET <irq>`
+ * \param irq the irq number 0-7
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_irq_set(bool relative, uint irq) {
     return _pio_encode_instr_and_args(pio_instr_bits_irq, 0, _pio_encode_irq(relative, irq));
 }
 
-inline static uint pio_encode_irq_clear(bool relative, uint irq) {
+/*! \brief Encode a IRQ WAIT instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `IRQ WAIT <irq> <relative>`
+ *
+ * \param relative true for a `IRQ WAIT <irq> REL`, false for regular `IRQ WAIT <irq>`
+ * \param irq the irq number 0-7
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_irq_wait(bool relative, uint irq) {
+    return _pio_encode_instr_and_args(pio_instr_bits_irq, 1, _pio_encode_irq(relative, irq));
+}
+
+/*! \brief Encode a IRQ CLEAR instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `IRQ CLEAR <irq> <relative>`
+ *
+ * \param relative true for a `IRQ CLEAR <irq> REL`, false for regular `IRQ CLEAR <irq>`
+ * \param irq the irq number 0-7
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_irq_clear(bool relative, uint irq) {
     return _pio_encode_instr_and_args(pio_instr_bits_irq, 2, _pio_encode_irq(relative, irq));
 }
 
-inline static uint pio_encode_set(enum pio_src_dest dest, uint value) {
+/*! \brief Encode a SET instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `SET <dest>, <value>`
+ *
+ * \param dest The destination to apply the value to
+ * \param value The value 0-31
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_set(enum pio_src_dest dest, uint value) {
     valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_SET_DEST));
     return _pio_encode_instr_and_src_dest(pio_instr_bits_set, dest, value);
 }
 
-inline static uint pio_encode_nop(void) {
+/*! \brief Encode a NOP instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `NOP` which is itself encoded as `MOV y, y`
+ *
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_nop(void) {
     return pio_encode_mov(pio_y, pio_y);
 }
 
diff --git a/src/rp2_common/hardware_pwm/include/hardware/pwm.h b/src/rp2_common/hardware_pwm/include/hardware/pwm.h
index ed696e765..634375e76 100644
--- a/src/rp2_common/hardware_pwm/include/hardware/pwm.h
+++ b/src/rp2_common/hardware_pwm/include/hardware/pwm.h
@@ -9,6 +9,7 @@
 
 #include "pico.h"
 #include "hardware/structs/pwm.h"
+#include "hardware/regs/dreq.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -26,7 +27,7 @@ extern "C" {
  *
  * The RP2040 PWM block has 8 identical slices. Each slice can drive two PWM output signals, or
  * measure the frequency or duty cycle of an input signal. This gives a total of up to 16 controllable
- * PWM outputs. All 30 GPIOs can be driven by the PWM block
+ * PWM outputs. All 30 GPIOs can be driven by the PWM block.
  *
  * The PWM hardware functions by continuously comparing the input value to a free-running counter. This produces a
  * toggling output where the amount of time spent at the high output level is proportional to the input value. The fraction of
@@ -116,21 +117,21 @@ static inline void pwm_config_set_phase_correct(pwm_config *c, bool phase_correc
  * before passing them on to the PWM counter.
  */
 static inline void pwm_config_set_clkdiv(pwm_config *c, float div) {
-    c->div = (uint32_t)(div * (float)(1u << PWM_CH1_DIV_INT_LSB));
+    c->div = (uint32_t)(div * (float)(1u << PWM_CH0_DIV_INT_LSB));
 }
 
 /** \brief Set PWM clock divider in a PWM configuration
  *  \ingroup hardware_pwm
  *
  * \param c PWM configuration struct to modify
- * \param div integer value to reduce counting rate by. Must be greater than or equal to 1.
+ * \param div Integer value to reduce counting rate by. Must be greater than or equal to 1.
  *
  * If the divide mode is free-running, the PWM counter runs at clk_sys / div.
  * Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge)
  * before passing them on to the PWM counter.
  */
 static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint div) {
-    c->div = div << PWM_CH1_DIV_INT_LSB;
+    c->div = div << PWM_CH0_DIV_INT_LSB;
 }
 
 /** \brief Set PWM counting mode in a PWM configuration
@@ -201,7 +202,7 @@ static inline void pwm_init(uint slice_num, pwm_config *c, bool start) {
 /** \brief Get a set of default values for PWM configuration
  *  \ingroup hardware_pwm
  *
- * PWM config is free running at system clock speed, no phase correction, wrapping at 0xffff,
+ * PWM config is free-running at system clock speed, no phase correction, wrapping at 0xffff,
  * with standard polarities for channels A and B.
  *
  * \return Set of default values.
@@ -239,7 +240,7 @@ static inline void pwm_set_wrap(uint slice_num, uint16_t wrap) {
 /** \brief Set the current PWM counter compare value for one channel
  *  \ingroup hardware_pwm
  *
- * Set the value of the PWM counter compare value, for either channel A or channel B
+ * Set the value of the PWM counter compare value, for either channel A or channel B.
  *
  * The counter compare register is double-buffered in hardware. This means
  * that, when the PWM is running, a write to the counter compare values does
@@ -263,7 +264,7 @@ static inline void pwm_set_chan_level(uint slice_num, uint chan, uint16_t level)
 /** \brief Set PWM counter compare values
  *  \ingroup hardware_pwm
  *
- * Set the value of the PWM counter compare values, A and B
+ * Set the value of the PWM counter compare values, A and B.
  *
  * The counter compare register is double-buffered in hardware. This means
  * that, when the PWM is running, a write to the counter compare values does
@@ -284,7 +285,7 @@ static inline void pwm_set_both_levels(uint slice_num, uint16_t level_a, uint16_
  *  \ingroup hardware_pwm
  *
  * Look up the correct slice (0 to 7) and channel (A or B) for a given GPIO, and update the corresponding
- * counter-compare field.
+ * counter compare field.
  *
  * This PWM slice should already have been configured and set running. Also be careful of multiple GPIOs
  * mapping to the same slice and channel (if GPIOs have a difference of 16).
@@ -309,7 +310,7 @@ static inline void pwm_set_gpio_level(uint gpio, uint16_t level) {
  * Get current value of PWM counter
  *
  * \param slice_num PWM slice number
- * \return Current value of PWM counter
+ * \return Current value of the PWM counter
  */
 static inline uint16_t pwm_get_counter(uint slice_num) {
     check_slice_num_param(slice_num);
@@ -367,7 +368,7 @@ static inline void pwm_retard_count(uint slice_num) {
 /** \brief Set PWM clock divider using an 8:4 fractional value
  *  \ingroup hardware_pwm
  *
- * Set the clock divider. Counter increment will be on sysclock divided by this value, taking in to account the gating.
+ * Set the clock divider. Counter increment will be on sysclock divided by this value, taking into account the gating.
  *
  * \param slice_num PWM slice number
  * \param integer  8 bit integer part of the clock divider
@@ -382,7 +383,7 @@ static inline void pwm_set_clkdiv_int_frac(uint slice_num, uint8_t integer, uint
 /** \brief Set PWM clock divider
  *  \ingroup hardware_pwm
  *
- * Set the clock divider. Counter increment will be on sysclock divided by this value, taking in to account the gating.
+ * Set the clock divider. Counter increment will be on sysclock divided by this value, taking into account the gating.
  *
  * \param slice_num PWM slice number
  * \param divider Floating point clock divider,  1.f <= value < 256.f
@@ -441,8 +442,28 @@ static inline void pwm_set_phase_correct(uint slice_num, bool phase_correct) {
 /** \brief Enable/Disable PWM
  *  \ingroup hardware_pwm
  *
+ * When a PWM is disabled, it halts its counter, and the output pins are left
+ * high or low depending on exactly when the counter is halted. When
+ * re-enabled the PWM resumes immediately from where it left off.
+ *
+ * If the PWM's output pins need to be low when halted:
+ *
+ * - The counter compare can be set to zero whilst the PWM is enabled, and
+ *   then the PWM disabled once both pins are seen to be low
+ *
+ * - The GPIO output overrides can be used to force the actual pins low
+ *
+ * - The PWM can be run for one cycle (i.e. enabled then immediately disabled)
+ *   with a TOP of 0, count of 0 and counter compare of 0, to force the pins
+ *   low when the PWM has already been halted. The same method can be used
+ *   with a counter compare value of 1 to force a pin high.
+ *
+ * Note that, when disabled, the PWM can still be advanced one count at a time
+ * by pulsing the PH_ADV bit in its CSR. The output pins transition as though
+ * the PWM were enabled.
+ *
  * \param slice_num PWM slice number
- * \param enabled true to enable the specified PWM, false to disable
+ * \param enabled true to enable the specified PWM, false to disable.
  */
 static inline void pwm_set_enabled(uint slice_num, bool enabled) {
     check_slice_num_param(slice_num);
@@ -461,7 +482,7 @@ static inline void pwm_set_mask_enabled(uint32_t mask) {
 /*! \brief  Enable PWM instance interrupt
  *  \ingroup hardware_pwm
  *
- * Used to enable a single PWM instance interrupt
+ * Used to enable a single PWM instance interrupt.
  *
  * \param slice_num PWM block to enable/disable
  * \param enabled true to enable, false to disable
@@ -492,7 +513,7 @@ static inline void pwm_set_irq_mask_enabled(uint32_t slice_mask, bool enabled) {
     }
 }
 
-/*! \brief  Clear single PWM channel interrupt
+/*! \brief  Clear a single PWM channel interrupt
  *  \ingroup hardware_pwm
  *
  * \param slice_num PWM slice number
@@ -519,6 +540,18 @@ static inline void pwm_force_irq(uint slice_num) {
     pwm_hw->intf = 1u << slice_num;
 }
 
+/*! \brief Return the DREQ to use for pacing transfers to a particular PWM slice
+ *  \ingroup hardware_pwm
+ *
+ * \param slice_num PWM slice number
+ */
+static inline uint pwm_get_dreq(uint slice_num) {
+    static_assert(DREQ_PWM_WRAP1 == DREQ_PWM_WRAP0 + 1, "");
+    static_assert(DREQ_PWM_WRAP7 == DREQ_PWM_WRAP0 + 7, "");
+    check_slice_num_param(slice_num);
+    return DREQ_PWM_WRAP0 + slice_num;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/rp2_common/hardware_spi/include/hardware/spi.h b/src/rp2_common/hardware_spi/include/hardware/spi.h
index b766f74f1..e8dc95251 100644
--- a/src/rp2_common/hardware_spi/include/hardware/spi.h
+++ b/src/rp2_common/hardware_spi/include/hardware/spi.h
@@ -10,6 +10,7 @@
 #include "pico.h"
 #include "pico/time.h"
 #include "hardware/structs/spi.h"
+#include "hardware/regs/dreq.h"
 
 // PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_SPI, Enable/disable assertions in the SPI module, type=bool, default=0, group=hardware_spi
 #ifndef PARAM_ASSERTIONS_ENABLED_SPI
@@ -337,6 +338,19 @@ int spi_write16_blocking(spi_inst_t *spi, const uint16_t *src, size_t len);
  */
 int spi_read16_blocking(spi_inst_t *spi, uint16_t repeated_tx_data, uint16_t *dst, size_t len);
 
+/*! \brief Return the DREQ to use for pacing transfers to/from a particular SPI instance
+ *  \ingroup hardware_spi
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param is_tx true for sending data to the SPI instance, false for receiving data from the SPI instance
+ */
+static inline uint spi_get_dreq(spi_inst_t *spi, bool is_tx) {
+    static_assert(DREQ_SPI0_RX == DREQ_SPI0_TX + 1, "");
+    static_assert(DREQ_SPI1_RX == DREQ_SPI1_TX + 1, "");
+    static_assert(DREQ_SPI1_TX == DREQ_SPI0_TX + 2, "");
+    return DREQ_SPI0_TX + spi_get_index(spi) * 2 + !is_tx;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/rp2_common/hardware_uart/include/hardware/uart.h b/src/rp2_common/hardware_uart/include/hardware/uart.h
index 02fdd1fb9..bce0d2f0f 100644
--- a/src/rp2_common/hardware_uart/include/hardware/uart.h
+++ b/src/rp2_common/hardware_uart/include/hardware/uart.h
@@ -9,6 +9,7 @@
 
 #include "pico.h"
 #include "hardware/structs/uart.h"
+#include "hardware/regs/dreq.h"
 
 // PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_UART, Enable/disable assertions in the UART module, type=bool, default=0, group=hardware_uart
 #ifndef PARAM_ASSERTIONS_ENABLED_UART
@@ -205,12 +206,17 @@ static inline void uart_set_format(uart_inst_t *uart, uint data_bits, uint stop_
  * this function.
  *
  * \param uart UART instance. \ref uart0 or \ref uart1
- * \param rx_has_data If true an interrupt will be fired when the RX FIFO contain data.
+ * \param rx_has_data If true an interrupt will be fired when the RX FIFO contains data.
  * \param tx_needs_data If true an interrupt will be fired when the TX FIFO needs data.
  */
 static inline void uart_set_irq_enables(uart_inst_t *uart, bool rx_has_data, bool tx_needs_data) {
+    // Both UARTRXINTR (RX) and UARTRTINTR (RX timeout) interrupts are
+    // required for rx_has_data. RX asserts when >=4 characters are in the RX
+    // FIFO (for RXIFLSEL=0). RT asserts when there are >=1 characters and no
+    // more have been received for 32 bit periods.
     uart_get_hw(uart)->imsc = (bool_to_bit(tx_needs_data) << UART_UARTIMSC_TXIM_LSB) |
-                              (bool_to_bit(rx_has_data) << UART_UARTIMSC_RXIM_LSB);
+                              (bool_to_bit(rx_has_data) << UART_UARTIMSC_RXIM_LSB) |
+                              (bool_to_bit(rx_has_data) << UART_UARTIMSC_RTIM_LSB);
     if (rx_has_data) {
         // Set minimum threshold
         hw_write_masked(&uart_get_hw(uart)->ifls, 0 << UART_UARTIFLS_RXIFLSEL_LSB,
@@ -321,7 +327,7 @@ static inline void uart_read_blocking(uart_inst_t *uart, uint8_t *dst, size_t le
 /*! \brief  Write single character to UART for transmission.
  *  \ingroup hardware_uart
  *
- * This function will block until all the character has been sent
+ * This function will block until the entire character has been sent
  *
  * \param uart UART instance. \ref uart0 or \ref uart1
  * \param c The character  to send
@@ -407,7 +413,7 @@ static inline void uart_set_break(uart_inst_t *uart, bool en) {
  */
 void uart_set_translate_crlf(uart_inst_t *uart, bool translate);
 
-/*! \brief Wait for the default UART'S TX fifo to be drained
+/*! \brief Wait for the default UART's TX FIFO to be drained
  *  \ingroup hardware_uart
  */
 static inline void uart_default_tx_wait_blocking(void) {
@@ -427,6 +433,19 @@ static inline void uart_default_tx_wait_blocking(void) {
  */
 bool uart_is_readable_within_us(uart_inst_t *uart, uint32_t us);
 
+/*! \brief Return the DREQ to use for pacing transfers to/from a particular UART instance
+ *  \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param is_tx true for sending data to the UART instance, false for receiving data from the UART instance
+ */
+static inline uint uart_get_dreq(uart_inst_t *uart, bool is_tx) {
+    static_assert(DREQ_UART0_RX == DREQ_UART0_TX + 1, "");
+    static_assert(DREQ_UART1_RX == DREQ_UART1_TX + 1, "");
+    static_assert(DREQ_UART1_TX == DREQ_UART0_TX + 2, "");
+    return DREQ_UART0_TX + uart_get_index(uart) * 2 + !is_tx;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/rp2_common/hardware_watchdog/include/hardware/watchdog.h b/src/rp2_common/hardware_watchdog/include/hardware/watchdog.h
index cbc43a64f..747838be8 100644
--- a/src/rp2_common/hardware_watchdog/include/hardware/watchdog.h
+++ b/src/rp2_common/hardware_watchdog/include/hardware/watchdog.h
@@ -8,6 +8,7 @@
 #define _HARDWARE_WATCHDOG_H
 
 #include "pico.h"
+#include "hardware/structs/watchdog.h"
 
 /** \file hardware/watchdog.h
  *  \defgroup hardware_watchdog hardware_watchdog
@@ -66,6 +67,11 @@ void watchdog_update(void);
  *
  * By default the SDK assumes a 12MHz XOSC and sets the \ref watchdog_start_tick appropriately.
  *
+ * This method sets a marker in the watchdog scratch register 4 that is checked by \ref watchdog_enable_caused_reboot.
+ * If the device is subsequently reset via a call to watchdog_reboot (including for example by dragging a UF2
+ * onto the RPI-RP2), then this value will be cleared, and so \ref watchdog_enable_caused_reboot will
+ * return false.
+ *
  * \param delay_ms Number of milliseconds before watchdog will reboot without watchdog_update being called. Maximum of 0x7fffff, which is approximately 8.3 seconds
  * \param pause_on_debug If the watchdog should be paused when the debugger is stepping through code
  */
@@ -75,11 +81,30 @@ void watchdog_enable(uint32_t delay_ms, bool pause_on_debug);
  * \brief Did the watchdog cause the last reboot?
  * \ingroup hardware_watchdog
  *
- * @return true if the watchdog timer or a watchdog force caused the last reboot
- * @return false there has been no watchdog reboot since run has been
+ * @return true If the watchdog timer or a watchdog force caused the last reboot
+ * @return false If there has been no watchdog reboot since the last power on reset. A power on reset is typically caused by a power cycle or the run pin (reset button) being toggled.
  */
 bool watchdog_caused_reboot(void);
 
+/**
+ * \brief Did watchdog_enable cause the last reboot?
+ * \ingroup hardware_watchdog
+ *
+ * Perform additional checking along with \ref watchdog_caused_reboot to determine if a watchdog timeout initiated by
+ * \ref watchdog_enable caused the last reboot.
+ *
+ * This method checks for a special value in watchdog scratch register 4 placed there by \ref watchdog_enable.
+ * This would not be present if a watchdog reset is initiated by \ref watchdog_reboot or by the RP2040 bootrom
+ * (e.g. dragging a UF2 onto the RPI-RP2 drive).
+ *
+ * @return true If the watchdog timer or a watchdog force caused (see \reg watchdog_caused_reboot) the last reboot
+ *              and the watchdog reboot happened after \ref watchdog_enable was called
+ * @return false If there has been no watchdog reboot since the last power on reset, or the watchdog reboot was not caused
+ *               by a watchdog timeout after \ref watchdog_enable was called.
+ *               A power on reset is typically caused by a power cycle or the run pin (reset button) being toggled.
+ */
+bool watchdog_enable_caused_reboot(void);
+
 /**
  * @brief Returns the number of microseconds before the watchdog will reboot the chip.
  * \ingroup hardware_watchdog
diff --git a/src/rp2_common/hardware_watchdog/watchdog.c b/src/rp2_common/hardware_watchdog/watchdog.c
index 36031aaff..954520577 100644
--- a/src/rp2_common/hardware_watchdog/watchdog.c
+++ b/src/rp2_common/hardware_watchdog/watchdog.c
@@ -49,25 +49,28 @@ void _watchdog_enable(uint32_t delay_ms, bool pause_on_debug) {
         hw_clear_bits(&watchdog_hw->ctrl, dbg_bits);
     }
 
-    if (!delay_ms) delay_ms = 50;
-
-    // Note, we have x2 here as the watchdog HW currently decrements twice per tick
-    load_value = delay_ms * 1000 * 2;
-
-    if (load_value > 0xffffffu)
-        load_value = 0xffffffu;
+    if (!delay_ms) {
+        hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_TRIGGER_BITS);
+    } else {
+        // Note, we have x2 here as the watchdog HW currently decrements twice per tick
+        load_value = delay_ms * 1000 * 2;
 
+        if (load_value > 0xffffffu)
+            load_value = 0xffffffu;
 
-    watchdog_update();
+        watchdog_update();
 
-    hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS);
+        hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS);
+    }
 }
 // end::watchdog_enable[]
 
+#define WATCHDOG_NON_REBOOT_MAGIC 0x6ab73121
+
 void watchdog_enable(uint32_t delay_ms, bool pause_on_debug) {
-    // This watchdog enable doesn't reboot so clear scratch register
-    // with magic word to jump into code
-    watchdog_hw->scratch[4] = 0;
+    // update scratch[4] to distinguish from magic used for reboot to specific address, or 0 used to reboot
+    // into regular flash path
+    watchdog_hw->scratch[4] = WATCHDOG_NON_REBOOT_MAGIC;
     _watchdog_enable(delay_ms, pause_on_debug);
 }
 
@@ -96,4 +99,8 @@ void watchdog_reboot(uint32_t pc, uint32_t sp, uint32_t delay_ms) {
 bool watchdog_caused_reboot(void) {
     // If any reason bits are set this is true
     return watchdog_hw->reason;
+}
+
+bool watchdog_enable_caused_reboot(void) {
+    return watchdog_hw->reason && watchdog_hw->scratch[4] == WATCHDOG_NON_REBOOT_MAGIC;
 }
\ No newline at end of file
diff --git a/src/rp2_common/hardware_xosc/xosc.c b/src/rp2_common/hardware_xosc/xosc.c
index 9a95e372b..7a7055cb7 100644
--- a/src/rp2_common/hardware_xosc/xosc.c
+++ b/src/rp2_common/hardware_xosc/xosc.c
@@ -13,8 +13,8 @@
 #include "hardware/regs/xosc.h"
 #include "hardware/xosc.h"
 
-#if XOSC_MHZ < 1 || XOSC_MHZ > 15
-#error XOSC_MHZ must be in the range 1-15
+#if XOSC_MHZ < 1 || XOSC_MHZ > 50
+#error XOSC_MHZ must be in the range 1-50
 #endif
 
 #define STARTUP_DELAY (((((XOSC_MHZ * MHZ) / 1000) + 128) / 256) * PICO_XOSC_STARTUP_DELAY_MULTIPLIER)
diff --git a/src/rp2_common/pico_bit_ops/bit_ops_aeabi.S b/src/rp2_common/pico_bit_ops/bit_ops_aeabi.S
index 7c0b42cc6..eba839eed 100644
--- a/src/rp2_common/pico_bit_ops/bit_ops_aeabi.S
+++ b/src/rp2_common/pico_bit_ops/bit_ops_aeabi.S
@@ -9,6 +9,8 @@
 .thumb
 
 #include "pico/asm_helper.S"
+#include "pico/bootrom.h"
+
 __pre_init __aeabi_bits_init, 00010
 
 .macro bits_section name
@@ -24,10 +26,10 @@ __pre_init __aeabi_bits_init, 00010
 .equ BITS_FUNC_COUNT, 4
 .align 4
 aeabi_bits_funcs:
-    .word rom_table_code('P','3') // popcount32
-    .word rom_table_code('L','3') // clz32
-    .word rom_table_code('T','3') // ctz32
-    .word rom_table_code('R','3') // reverse32
+    .word ROM_FUNC_POPCOUNT32
+    .word ROM_FUNC_CLZ32
+    .word ROM_FUNC_CTZ32
+    .word ROM_FUNC_REVERSE32
 aeabi_bits_funcs_end:
 
 .section .text
diff --git a/src/rp2_common/pico_bootrom/bootrom.c b/src/rp2_common/pico_bootrom/bootrom.c
index 08cdb3373..af7d09148 100644
--- a/src/rp2_common/pico_bootrom/bootrom.c
+++ b/src/rp2_common/pico_bootrom/bootrom.c
@@ -16,9 +16,7 @@ typedef void *(*rom_table_lookup_fn)(uint16_t *table, uint32_t code);
 #define rom_hword_as_ptr(rom_address) (void *)(uintptr_t)(*(uint16_t *)rom_address)
 
 void *rom_func_lookup(uint32_t code) {
-    rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) rom_hword_as_ptr(0x18);
-    uint16_t *func_table = (uint16_t *) rom_hword_as_ptr(0x14);
-    return rom_table_lookup(func_table, code);
+    return rom_func_lookup_inline(code);
 }
 
 void *rom_data_lookup(uint32_t code) {
diff --git a/src/rp2_common/pico_bootrom/include/pico/bootrom.h b/src/rp2_common/pico_bootrom/include/pico/bootrom.h
index 7d42926b6..e55789315 100644
--- a/src/rp2_common/pico_bootrom/include/pico/bootrom.h
+++ b/src/rp2_common/pico_bootrom/include/pico/bootrom.h
@@ -12,7 +12,59 @@
 /** \file bootrom.h
  * \defgroup pico_bootrom pico_bootrom
  * Access to functions and data in the RP2040 bootrom
+ *
+ * This header may be included by assembly code
+ */
+
+// ROM FUNCTIONS
+
+#define ROM_FUNC_POPCOUNT32             ROM_TABLE_CODE('P', '3')
+#define ROM_FUNC_REVERSE32              ROM_TABLE_CODE('R', '3')
+#define ROM_FUNC_CLZ32                  ROM_TABLE_CODE('L', '3')
+#define ROM_FUNC_CTZ32                  ROM_TABLE_CODE('T', '3')
+#define ROM_FUNC_MEMSET                 ROM_TABLE_CODE('M', 'S')
+#define ROM_FUNC_MEMSET4                ROM_TABLE_CODE('S', '4')
+#define ROM_FUNC_MEMCPY                 ROM_TABLE_CODE('M', 'C')
+#define ROM_FUNC_MEMCPY44               ROM_TABLE_CODE('C', '4')
+#define ROM_FUNC_RESET_USB_BOOT         ROM_TABLE_CODE('U', 'B')
+#define ROM_FUNC_CONNECT_INTERNAL_FLASH ROM_TABLE_CODE('I', 'F')
+#define ROM_FUNC_FLASH_EXIT_XIP         ROM_TABLE_CODE('E', 'X')
+#define ROM_FUNC_FLASH_RANGE_ERASE      ROM_TABLE_CODE('R', 'E')
+#define ROM_FUNC_FLASH_RANGE_PROGRAM    ROM_TABLE_CODE('R', 'P')
+#define ROM_FUNC_FLASH_FLUSH_CACHE      ROM_TABLE_CODE('F', 'C')
+#define ROM_FUNC_FLASH_ENTER_CMD_XIP    ROM_TABLE_CODE('C', 'X')
+
+/*! \brief Return a bootrom lookup code based on two ASCII characters
+ * \ingroup pico_bootrom
+ *
+ * These codes are uses to lookup data or function addresses in the bootrom
+ *
+ * \param c1 the first character
+ * \param c2 the second character
+ * \return the 'code' to use in rom_func_lookup() or rom_data_lookup()
  */
+#define ROM_TABLE_CODE(c1, c2) ((c1) | ((c2) << 8))
+
+#ifndef __ASSEMBLER__
+
+// ROM FUNCTION SIGNATURES
+
+typedef uint32_t (*rom_popcount32_fn)(uint32_t);
+typedef uint32_t (*rom_reverse32_fn)(uint32_t);
+typedef uint32_t (*rom_clz32_fn)(uint32_t);
+typedef uint32_t (*rom_ctz32_fn)(uint32_t);
+typedef uint8_t *(*rom_memset_fn)(uint8_t *, uint8_t, uint32_t);
+typedef uint32_t *(*rom_memset4_fn)(uint32_t *, uint8_t, uint32_t);
+typedef uint32_t *(*rom_memcpy_fn)(uint8_t *, const uint8_t *, uint32_t);
+typedef uint32_t *(*rom_memcpy44_fn)(uint32_t *, const uint32_t *, uint32_t);
+typedef void __attribute__((noreturn)) (*rom_reset_usb_boot_fn)(uint32_t, uint32_t);
+typedef rom_reset_usb_boot_fn reset_usb_boot_fn; // kept for backwards compatibility
+typedef void (*rom_connect_internal_flash_fn)(void);
+typedef void (*rom_flash_exit_xip_fn)(void);
+typedef void (*rom_flash_range_erase_fn)(uint32_t, size_t, uint32_t, uint8_t);
+typedef void (*rom_flash_range_program_fn)(uint32_t, const uint8_t*, size_t);
+typedef void (*rom_flash_flush_cache_fn)(void);
+typedef void (*rom_flash_enter_cmd_xip_fn)(void);
 
 #ifdef __cplusplus
 extern "C" {
@@ -22,13 +74,13 @@ extern "C" {
  * \ingroup pico_bootrom
  *
  * These codes are uses to lookup data or function addresses in the bootrom
- * 
+ *
  * \param c1 the first character
  * \param c2 the second character
  * \return the 'code' to use in rom_func_lookup() or rom_data_lookup()
  */
 static inline uint32_t rom_table_code(uint8_t c1, uint8_t c2) {
-    return (((uint)c2) << 8u) | (uint)c1;
+    return ROM_TABLE_CODE((uint32_t) c1, (uint32_t) c2);
 }
 
 /*!
@@ -60,7 +112,24 @@ void *rom_data_lookup(uint32_t code);
  */
 bool rom_funcs_lookup(uint32_t *table, unsigned int count);
 
-typedef void __attribute__((noreturn)) (*reset_usb_boot_fn)(uint32_t, uint32_t);
+// Bootrom function: rom_table_lookup
+// Returns the 32 bit pointer into the ROM if found or NULL otherwise.
+typedef void *(*rom_table_lookup_fn)(uint16_t *table, uint32_t code);
+
+// Convert a 16 bit pointer stored at the given rom address into a 32 bit pointer
+#define rom_hword_as_ptr(rom_address) (void *)(uintptr_t)(*(uint16_t *)rom_address)
+
+/*!
+ * \brief Lookup a bootrom function by code. This method is forceably inlined into the caller for FLASH/RAM sensitive code usage
+ * \ingroup pico_bootrom
+ * \param code the code
+ * \return a pointer to the function, or NULL if the code does not match any bootrom function
+ */
+static __force_inline void *rom_func_lookup_inline(uint32_t code) {
+    rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) rom_hword_as_ptr(0x18);
+    uint16_t *func_table = (uint16_t *) rom_hword_as_ptr(0x14);
+    return rom_table_lookup(func_table, code);
+}
 
 /*!
  * \brief Reboot the device into BOOTSEL mode
@@ -81,7 +150,7 @@ typedef void __attribute__((noreturn)) (*reset_usb_boot_fn)(uint32_t, uint32_t);
  */
 static inline void __attribute__((noreturn)) reset_usb_boot(uint32_t usb_activity_gpio_pin_mask,
                                                             uint32_t disable_interface_mask) {
-    reset_usb_boot_fn func = (reset_usb_boot_fn) rom_func_lookup(rom_table_code('U', 'B'));
+    rom_reset_usb_boot_fn func = (rom_reset_usb_boot_fn) rom_func_lookup(ROM_FUNC_RESET_USB_BOOT);
     func(usb_activity_gpio_pin_mask, disable_interface_mask);
 }
 
@@ -89,4 +158,5 @@ static inline void __attribute__((noreturn)) reset_usb_boot(uint32_t usb_activit
 }
 #endif
 
+#endif // !__ASSEMBLER__
 #endif
diff --git a/src/rp2_common/pico_bootsel_via_double_reset/pico_bootsel_via_double_reset.c b/src/rp2_common/pico_bootsel_via_double_reset/pico_bootsel_via_double_reset.c
index 595a2d51e..d333ab2ff 100644
--- a/src/rp2_common/pico_bootsel_via_double_reset/pico_bootsel_via_double_reset.c
+++ b/src/rp2_common/pico_bootsel_via_double_reset/pico_bootsel_via_double_reset.c
@@ -43,8 +43,7 @@ static const uint32_t magic_token[] = {
 
 static uint32_t __uninitialized_ram(magic_location)[count_of(magic_token)];
 
-/*! \brief Check for double reset and enter BOOTSEL mode if detected
- *  \ingroup pico_bootsel_via_double_reset
+/* Check for double reset and enter BOOTSEL mode if detected
  *
  * This function is registered to run automatically before main(). The
  * algorithm is:
diff --git a/src/rp2_common/pico_divider/CMakeLists.txt b/src/rp2_common/pico_divider/CMakeLists.txt
index 813d1c14c..ceed04275 100644
--- a/src/rp2_common/pico_divider/CMakeLists.txt
+++ b/src/rp2_common/pico_divider/CMakeLists.txt
@@ -21,6 +21,7 @@ if (NOT TARGET pico_divider)
 
     target_link_libraries(pico_divider_hardware_explicit INTERFACE
             pico_divider_headers
+            hardware_divider
             hardware_regs
             )
 
diff --git a/src/rp2_common/pico_divider/divider.S b/src/rp2_common/pico_divider/divider.S
index ac67a5e7a..234c1a472 100644
--- a/src/rp2_common/pico_divider/divider.S
+++ b/src/rp2_common/pico_divider/divider.S
@@ -413,6 +413,7 @@ y64:
  lsls r3,#16
  orrs r3,r4
  str r3,[r7,#SIO_DIV_UDIVIDEND_OFFSET] @ y1=(r0<<16)+(((ui32)y)>>16);
+ str r2,[r7,#SIO_DIV_UDIVISOR_OFFSET]  @ must set divisor again, as we do not save/restore regs at all in IRQs if not dirty
  wait_div 1
  uxth r4,r0
  ldr r3,[r7,#SIO_DIV_REMAINDER_OFFSET] @ r1=y1-q1*x; 0<=r1<x
@@ -420,6 +421,7 @@ y64:
  lsls r3,#16
  orrs r3,r4
  str r3,[r7,#SIO_DIV_UDIVIDEND_OFFSET] @ y1=(r0<<16)+(((ui32)y)>>16);
+ str r2,[r7,#SIO_DIV_UDIVISOR_OFFSET]  @ must set divisor again, as we do not save/restore regs at all in IRQs if not dirty
  wait_div 3
  movs r3,#0
  lsls r4,r5,#16             @ quotient=(q0<<32)+(q1<<16)+q2
diff --git a/src/rp2_common/pico_double/double_aeabi.S b/src/rp2_common/pico_double/double_aeabi.S
index a871e4384..0c5973841 100644
--- a/src/rp2_common/pico_double/double_aeabi.S
+++ b/src/rp2_common/pico_double/double_aeabi.S
@@ -83,7 +83,7 @@ __check_nan_d2:
 
 .macro table_tail_call SF_TABLE_OFFSET
     push {r3, r4}
-#if PICO_DOUBLE_SUPPORT_ROM_V1
+#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
 #ifndef NDEBUG
     movs r3, #0
     mov ip, r3
@@ -99,12 +99,12 @@ __check_nan_d2:
     push {r3, r4}
     ldr r3, =sd_table
     ldr r3, [r3, #\SF_TABLE_OFFSET]
-#if PICO_DOUBLE_SUPPORT_ROM_V1
+#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
     mov ip, pc
 #endif
     str r3, [sp, #4]
     pop {r3, pc}
-#if PICO_DOUBLE_SUPPORT_ROM_V1
+#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
 .byte \SF_TABLE_OFFSET, 0xdf
 .word \shim
 #endif
@@ -733,7 +733,7 @@ sincos_shim_bootstrap:
     push {r2, r3, r4}
     movs r3, #0x13
     ldrb r3, [r3]
-#if PICO_DOUBLE_SUPPORT_ROM_V1
+#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
     cmp r3, #1
     bne 1f
     ldr r3, =dsincos_shim
diff --git a/src/rp2_common/pico_double/double_init_rom.c b/src/rp2_common/pico_double/double_init_rom.c
index 1a255595d..af6f6a2c3 100644
--- a/src/rp2_common/pico_double/double_init_rom.c
+++ b/src/rp2_common/pico_double/double_init_rom.c
@@ -12,16 +12,18 @@
 // IT IS ***NOT*** SAFE TO CALL THESE FUNCTION POINTERS FROM ARBITRARY CODE
 uint32_t sd_table[SF_TABLE_V2_SIZE / 2];
 
-#if !PICO_DOUBLE_SUPPORT_ROM_V1
+#if !(PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED)
 static __attribute__((noreturn)) void missing_double_func_shim(void) {
     panic("missing double function");
 }
 #endif
 extern void double_table_shim_on_use_helper(void);
 
+void __attribute__((weak)) *sf_clz_func;
+
 void __aeabi_double_init(void) {
     int rom_version = rp2040_rom_version();
-#if PICO_DOUBLE_SUPPORT_ROM_V1
+#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
     if (rom_version == 1) {
 
         // this is a little tricky.. we only want to pull in a shim if the corresponding function
@@ -63,4 +65,6 @@ void __aeabi_double_init(void) {
         // we use the unused entry for SINCOS
         sd_table[SF_TABLE_V3_FSINCOS / 4] = (uintptr_t) double_table_shim_on_use_helper;
     }
+
+    sf_clz_func = rom_func_lookup(ROM_FUNC_CLZ32);
 }
diff --git a/src/rp2_common/pico_double/double_math.c b/src/rp2_common/pico_double/double_math.c
index c6db8c12b..6c35ded4a 100644
--- a/src/rp2_common/pico_double/double_math.c
+++ b/src/rp2_common/pico_double/double_math.c
@@ -41,11 +41,25 @@ typedef int64_t i64;
 #define DUNPACK(x,e,m) e=((x)>>52)&0x7ff,m=((x)&0x000fffffffffffffULL)|0x0010000000000000ULL
 #define DUNPACKS(x,s,e,m) s=((x)>>63),DUNPACK((x),(e),(m))
 
-_Pragma("GCC diagnostic push")
-_Pragma("GCC diagnostic ignored \"-Wstrict-aliasing\"")
+typedef union {
+    double d;
+    ui64 ix;
+} double_ui64;
+
+static inline double ui642double(ui64 ix) {
+    double_ui64 tmp;
+    tmp.ix = ix;
+    return tmp.d;
+}
+
+static inline ui64 double2ui64(double d) {
+    double_ui64 tmp;
+    tmp.d = d;
+    return tmp.ix;
+}
 
 static inline bool disnan(double x) {
-    ui64 ix=*(ui64*)&x;
+    ui64 ix= double2ui64(x);
     // checks the top bit of the low 32 bit of the NAN, but it I think that is ok
     return ((uint32_t)(ix >> 31)) > 0xffe00000u;
 }
@@ -59,17 +73,17 @@ static inline bool disnan(double x) {
 #endif
 
 static inline int dgetsignexp(double x) {
-    ui64 ix=*(ui64*)&x;
+    ui64 ix=double2ui64(x);
     return (ix>>52)&0xfff;
 }
 
 static inline int dgetexp(double x) {
-    ui64 ix=*(ui64*)&x;
+    ui64 ix=double2ui64(x);
     return (ix>>52)&0x7ff;
 }
 
 static inline double dldexp(double x,int de) {
-    ui64 ix=*(ui64*)&x,iy;
+    ui64 ix=double2ui64(x),iy;
     int e;
     e=dgetexp(x);
     if(e==0||e==0x7ff) return x;
@@ -77,7 +91,7 @@ static inline double dldexp(double x,int de) {
     if(e<=0) iy=ix&0x8000000000000000ULL; // signed zero for underflow
     else if(e>=0x7ff) iy=(ix&0x8000000000000000ULL)|0x7ff0000000000000ULL; // signed infinity on overflow
     else iy=ix+((ui64)de<<52);
-    return *(double*)&iy;
+    return ui642double(iy);
 }
 
 double WRAPPER_FUNC(ldexp)(double x, int de) {
@@ -87,9 +101,9 @@ double WRAPPER_FUNC(ldexp)(double x, int de) {
 
 
 static inline double dcopysign(double x,double y) {
-    ui64 ix=*(ui64*)&x,iy=*(ui64*)&y;
+    ui64 ix=double2ui64(x),iy=double2ui64(y);
     ix=((ix&0x7fffffffffffffffULL)|(iy&0x8000000000000000ULL));
-    return *(double*)&ix;
+    return ui642double(ix);
 }
 
 double WRAPPER_FUNC(copysign)(double x, double y) {
@@ -104,7 +118,7 @@ static inline int dispinf(double x)  { return dgetsignexp(x)==0x7ff; }
 static inline int disminf(double x)  { return dgetsignexp(x)==0xfff; }
 
 static inline int disint(double x) {
-    ui64 ix=*(ui64*)&x,m;
+    ui64 ix=double2ui64(x),m;
     int e=dgetexp(x);
     if(e==0) return 1;       // 0 is an integer
     e-=0x3ff;                // remove exponent bias
@@ -117,7 +131,7 @@ static inline int disint(double x) {
 }
 
 static inline int disoddint(double x) {
-    ui64 ix=*(ui64*)&x,m;
+    ui64 ix=double2ui64(x),m;
     int e=dgetexp(x);
     e-=0x3ff;                // remove exponent bias
     if(e<0) return 0;        // |x|<1; 0 is not odd
@@ -130,24 +144,24 @@ static inline int disoddint(double x) {
 }
 
 static inline int disstrictneg(double x) {
-    ui64 ix=*(ui64*)&x;
+    ui64 ix=double2ui64(x);
     if(diszero(x)) return 0;
     return ix>>63;
 }
 
 static inline int disneg(double x) {
-    ui64 ix=*(ui64*)&x;
+    ui64 ix=double2ui64(x);
     return ix>>63;
 }
 
 static inline double dneg(double x) {
-    ui64 ix=*(ui64*)&x;
+    ui64 ix=double2ui64(x);
     ix^=0x8000000000000000ULL;
-    return *(double*)&ix;
+    return ui642double(ix);
 }
 
 static inline int dispo2(double x) {
-    ui64 ix=*(ui64*)&x;
+    ui64 ix=double2ui64(x);
     if(diszero(x)) return 0;
     if(disinf(x)) return 0;
     ix&=0x000fffffffffffffULL;
@@ -164,33 +178,33 @@ static inline double dnan_or(double x) {
 
 double WRAPPER_FUNC(trunc)(double x) {
     check_nan_d1(x);
-    ui64 ix=*(ui64*)&x,m;
+    ui64 ix=double2ui64(x),m;
     int e=dgetexp(x);
     e-=0x3ff;                // remove exponent bias
     if(e<0) {                // |x|<1
         ix&=0x8000000000000000ULL;
-        return *(double*)&ix;
+        return ui642double(ix);
     }
     e=52-e;                  // bit position in mantissa with significance 1
     if(e<=0) return x;       // |x| large, so must be an integer
     m=(1ULL<<e)-1;           // mask for bits of significance <1
     ix&=~m;
-    return *(double*)&ix;
+    return ui642double(ix);
 }
 
 double WRAPPER_FUNC(round)(double x) {
     check_nan_d1(x);
-    ui64 ix=*(ui64*)&x,m;
+    ui64 ix=double2ui64(x),m;
     int e=dgetexp(x);
     e-=0x3ff;                // remove exponent bias
     if(e<-1) {               // |x|<0.5
         ix&=0x8000000000000000ULL;
-        return *(double*)&ix;
+        return ui642double(ix);
     }
     if(e==-1) {              // 0.5<=|x|<1
         ix&=0x8000000000000000ULL;
         ix|=0x3ff0000000000000ULL;        // ±1
-        return *(double*)&ix;
+        return ui642double(ix);
     }
     e=52-e;                  // bit position in mantissa with significance 1, <=52
     if(e<=0) return x;       // |x| large, so must be an integer
@@ -198,16 +212,16 @@ double WRAPPER_FUNC(round)(double x) {
     ix+=m;
     m=m+m-1;                 // mask for bits of significance <1
     ix&=~m;
-    return *(double*)&ix;
+    return ui642double(ix);
 }
 
 double WRAPPER_FUNC(floor)(double x) {
     check_nan_d1(x);
-    ui64 ix=*(ui64*)&x,m;
+    ui64 ix=double2ui64(x),m;
     int e=dgetexp(x);
     if(e==0) {               // x==0
         ix&=0x8000000000000000ULL;
-        return *(double*)&ix;
+        return ui642double(ix);
     }
     e-=0x3ff;                // remove exponent bias
     if(e<0) {                // |x|<1, not zero
@@ -219,16 +233,16 @@ double WRAPPER_FUNC(floor)(double x) {
     m=(1ULL<<e)-1;           // mask for bit of significance <1
     if(disneg(x)) ix+=m;     // add 1-ε to magnitude if negative
     ix&=~m;                  // truncate
-    return *(double*)&ix;
+    return ui642double(ix);
 }
 
 double WRAPPER_FUNC(ceil)(double x) {
     check_nan_d1(x);
-    ui64 ix=*(ui64*)&x,m;
+    ui64 ix=double2ui64(x),m;
     int e=dgetexp(x);
     if(e==0) {               // x==0
         ix&=0x8000000000000000ULL;
-        return *(double*)&ix;
+        return ui642double(ix);
     }
     e-=0x3ff;                 // remove exponent bias
     if(e<0) {                // |x|<1, not zero
@@ -240,7 +254,7 @@ double WRAPPER_FUNC(ceil)(double x) {
     m=(1ULL<<e)-1;           // mask for bit of significance <1
     if(!disneg(x)) ix+=m;    // add 1-ε to magnitude if positive
     ix&=~m;                  // truncate
-    return *(double*)&ix;
+    return ui642double(ix);
 }
 
 double WRAPPER_FUNC(asin)(double x) {
@@ -549,7 +563,7 @@ static i64 drem_0(i64 mx,i64 my,int e,int*pquo) {
 
 double WRAPPER_FUNC(fmod)(double x,double y) {
     check_nan_d2(x, y);
-    ui64 ix=*(ui64*)&x,iy=*(ui64*)&y;
+    ui64 ix=double2ui64(x),iy=double2ui64(y);
     int sx,ex,ey;
     i64 mx,my;
     DUNPACKS(ix,sx,ex,mx);
@@ -568,7 +582,7 @@ double WRAPPER_FUNC(fmod)(double x,double y) {
 
 double WRAPPER_FUNC(remquo)(double x,double y,int*quo) {
     check_nan_d2(x, y);
-    ui64 ix=*(ui64*)&x,iy=*(ui64*)&y;
+    ui64 ix=double2ui64(x),iy=double2ui64(y);
     int sx,sy,ex,ey,q;
     i64 mx,my;
     DUNPACKS(ix,sx,ex,mx);
@@ -609,5 +623,4 @@ double WRAPPER_FUNC(drem)(double x,double y) { check_nan_d2(x, y); return remquo
 
 double WRAPPER_FUNC(remainder)(double x,double y) { check_nan_d2(x, y); return remquo(x,y,0); }
 
-_Pragma("GCC diagnostic pop") // strict-aliasing
 _Pragma("GCC diagnostic pop") // conversion
\ No newline at end of file
diff --git a/src/rp2_common/pico_double/double_v1_rom_shim.S b/src/rp2_common/pico_double/double_v1_rom_shim.S
index a8db6b703..7a14ca4fd 100644
--- a/src/rp2_common/pico_double/double_v1_rom_shim.S
+++ b/src/rp2_common/pico_double/double_v1_rom_shim.S
@@ -63,7 +63,7 @@ regular_func double_table_shim_on_use_helper
     str r0, [sp, #12]
     pop {r0-r2, pc}
 
-#if PICO_DOUBLE_SUPPORT_ROM_V1
+#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
 // Note that the V1 ROM has no double support, so this is basically the identical
 // library, and shim inter-function calls do not bother to redirect back thru the
 // wrapper functions
@@ -1218,11 +1218,6 @@ double_section dcordic_rot_step
  mov r9,r3
  bx r14
 
-ret_dzero:
- movs r0,#0
- movs r1,#0
- bx r14
-
 @ convert packed double in r0:r1 to signed/unsigned 32/64-bit integer/fixed-point value in r0:r1 [with r2 places after point], with rounding towards -Inf
 @ fixed-point versions only work with reasonable values in r2 because of the way dunpacks works
 
@@ -1264,7 +1259,7 @@ regular_func double2fix64_shim
  eors r1,r1,r0                 @ generate extreme fixed-point values
  pop {r15}
 
-double_section double2uint64_shim
+double_section double2uint64_shim 
  regular_func double2uint64_shim
  movs r2,#0                    @ and fall through
 regular_func double2ufix64_shim
@@ -1288,7 +1283,12 @@ d2fix:
  asrs r3,r1,#31
  ldr r4, =d2fix_a
  bx r4
-
+ 
+ret_dzero:
+ movs r0,#0
+ movs r1,#0
+ bx r14
+ 
 .weak d2fix_a // weak because it exists in float code too
 regular_func d2fix_a
 @ here
@@ -2181,4 +2181,4 @@ dtab_exp:
 .word 0x40000000, 0x00000000   @ log 1+2^-32 Q62
 
 
-#endif
\ No newline at end of file
+#endif
diff --git a/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c b/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c
index 91583205b..e1073ca43 100644
--- a/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c
+++ b/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c
@@ -22,16 +22,21 @@ static void hw_enumeration_fix_force_ls_j(void);
 static void hw_enumeration_fix_finish(void);
 
 void rp2040_usb_device_enumeration_fix(void) {
-    // After coming out of reset, the hardware expects 800us of LS_J (linestate J) time
-    // before it will move to the connected state. However on a hub that broadcasts packets
-    // for other devices this isn't the case. The plan here is to wait for the end of the bus
-    // reset, force an LS_J for 1ms and then switch control back to the USB phy. Unfortunately
-    // this requires us to use GPIO15 as there is no other way to force the input path.
-    // We only need to force DP as DM can be left at zero. It will be gated off by GPIO
-    // logic if it isn't func selected.
-
-    // Wait SE0 phase will call force ls_j phase which will call finish phase
-    hw_enumeration_fix_wait_se0();
+#if PICO_RP2040_B0_SUPPORTED || PICO_RP2040_B1_SUPPORTED
+    // Actually check for B0/B1 h/w
+    if (rp2040_chip_version() == 1) {
+        // After coming out of reset, the hardware expects 800us of LS_J (linestate J) time
+        // before it will move to the connected state. However on a hub that broadcasts packets
+        // for other devices this isn't the case. The plan here is to wait for the end of the bus
+        // reset, force an LS_J for 1ms and then switch control back to the USB phy. Unfortunately
+        // this requires us to use GPIO15 as there is no other way to force the input path.
+        // We only need to force DP as DM can be left at zero. It will be gated off by GPIO
+        // logic if it isn't func selected.
+
+        // Wait SE0 phase will call force ls_j phase which will call finish phase
+        hw_enumeration_fix_wait_se0();
+    }
+#endif
 }
 
 static inline uint8_t hw_line_state(void) {
diff --git a/src/rp2_common/pico_float/float_aeabi.S b/src/rp2_common/pico_float/float_aeabi.S
index b901d3038..db393dfa3 100644
--- a/src/rp2_common/pico_float/float_aeabi.S
+++ b/src/rp2_common/pico_float/float_aeabi.S
@@ -80,7 +80,7 @@ __check_nan_f2:
 #endif
 
 .macro table_tail_call SF_TABLE_OFFSET
-#if PICO_FLOAT_SUPPORT_ROM_V1
+#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
 #ifndef NDEBUG
     movs r3, #0
     mov ip, r3
@@ -94,11 +94,11 @@ __check_nan_f2:
 .macro shimmable_table_tail_call SF_TABLE_OFFSET shim
     ldr r3, =sf_table
     ldr r3, [r3, #\SF_TABLE_OFFSET]
-#if PICO_FLOAT_SUPPORT_ROM_V1
+#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
     mov ip, pc
 #endif
     bx r3
-#if PICO_FLOAT_SUPPORT_ROM_V1
+#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
 .byte \SF_TABLE_OFFSET, 0xdf
 .word \shim
 #endif
@@ -584,13 +584,13 @@ wrapper_func __aeabi_f2d
 
 float_wrapper_section srqtf
 wrapper_func_f1 sqrtf
-#if PICO_FLOAT_SUPPORT_ROM_V1
+#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
     // check for negative
     asrs r1, r0, #23
     bmi 1f
 #endif
     table_tail_call SF_TABLE_FSQRT
-#if PICO_FLOAT_SUPPORT_ROM_V1
+#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
 1:
     mvns r0, r1
     cmp r0, #255
diff --git a/src/rp2_common/pico_float/float_init_rom.c b/src/rp2_common/pico_float/float_init_rom.c
index 24c74ce94..646c0e940 100644
--- a/src/rp2_common/pico_float/float_init_rom.c
+++ b/src/rp2_common/pico_float/float_init_rom.c
@@ -11,9 +11,9 @@
 // NOTE THIS FUNCTION TABLE IS NOT PUBLIC OR NECESSARILY COMPLETE...
 // IT IS ***NOT*** SAFE TO CALL THESE FUNCTION POINTERS FROM ARBITRARY CODE
 uint32_t sf_table[SF_TABLE_V2_SIZE / 2];
-void *sf_clz_func;
+void __attribute__((weak)) *sf_clz_func;
 
-#if !PICO_FLOAT_SUPPORT_ROM_V1
+#if !(PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED)
 static __attribute__((noreturn)) void missing_float_func_shim(void) {
     panic("");
 }
@@ -22,7 +22,7 @@ static __attribute__((noreturn)) void missing_float_func_shim(void) {
 void __aeabi_float_init(void) {
     int rom_version = rp2040_rom_version();
     void *rom_table = rom_data_lookup(rom_table_code('S', 'F'));
-#if PICO_FLOAT_SUPPORT_ROM_V1
+#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
     if (rom_version == 1) {
         memcpy(&sf_table, rom_table, SF_TABLE_V1_SIZE);
         extern void float_table_shim_on_use_helper(void);
@@ -66,5 +66,5 @@ void __aeabi_float_init(void) {
         assert(*((uint8_t *)(rom_table-2)) * 4 >= SF_TABLE_V2_SIZE);
         memcpy(&sf_table, rom_table, SF_TABLE_V2_SIZE);
     }
-    sf_clz_func = rom_func_lookup(rom_table_code('L', '3'));
+    sf_clz_func = rom_func_lookup(ROM_FUNC_CLZ32);
 }
diff --git a/src/rp2_common/pico_float/float_math.c b/src/rp2_common/pico_float/float_math.c
index bc7fa9a0a..a48a2d724 100644
--- a/src/rp2_common/pico_float/float_math.c
+++ b/src/rp2_common/pico_float/float_math.c
@@ -39,11 +39,25 @@ typedef int32_t i32;
 #define FUNPACK(x,e,m) e=((x)>>23)&0xff,m=((x)&0x007fffff)|0x00800000
 #define FUNPACKS(x,s,e,m) s=((x)>>31),FUNPACK((x),(e),(m))
 
-_Pragma("GCC diagnostic push")
-_Pragma("GCC diagnostic ignored \"-Wstrict-aliasing\"")
+typedef union {
+    float f;
+    ui32 ix;
+} float_ui32;
+
+static inline float ui322float(ui32 ix) {
+    float_ui32 tmp;
+    tmp.ix = ix;
+    return tmp.f;
+}
+
+static inline ui32 float2ui32(float f) {
+    float_ui32 tmp;
+    tmp.f = f;
+    return tmp.ix;
+}
 
 static inline bool fisnan(float x) {
-    ui32 ix=*(ui32*)&x;
+    ui32 ix=float2ui32(x);
     return ix * 2 > 0xff000000u;
 }
 
@@ -56,17 +70,17 @@ static inline bool fisnan(float x) {
 #endif
 
 static inline int fgetsignexp(float x) {
-    ui32 ix=*(ui32*)&x;
+    ui32 ix=float2ui32(x);
     return (ix>>23)&0x1ff;
 }
 
 static inline int fgetexp(float x) {
-    ui32 ix=*(ui32*)&x;
+    ui32 ix=float2ui32(x);
     return (ix>>23)&0xff;
 }
 
 static inline float fldexp(float x,int de) {
-    ui32 ix=*(ui32*)&x,iy;
+    ui32 ix=float2ui32(x),iy;
     int e;
     e=fgetexp(x);
     if(e==0||e==0xff) return x;
@@ -74,7 +88,7 @@ static inline float fldexp(float x,int de) {
     if(e<=0) iy=ix&0x80000000; // signed zero for underflow
     else if(e>=0xff) iy=(ix&0x80000000)|0x7f800000ULL; // signed infinity on overflow
     else iy=ix+((ui32)de<<23);
-    return *(float*)&iy;
+    return ui322float(iy);
 }
 
 float WRAPPER_FUNC(ldexpf)(float x, int de) {
@@ -83,9 +97,9 @@ float WRAPPER_FUNC(ldexpf)(float x, int de) {
 }
 
 static inline float fcopysign(float x,float y) {
-    ui32 ix=*(ui32*)&x,iy=*(ui32*)&y;
+    ui32 ix=float2ui32(x),iy=float2ui32(y);
     ix=((ix&0x7fffffff)|(iy&0x80000000));
-    return *(float*)&ix;
+    return ui322float(ix);
 }
 
 float WRAPPER_FUNC(copysignf)(float x, float y) {
@@ -101,7 +115,7 @@ static inline int fispinf(float x)  { return fgetsignexp(x)==0xff; }
 static inline int fisminf(float x)  { return fgetsignexp(x)==0x1ff; }
 
 static inline int fisint(float x) {
-    ui32 ix=*(ui32*)&x,m;
+    ui32 ix=float2ui32(x),m;
     int e=fgetexp(x);
     if(e==0) return 1;       // 0 is an integer
     e-=0x7f;                 // remove exponent bias
@@ -114,7 +128,7 @@ static inline int fisint(float x) {
 }
 
 static inline int fisoddint(float x) {
-    ui32 ix=*(ui32*)&x,m;
+    ui32 ix=float2ui32(x),m;
     int e=fgetexp(x);
     e-=0x7f;                 // remove exponent bias
     if(e<0) return 0;        // |x|<1; 0 is not odd
@@ -127,24 +141,24 @@ static inline int fisoddint(float x) {
 }
 
 static inline int fisstrictneg(float x) {
-    ui32 ix=*(ui32*)&x;
+    ui32 ix=float2ui32(x);
     if(fiszero(x)) return 0;
     return ix>>31;
 }
 
 static inline int fisneg(float x) {
-    ui32 ix=*(ui32*)&x;
+    ui32 ix=float2ui32(x);
     return ix>>31;
 }
 
 static inline float fneg(float x) {
-    ui32 ix=*(ui32*)&x;
+    ui32 ix=float2ui32(x);
     ix^=0x80000000;
-    return *(float*)&ix;
+    return ui322float(ix);
 }
 
 static inline int fispo2(float x) {
-    ui32 ix=*(ui32*)&x;
+    ui32 ix=float2ui32(x);
     if(fiszero(x)) return 0;
     if(fisinf(x)) return 0;
     ix&=0x007fffff;
@@ -161,33 +175,33 @@ static inline float fnan_or(float x) {
 
 float WRAPPER_FUNC(truncf)(float x) {
     check_nan_f1(x);
-    ui32 ix=*(ui32*)&x,m;
+    ui32 ix=float2ui32(x),m;
     int e=fgetexp(x);
     e-=0x7f;                 // remove exponent bias
     if(e<0) {                // |x|<1
         ix&=0x80000000;
-        return *(float*)&ix;
+        return ui322float(ix);
     }
     e=23-e;                  // bit position in mantissa with significance 1
     if(e<=0) return x;       // |x| large, so must be an integer
     m=(1<<e)-1;              // mask for bits of significance <1
     ix&=~m;
-    return *(float*)&ix;
+    return ui322float(ix);
 }
 
 float WRAPPER_FUNC(roundf)(float x) {
     check_nan_f1(x);
-    ui32 ix=*(ui32*)&x,m;
+    ui32 ix=float2ui32(x),m;
     int e=fgetexp(x);
     e-=0x7f;                 // remove exponent bias
     if(e<-1) {               // |x|<0.5
         ix&=0x80000000;
-        return *(float*)&ix;
+        return ui322float(ix);
     }
     if(e==-1) {              // 0.5<=|x|<1
         ix&=0x80000000;
         ix|=0x3f800000;        // ±1
-        return *(float*)&ix;
+        return ui322float(ix);
     }
     e=23-e;                  // bit position in mantissa with significance 1, <=23
     if(e<=0) return x;       // |x| large, so must be an integer
@@ -195,16 +209,16 @@ float WRAPPER_FUNC(roundf)(float x) {
     ix+=m;
     m=m+m-1;                 // mask for bits of significance <1
     ix&=~m;
-    return *(float*)&ix;
+    return ui322float(ix);
 }
 
 float WRAPPER_FUNC(floorf)(float x) {
     check_nan_f1(x);
-    ui32 ix=*(ui32*)&x,m;
+    ui32 ix=float2ui32(x),m;
     int e=fgetexp(x);
     if(e==0) {       // x==0
         ix&=0x80000000;
-        return *(float*)&ix;
+        return ui322float(ix);
     }
     e-=0x7f;                 // remove exponent bias
     if(e<0) {                // |x|<1, not zero
@@ -216,16 +230,16 @@ float WRAPPER_FUNC(floorf)(float x) {
     m=(1<<e)-1;              // mask for bit of significance <1
     if(fisneg(x)) ix+=m;     // add 1-ε to magnitude if negative
     ix&=~m;                  // truncate
-    return *(float*)&ix;
+    return ui322float(ix);
 }
 
 float WRAPPER_FUNC(ceilf)(float x) {
     check_nan_f1(x);
-    ui32 ix=*(ui32*)&x,m;
+    ui32 ix=float2ui32(x),m;
     int e=fgetexp(x);
     if(e==0) {       // x==0
         ix&=0x80000000;
-        return *(float*)&ix;
+        return ui322float(ix);
     }
     e-=0x7f;                 // remove exponent bias
     if(e<0) {                // |x|<1, not zero
@@ -237,7 +251,7 @@ float WRAPPER_FUNC(ceilf)(float x) {
     m=(1<<e)-1;              // mask for bit of significance <1
     if(!fisneg(x)) ix+=m;    // add 1-ε to magnitude if positive
     ix&=~m;                  // truncate
-    return *(float*)&ix;
+    return ui322float(ix);
 }
 
 float WRAPPER_FUNC(asinf)(float x) {
@@ -505,7 +519,7 @@ static i32 frem_0(i32 mx,i32 my,int e,int*pquo) {
 
 float WRAPPER_FUNC(fmodf)(float x,float y) {
     check_nan_f2(x,y);
-    ui32 ix=*(ui32*)&x,iy=*(ui32*)&y;
+    ui32 ix=float2ui32(x),iy=float2ui32(y);
     int sx,ex,ey;
     i32 mx,my;
     FUNPACKS(ix,sx,ex,mx);
@@ -526,7 +540,7 @@ float WRAPPER_FUNC(fmodf)(float x,float y) {
 
 float WRAPPER_FUNC(remquof)(float x,float y,int*quo) {
     check_nan_f2(x,y);
-    ui32 ix=*(ui32*)&x,iy=*(ui32*)&y;
+    ui32 ix=float2ui32(x),iy=float2ui32(y);
     int sx,sy,ex,ey,q;
     i32 mx,my;
     FUNPACKS(ix,sx,ex,mx);
@@ -567,5 +581,4 @@ float WRAPPER_FUNC(dremf)(float x,float y) { check_nan_f2(x,y); return remquof(x
 
 float WRAPPER_FUNC(remainderf)(float x,float y) { check_nan_f2(x,y); return remquof(x,y,0); }
 
-_Pragma("GCC diagnostic pop") // strict-aliasing
 _Pragma("GCC diagnostic pop") // conversion
\ No newline at end of file
diff --git a/src/rp2_common/pico_float/float_v1_rom_shim.S b/src/rp2_common/pico_float/float_v1_rom_shim.S
index a29925ed3..d7541a4a3 100644
--- a/src/rp2_common/pico_float/float_v1_rom_shim.S
+++ b/src/rp2_common/pico_float/float_v1_rom_shim.S
@@ -6,7 +6,7 @@
 
 #include "pico/asm_helper.S"
 
-#if PICO_FLOAT_SUPPORT_ROM_V1
+#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
 .syntax unified
 .cpu cortex-m0plus
 .thumb
diff --git a/src/rp2_common/pico_mem_ops/mem_ops_aeabi.S b/src/rp2_common/pico_mem_ops/mem_ops_aeabi.S
index e07a9feee..854090533 100644
--- a/src/rp2_common/pico_mem_ops/mem_ops_aeabi.S
+++ b/src/rp2_common/pico_mem_ops/mem_ops_aeabi.S
@@ -9,6 +9,7 @@
 .thumb
 
 #include "pico/asm_helper.S"
+#include "pico/bootrom.h"
 
 __pre_init __aeabi_mem_init, 00001
 
@@ -34,10 +35,10 @@ __pre_init __aeabi_mem_init, 00001
 
 .align 2
 aeabi_mem_funcs:
-    .word rom_table_code('M','S')
-    .word rom_table_code('M','C')
-    .word rom_table_code('S','4')
-    .word rom_table_code('C','4')
+    .word ROM_FUNC_MEMSET
+    .word ROM_FUNC_MEMCPY
+    .word ROM_FUNC_MEMSET4
+    .word ROM_FUNC_MEMCPY44
 aeabi_mem_funcs_end:
 
 .section .text
@@ -58,20 +59,20 @@ regular_func __aeabi_mem_init
 mem_section aeabi_memset_memcpy
 
 wrapper_func __aeabi_memset
-    // args are backwards
-    eors r0, r1
-    eors r1, r0
-    eors r0, r1
+    // 2nd/3rd args are reversed
+    eors r2, r1
+    eors r1, r2
+    eors r2, r1
     ldr r3, =aeabi_mem_funcs
     ldr r3, [r3, #MEMSET]
     bx r3
 
 wrapper_func __aeabi_memset4
 wrapper_func __aeabi_memset8
-    // args are backwards
-    eors r0, r1
-    eors r1, r0
-    eors r0, r1
+    // 2nd/3rd args are reversed
+    eors r2, r1
+    eors r1, r2
+    eors r2, r1
     ldr r3, =aeabi_mem_funcs
     ldr r3, [r3, #MEMSET4]
     bx r3
diff --git a/src/rp2_common/pico_multicore/include/pico/multicore.h b/src/rp2_common/pico_multicore/include/pico/multicore.h
index 1c91a86ec..6f12f412b 100644
--- a/src/rp2_common/pico_multicore/include/pico/multicore.h
+++ b/src/rp2_common/pico_multicore/include/pico/multicore.h
@@ -17,7 +17,7 @@ extern "C" {
 
 /** \file multicore.h
  *  \defgroup pico_multicore pico_multicore
- * Adds support for running code on the second processor core (core1)
+ * Adds support for running code on the second processor core (core 1)
  *
  * \subsection multicore_example Example
  * \addtogroup pico_multicore
@@ -33,95 +33,155 @@ extern "C" {
 #endif
 #endif
 
-/*! \brief  Reset Core 1
+/*! \brief  Reset core 1
  *  \ingroup pico_multicore
  *
+ * This function can be used to reset core 1 into its initial state (ready for launching code against via \ref multicore_launch_core1 and similar methods)
+ *
+ * \note this function should only be called from core 0
  */
 void multicore_reset_core1(void);
 
 /*! \brief  Run code on core 1
  *  \ingroup pico_multicore
  *
- * Reset core1 and enter the given function on core 1 using the default core 1 stack (below core 0 stack)
+ * Wake up (a previously reset) core 1 and enter the given function on core 1 using the default core 1 stack (below core 0 stack).
+ *
+ * core 1 must previously have been reset either as a result of a system reset or by calling \ref multicore_reset_core1
  *
- * \param entry Function entry point, this function should not return.
+ * core 1 will use the same vector table as core 0
+ *
+ * \param entry Function entry point
+ * \see multicore_reset_core1
  */
 void multicore_launch_core1(void (*entry)(void));
 
 /*! \brief  Launch code on core 1 with stack
  *  \ingroup pico_multicore
  *
- * Reset core1 and enter the given function on core 1 using the passed stack for core 1
+ * Wake up (a previously reset) core 1 and enter the given function on core 1 using the passed stack for core 1
+ *
+ * core 1 must previously have been reset either as a result of a system reset or by calling \ref multicore_reset_core1
+ *
+ * core 1 will use the same vector table as core 0
+ *
+ * \param entry Function entry point
+ * \param stack_bottom The bottom (lowest address) of the stack
+ * \param stack_size_bytes The size of the stack in bytes (must be a multiple of 4)
+ * \see multicore_reset_core1
  */
 void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes);
 
 /*! \brief  Launch code on core 1 with no stack protection
  *  \ingroup pico_multicore
  *
- * Reset core1 and enter the given function using the passed sp as the initial stack pointer.
- * This is a bare bones functions that does not provide a stack guard even if USE_STACK_GUARDS is defined
+ * Wake up (a previously reset) core 1 and start it executing with a specific entry point, stack pointer
+ * and vector table.
+ *
+ * This is a low level function that does not provide a stack guard even if USE_STACK_GUARDS is defined
+ *
+ * core 1 must previously have been reset either as a result of a system reset or by calling \ref multicore_reset_core1
  *
+ * \param entry Function entry point
+ * \param sp Pointer to the top of the core 1 stack
+ * \param vector_table address of the vector table to use for core 1
+ * \see multicore_reset_core1
  */
 void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table);
 
 /*!
  * \defgroup multicore_fifo fifo
  * \ingroup pico_multicore
- * \brief Functions for inter-core FIFO
+ * \brief Functions for the inter-core FIFOs
  *
  * The RP2040 contains two FIFOs for passing data, messages or ordered events between the two cores. Each FIFO is 32 bits
  * wide, and 8 entries deep. One of the FIFOs can only be written by core 0, and read by core 1. The other can only be written
  * by core 1, and read by core 0.
+ *
+ * \note The inter-core FIFOs are a very precious resource and are frequently used for SDK functionality (e.g. during
+ * core 1 launch or by the \ref multicore_lockout functions). Additionally they are often required for the exclusive use
+ * of an RTOS (e.g. FreeRTOS SMP). For these reasons it is suggested that you do not use the FIFO for your own purposes
+ * unless none of the above concerns apply; the majority of cases for transferring data between cores can be eqaully
+ * well handled  by using a \ref queue
  */
 
-
-/*! \brief Check the read FIFO to see if there is data waiting
+/*! \brief Check the read FIFO to see if there is data available (sent by the other core)
  *  \ingroup multicore_fifo
  *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
  * \return true if the FIFO has data in it, false otherwise
  */
 static inline bool multicore_fifo_rvalid(void) {
     return !!(sio_hw->fifo_st & SIO_FIFO_ST_VLD_BITS);
 }
 
-/*! \brief Check the write FIFO to see if it is ready for more data
+/*! \brief Check the write FIFO to see if it has space for more data
  *  \ingroup multicore_fifo
  *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
  *  @return true if the FIFO has room for more data, false otherwise
  */
 static inline bool multicore_fifo_wready(void) {
     return !!(sio_hw->fifo_st & SIO_FIFO_ST_RDY_BITS);
 }
 
-/*! \brief Push data on to the FIFO.
+/*! \brief Push data on to the write FIFO (data to the other core).
  *  \ingroup multicore_fifo
  *
  * This function will block until there is space for the data to be sent.
  * Use multicore_fifo_wready() to check if it is possible to write to the
  * FIFO if you don't want to block.
  *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
  * \param data A 32 bit value to push on to the FIFO
  */
 void multicore_fifo_push_blocking(uint32_t data);
 
+/*! \brief Push data on to the write FIFO (data to the other core) with timeout.
+ *  \ingroup multicore_fifo
+ *
+ * This function will block until there is space for the data to be sent
+ * or the timeout is reached
+ *
+ * \param data A 32 bit value to push on to the FIFO
+ * \param timeout_us the timeout in microseconds
+ * \return true if the data was pushed, false if the timeout occurred before data could be pushed
+ */
 bool multicore_fifo_push_timeout_us(uint32_t data, uint64_t timeout_us);
 
-/*! \brief Pop data from the FIFO.
+/*! \brief Pop data from the read FIFO (data from the other core).
  *  \ingroup multicore_fifo
  *
  * This function will block until there is data ready to be read
  * Use multicore_fifo_rvalid() to check if data is ready to be read if you don't
  * want to block.
  *
- * \return 32 bit unsigned data from the FIFO.
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
+ * \return 32 bit data from the read FIFO.
  */
 uint32_t multicore_fifo_pop_blocking(void);
 
+/*! \brief Pop data from the read FIFO (data from the other core) with timeout.
+ *  \ingroup multicore_fifo
+ *
+ * This function will block until there is data ready to be read or the timeout is reached
+ *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
+ * \param timeout_us the timeout in microseconds
+ * \param out the location to store the popped data if available
+ * \return true if the data was popped and a value copied into `out`, false if the timeout occurred before data could be popped
+ */
 bool multicore_fifo_pop_timeout_us(uint64_t timeout_us, uint32_t *out);
 
-/*! \brief Flush any data in the incoming FIFO
+/*! \brief Discard any data in the read FIFO
  *  \ingroup multicore_fifo
  *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
  */
 static inline void multicore_fifo_drain(void) {
     while (multicore_fifo_rvalid())
@@ -133,38 +193,117 @@ static inline void multicore_fifo_drain(void) {
  *
  * Note that this only clears an interrupt that was caused by the ROE or WOF flags.
  * To clear the VLD flag you need to use one of the 'pop' or 'drain' functions.
+ *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
+ * \see multicore_fifo_get_status
 */
 static inline void multicore_fifo_clear_irq(void) {
     // Write any value to clear the error flags
     sio_hw->fifo_st = 0xff;
 }
 
-/*! \brief Get FIFO status
+/*! \brief Get FIFO statuses
  *  \ingroup multicore_fifo
  *
- * \return The status as a bitfield
+ * \return The statuses as a bitfield
  *
  * Bit | Description
  * ----|------------
- * 3 | Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.
- * 2 | Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.
+ * 3 | Sticky flag indicating the RX FIFO was read when empty (ROE). This read was ignored by the FIFO.
+ * 2 | Sticky flag indicating the TX FIFO was written when full (WOF). This write was ignored by the FIFO.
  * 1 | Value is 1 if this core’s TX FIFO is not full (i.e. if FIFO_WR is ready for more data)
  * 0 | Value is 1 if this core’s RX FIFO is not empty (i.e. if FIFO_RD is valid)
+ *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
 */
 static inline uint32_t multicore_fifo_get_status(void) {
     return sio_hw->fifo_st;
 }
 
-// call this from the lockout victim thread
+/*!
+ * \defgroup multicore_lockout lockout
+ * \ingroup pico_multicore
+ * \brief Functions to enable one core to force the other core to pause execution in a known state.
+ *
+ * Sometimes it is useful to enter a critical section on both cores at once. On a single
+ * core system a critical section can trivially be entered by disabling interrupts, however on a multi-core
+ * system that is not sufficient, and unless the other core is polling in some way, then it will need to be interrupted
+ * in order to cooperatively enter a blocked state.
+ *
+ * These "lockout" functions use the inter core FIFOs to cause an interrupt on one core from the other, and manage
+ * waiting for the other core to enter the "locked out" state.
+ *
+ * The usage is that the "victim" core ... i.e the core that can be "locked out" by the other core calls
+ * \ref multicore_lockout_victim_init to hook the FIFO interrupt. Note that either or both cores may do this.
+ *
+ * \note When "locked out" the victim core is paused (it is actually executing a tight loop with code in RAM) and has interrupts disabled.
+ * This makes the lockout functions suitable for use by code that wants to write to flash (at which point no code may be executing
+ * from flash)
+ *
+ * The core which wishes to lockout the other core calls \ref multicore_lockout_start_blocking or
+ * \ref multicore_lockout_start_timeout_us to interrupt the other "victim" core and wait for it to be in a
+ * "locked out" state. Once the lockout is no longer needed it calls \ref multicore_lockout_end_blocking or
+ * \ref multicore_lockout_end_timeout_us to release the lockout and wait for confirmation.
+ *
+ * \note Because multicore lockout uses the intercore FIFOs, the FIFOs <b>cannot</b> be used for any other purpose
+ */
+
+/*! \brief Initialize the current core such that it can be a "victim" of lockout (i.e. forced to pause in a known state by the other core)
+ *  \ingroup multicore_lockout
+ *
+ * This code hooks the intercore FIFO IRQ, and the FIFO may not be used for any other purpose after this.
+ */
 void multicore_lockout_victim_init(void);
 
-// start locking out the other core (it will be
-bool multicore_lockout_start_timeout_us(uint64_t timeout_us);
+/*! \brief Request the other core to pause in a known state and wait for it to do so
+ *  \ingroup multicore_lockout
+ *
+ * The other (victim) core must have previously executed \ref multicore_lockout_victim_init()
+ *
+ * \note multicore_lockout_start_ functions are not nestable, and must be paired with a call to a corresponding
+ * \ref multicore_lockout_end_blocking
+ */
 void multicore_lockout_start_blocking(void);
 
-bool multicore_lockout_end_timeout_us(uint64_t timeout_us);
+/*! \brief Request the other core to pause in a known state and wait up to a time limit for it to do so
+ *  \ingroup multicore_lockout
+ *
+ * The other core must have previously executed \ref multicore_lockout_victim_init()
+ *
+ * \note multicore_lockout_start_ functions are not nestable, and must be paired with a call to a corresponding
+ * \ref multicore_lockout_end_blocking
+ *
+ * \param timeout_us the timeout in microseconds
+ * \return true if the other core entered the locked out state within the timeout, false otherwise
+ */
+bool multicore_lockout_start_timeout_us(uint64_t timeout_us);
+
+/*! \brief Release the other core from a locked out state amd wait for it to acknowledge
+ *  \ingroup multicore_lockout
+ *
+ * \note The other core must previously have been "locked out" by calling a `multicore_lockout_start_` function
+ * from this core
+ */
 void multicore_lockout_end_blocking(void);
 
+/*! \brief Release the other core from a locked out state amd wait up to a time limit for it to acknowledge
+ *  \ingroup multicore_lockout
+ *
+ * The other core must previously have been "locked out" by calling a `multicore_lockout_start_` function
+ * from this core
+ *
+ * \note be very careful using small timeout values, as a timeout here will leave the "lockout" functionality
+ * in a bad state. It is probably preferable to use \ref multicore_lockout_end_blocking anyway as if you have
+ * already waited for the victim core to enter the lockout state, then the victim core will be ready to exit
+ * the lockout state very quickly.
+ *
+ * \param timeout_us the timeout in microseconds
+ * \return true if the other core successfully exited locked out state within the timeout, false otherwise
+ */
+bool multicore_lockout_end_timeout_us(uint64_t timeout_us);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/rp2_common/pico_multicore/multicore.c b/src/rp2_common/pico_multicore/multicore.c
index 531e294a1..121b4fbfc 100644
--- a/src/rp2_common/pico_multicore/multicore.c
+++ b/src/rp2_common/pico_multicore/multicore.c
@@ -126,22 +126,32 @@ void multicore_launch_core1(void (*entry)(void)) {
 }
 
 void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table) {
-    const uint32_t cmd_sequence[] = {0, 0, 1, (uintptr_t) vector_table, (uintptr_t) sp, (uintptr_t) entry};
-
+    // Allow for the fact that the caller may have already enabled the FIFO IRQ for their
+    // own purposes (expecting FIFO content after core 1 is launched). We must disable
+    // the IRQ during the handshake, then restore afterwards.
     bool enabled = irq_is_enabled(SIO_IRQ_PROC0);
     irq_set_enabled(SIO_IRQ_PROC0, false);
 
+    // Values to be sent in order over the FIFO from core 0 to core 1
+    //
+    // vector_table is value for VTOR register
+    // sp is initial stack pointer (SP)
+    // entry is the initial program counter (PC) (don't forget to set the thumb bit!)
+    const uint32_t cmd_sequence[] =
+            {0, 0, 1, (uintptr_t) vector_table, (uintptr_t) sp, (uintptr_t) entry};
+
     uint seq = 0;
     do {
         uint cmd = cmd_sequence[seq];
-        // we drain before sending a 0
+        // Always drain the READ FIFO (from core 1) before sending a 0
         if (!cmd) {
             multicore_fifo_drain();
-            __sev(); // core 1 may be waiting for fifo space
+            // Execute a SEV as core 1 may be waiting for FIFO space via WFE
+            __sev();
         }
         multicore_fifo_push_blocking(cmd);
         uint32_t response = multicore_fifo_pop_blocking();
-        // move to next state on correct response otherwise start over
+        // Move to next state on correct response (echo-d value) otherwise start over
         seq = cmd == response ? seq + 1 : 0;
     } while (seq < count_of(cmd_sequence));
 
@@ -176,7 +186,7 @@ static void __isr __not_in_flash_func(multicore_lockout_handler)(void) {
 static void check_lockout_mutex_init(void) {
     // use known available lock - we only need it briefly
     uint32_t save = hw_claim_lock();
-    if (!mutex_is_initialzed(&lockout_mutex)) {
+    if (!mutex_is_initialized(&lockout_mutex)) {
         mutex_init(&lockout_mutex);
     }
     hw_claim_unlock(save);
@@ -237,7 +247,7 @@ void multicore_lockout_start_blocking() {
 }
 
 static bool multicore_lockout_end_block_until(absolute_time_t until) {
-    assert(mutex_is_initialzed(&lockout_mutex));
+    assert(mutex_is_initialized(&lockout_mutex));
     if (!mutex_enter_block_until(&lockout_mutex, until)) {
         return false;
     }
diff --git a/src/rp2_common/pico_platform/include/pico/asm_helper.S b/src/rp2_common/pico_platform/include/pico/asm_helper.S
index 050e6a5fb..3e01c665a 100644
--- a/src/rp2_common/pico_platform/include/pico/asm_helper.S
+++ b/src/rp2_common/pico_platform/include/pico/asm_helper.S
@@ -4,13 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include "hardware/platform_defs.h"
-#include "pico/config.h"
-
-#define WRAPPER_FUNC_NAME(x) __wrap_##x
-#define SECTION_NAME(x) .text.##x
-#define RAM_SECTION_NAME(x) .time_critical.##x
-#define rom_table_code(c1, c2) ((c1) | ((c2) << 8))
+#include "pico.h"
 
 // do not put align in here as it is used mid function sometimes
 .macro regular_func x
diff --git a/src/rp2_common/pico_platform/include/pico/platform.h b/src/rp2_common/pico_platform/include/pico/platform.h
index c008b9509..ee1d360ce 100644
--- a/src/rp2_common/pico_platform/include/pico/platform.h
+++ b/src/rp2_common/pico_platform/include/pico/platform.h
@@ -7,91 +7,304 @@
 #ifndef _PICO_PLATFORM_H_
 #define _PICO_PLATFORM_H_
 
+/** \file platform.h
+ *  \defgroup pico_platform pico_platform
+ *
+ * Macros and definitions (and functions when included by non assembly code) for the RP2 family device / architecture
+ * to provide a common abstraction over low level compiler / platform specifics.
+ *
+ * This header may be included by assembly code
+ */
+
+#include "hardware/platform_defs.h"
+
+// Marker for builds targeting the RP2040
+#define PICO_RP2040 1
+
+// PICO_CONFIG: PICO_STACK_SIZE, Stack Size, min=0x100, default=0x800, advanced=true, group=pico_platform
+#ifndef PICO_STACK_SIZE
+#define PICO_STACK_SIZE _u(0x800)
+#endif
+
+// PICO_CONFIG: PICO_HEAP_SIZE, Heap size to reserve, min=0x100, default=0x800, advanced=true, group=pico_platform
+#ifndef PICO_HEAP_SIZE
+#define PICO_HEAP_SIZE _u(0x800)
+#endif
+
+// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_platform
+#ifndef PICO_NO_RAM_VECTOR_TABLE
+#define PICO_NO_RAM_VECTOR_TABLE 0
+#endif
+
+// PICO_CONFIG: PICO_RP2040_B0_SUPPORTED, Whether to include any specific software support for RP2040 B0 revision, type=bool, default=1, advanced=true, group=pico_platform
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 1
+#endif
+
+// PICO_CONFIG: PICO_FLOAT_SUPPORT_ROM_V1, Include float support code for RP2040 B0 when that chip revision is supported , type=bool, default=1, advanced=true, group=pico_platform
+#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#define PICO_FLOAT_SUPPORT_ROM_V1 1
+#endif
+
+// PICO_CONFIG: PICO_DOUBLE_SUPPORT_ROM_V1, Include double support code for RP2040 B0 when that chip revision is supported , type=bool, default=1, advanced=true, group=pico_platform
+#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
+#define PICO_DOUBLE_SUPPORT_ROM_V1 1
+#endif
+
+
+// PICO_CONFIG: PICO_RP2040_B1_SUPPORTED, Whether to include any specific software support for RP2040 B1 revision, type=bool, default=1, advanced=true, group=pico_platform
+#ifndef PICO_RP2040_B1_SUPPORTED
+#define PICO_RP2040_B1_SUPPORTED 1
+#endif
+
+// PICO_CONFIG: PICO_RP2040_B2_SUPPORTED, Whether to include any specific software support for RP2040 B2 revision, type=bool, default=1, advanced=true, group=pico_platform
+#ifndef PICO_RP2040_B2_SUPPORTED
+#define PICO_RP2040_B2_SUPPORTED 1
+#endif
+
+// --- remainder of file is not included by assembly code ---
+
+#ifndef __ASSEMBLER__
+
 #include <sys/cdefs.h>
 #include "pico/types.h"
-#include "hardware/platform_defs.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/** \file platform.h
-*  \defgroup pico_platform pico_platform
-* Compiler definitions for the selected PICO_PLATFORM
-*/
-
+/*! \brief Marker for an interrupt handler
+ *  \ingroup pico_platform
+ * For example an IRQ handler function called my_interrupt_handler:
+ *
+ *     void __isr my_interrupt_handler(void) {
+ */
 #define __isr
 
-// Section naming macros
+/*! \brief Section attribute macro for placement in RAM after the `.data` section
+ *  \ingroup pico_platform
+ *
+ * For example a 400 element `uint32_t` array placed after the .data section
+ *
+ *     uint32_t __after_data("my_group_name") a_big_array[400];
+ *
+ * The section attribute is `.after_data.<group>`
+ *
+ * \param group a string suffix to use in the section name to distinguish groups that can be linker
+ *              garbage-collected independently
+ */
 #define __after_data(group) __attribute__((section(".after_data." group)))
+
+/*! \brief Section attribute macro for placement not in flash (i.e in RAM)
+ *  \ingroup pico_platform
+ *
+ * For example a 3 element `uint32_t` array placed in RAM (even though it is `static const`)
+ *
+ *     static const uint32_t __not_in_flash("my_group_name") an_array[3];
+ *
+ * The section attribute is `.time_critical.<group>`
+ *
+ * \param group a string suffix to use in the section name to distinguish groups that can be linker
+ *              garbage-collected independently
+ */
 #define __not_in_flash(group) __attribute__((section(".time_critical." group)))
+
+/*! \brief Section attribute macro for placement in the SRAM bank 4 (known as "scratch X")
+ *  \ingroup pico_platform
+ *
+ * Scratch X is commonly used for critical data and functions accessed only by one core (when only
+ * one core is accessing the RAM bank, there is no opportunity for stalls)
+ *
+ * For example a `uint32_t` variable placed in "scratch X"
+ *
+ *     uint32_t __scratch_x("my_group_name") foo = 23;
+ *
+ * The section attribute is `.scratch_x.<group>`
+ *
+ * \param group a string suffix to use in the section name to distinguish groups that can be linker
+ *              garbage-collected independently
+ */
 #define __scratch_x(group) __attribute__((section(".scratch_x." group)))
+
+/*! \brief Section attribute macro for placement in the SRAM bank 5 (known as "scratch Y")
+ *  \ingroup pico_platform
+ *
+ * Scratch Y is commonly used for critical data and functions accessed only by one core (when only
+ * one core is accessing the RAM bank, there is no opportunity for stalls)
+ *
+ * For example a `uint32_t` variable placed in "scratch Y"
+ *
+ *     uint32_t __scratch_y("my_group_name") foo = 23;
+ *
+ * The section attribute is `.scratch_y.<group>`
+ *
+ * \param group a string suffix to use in the section name to distinguish groups that can be linker
+ *              garbage-collected independently
+ */
 #define __scratch_y(group) __attribute__((section(".scratch_y." group)))
+
+/*! \brief Section attribute macro for data that is to be left uninitialized
+ *  \ingroup pico_platform
+ *
+ * Data marked this way will retain its value across a reset (normally uninitialized data - in the .bss
+ * section) is initialized to zero during runtime initialization
+ *
+ * For example a `uint32_t` foo that will retain its value if the program is restarted by reset.
+ *
+ *     uint32_t __uninitialized_ram("my_group_name") foo;
+ *
+ * The section attribute is `.uninitialized_ram.<group>`
+ *
+ * \param group a string suffix to use in the section name to distinguish groups that can be linker
+ *              garbage-collected independently
+ */
 #define __uninitialized_ram(group) __attribute__((section(".uninitialized_ram." #group))) group
-// For use with PICO_COPY_TO_RAM:
+
+/*! \brief Section attribute macro for placement in flash even in a COPY_TO_RAM binary
+ *  \ingroup pico_platform
+ *
+ * For example a `uint32_t` variable explicitly placed in flash (it will hard fault if you attempt to write it!)
+ *
+ *     uint32_t __in_flash("my_group_name") foo = 23;
+ *
+ * The section attribute is `.flashdata.<group>`
+ *
+ * \param group a string suffix to use in the section name to distinguish groups that can be linker
+ *              garbage-collected independently
+ */
 #define __in_flash(group) __attribute__((section(".flashdata" group)))
 
-/**
+/*! \brief Indicates a function should not be stored in flash
+ *  \ingroup pico_platform
+ *
  * Decorates a function name, such that the function will execute from RAM (assuming it is not inlined
  * into a flash function by the compiler)
+ *
+ * For example a function called my_func taking an int parameter:
+ *
+ *     void __not_in_flash_func(my_func)(int some_arg) {
+ *
+ * The function is placed in the `.time_critical.<func_name>` linker section
+ *
+ * \see __no_inline_not_in_flash_func
  */
 #define __not_in_flash_func(func_name) __not_in_flash(__STRING(func_name)) func_name
-/**
- * Historical synonym for __not_in_flash_func()
+
+/*! \brief Indicates a function is time/latency critical and should not run from flash
+ *  \ingroup pico_platform
+ *
+ * Decorates a function name, such that the function will execute from RAM (assuming it is not inlined
+ * into a flash function by the compiler) to avoid possible flash latency. Currently this macro is identical
+ * in implementation to `__not_in_flash_func`, however the semantics are distinct and a `__time_critical_func`
+ * may in the future be treated more specially to reduce the overhead when calling such function from a flash
+ * function.
+ *
+ * For example a function called my_func taking an int parameter:
+ *
+ *     void __time_critical(my_func)(int some_arg) {
+ *
+ * The function is placed in the `.time_critical.<func_name>` linker section
+ *
+ * \see __not_in_flash_func
  */
 #define __time_critical_func(func_name) __not_in_flash_func(func_name)
 
-/**
+/*! \brief Indicate a function should not be stored in flash and should not be inlined
+ *  \ingroup pico_platform
+ *
  * Decorates a function name, such that the function will execute from RAM, explicitly marking it as
  * noinline to prevent it being inlined into a flash function by the compiler
+ *
+ * For example a function called my_func taking an int parameter:
+ *
+ *     void __no_inline_not_in_flash_func(my_func)(int some_arg) {
+ *
+ * The function is placed in the `.time_critical.<func_name>` linker section
  */
 #define __no_inline_not_in_flash_func(func_name) __noinline __not_in_flash_func(func_name)
 
 #define __packed_aligned __packed __aligned(4)
 
-#if defined(__GNUC__) && __GNUC__ < 7
+/*! \brief Attribute to force inlining of a function regardless of optimization level
+ *  \ingroup pico_platform
+ *
+ *  For example my_function here will always be inlined:
+ *
+ *      int __force_inline my_function(int x) {
+ *
+ */
+#if defined(__GNUC__) && __GNUC__ <= 7
 #define __force_inline inline __always_inline
 #else
 #define __force_inline __always_inline
 #endif
+
+/*! \brief Macro to determine the number of elements in an array
+ *  \ingroup pico_platform
+ */
 #ifndef count_of
 #define count_of(a) (sizeof(a)/sizeof((a)[0]))
 #endif
 
+/*! \brief Macro to return the maximum of two comparable values
+ *  \ingroup pico_platform
+ */
 #ifndef MAX
 #define MAX(a, b) ((a)>(b)?(a):(b))
 #endif
 
+/*! \brief Macro to return the minimum of two comparable values
+ *  \ingroup pico_platform
+ */
 #ifndef MIN
 #define MIN(a, b) ((b)>(a)?(a):(b))
 #endif
 
-/**
- * Execute a breakpoint instruction
+/*! \brief Execute a breakpoint instruction
+ *  \ingroup pico_platform
  */
 static inline void __breakpoint(void) {
     __asm__("bkpt #0");
 }
 
-/**
- * Ensure that the compiler does not move memory access across this method call
+/*! \brief Ensure that the compiler does not move memory access across this method call
+ *  \ingroup pico_platform
+ *
+ *  For example in the following code:
+ *
+ *      *some_memory_location = var_a;
+ *      __compiler_memory_barrier();
+ *      uint32_t var_b = *some_other_memory_location
+ *
+ * The compiler will not move the load from `some_other_memory_location` above the memory barrier (which it otherwise
+ * might - even above the memory store!)
  */
 __force_inline static void __compiler_memory_barrier(void) {
     __asm__ volatile ("" : : : "memory");
 }
 
-// return a 32 bit handle for a raw ptr; DMA chaining for example embeds pointers in 32 bit values
-// which of course does not work if we're running the code natively on a 64 bit platforms. Therefore
-// we provide this macro which allows that code to provide a 64->32 bit mapping in host mode
+/*! \brief Macro for converting memory addresses to 32 bit addresses suitable for DMA
+ *  \ingroup pico_platform
+ *
+ *  This is just a cast to `uintptr_t` on the RP2040, however you may want to use this when developing code
+ *  that also runs in "host" mode. If the host mode is 64 bit and you are embedding data pointers
+ *  in other data (e.g. DMA chaining), then there is a need in "host" mode to convert a 64 bit native
+ *  pointer to a 32 bit value for storage, which can be done using this macro.
+ */
 #define host_safe_hw_ptr(x) ((uintptr_t)(x))
+#define native_safe_hw_ptr(x) host_safe_hw_ptr(x)
+
 
-/**
- * Panic (see panic()) with the message "Unsupported".
+/*! \brief Panics with the message "Unsupported"
+ *  \ingroup pico_platform
+ *  \see panic
  */
 void __attribute__((noreturn)) panic_unsupported(void);
 
-/**
- * Panic with a message. An attempt is made to output the message to all registered STDOUT drivers
+/*! \brief Displays a panic message and halts execution
+ *  \ingroup pico_platform
+ *
+ * An attempt is made to output the message to all registered STDOUT drivers
  * after which this method executes a BKPT instruction.
  *
  * @param fmt format string (printf-like)
@@ -110,36 +323,34 @@ static inline bool running_on_fpga(void) {return false;}
 bool running_on_fpga(void);
 #endif
 
-/**
- * @return the RP2040 chip revision number
+/*! \brief Returns the RP2040 chip revision number
+ *  \ingroup pico_platform
+ * @return the RP2040 chip revision number (1 for B0/B1, 2 for B2)
  */
 uint8_t rp2040_chip_version(void);
 
-/**
- * @return the RP2040 rom version number
+/*! \brief Returns the RP2040 rom version number
+ *  \ingroup pico_platform
+ * @return the RP2040 rom version number (1 for RP2040-B0, 2 for RP2040-B1, 3 for RP2040-B2)
  */
 static inline uint8_t rp2040_rom_version(void) {
     return *(uint8_t*)0x13;
 }
 
-/**
- * Empty function intended to be called by any tight hardware polling loop. using this ubiquitously
+/*! \brief No-op function for the body of tight loops
+ *  \ingroup pico_platform
+ *
+ * Np-op function intended to be called by any tight hardware polling loop. Using this ubiquitously
  * makes it much easier to find tight loops, but also in the future \#ifdef-ed support for lockup
  * debugging might be added
  */
-static inline void tight_loop_contents(void) {}
+static __force_inline void tight_loop_contents(void) {}
 
-/**
- * Helper macro for making chain DMA code portable to PICO_PLATFORM=host. The problem here is
- * that embedded pointers in the data are only 32 bit, which is a problem if the host
- * system is 64 bit. This macro is zero cost on the actual device, but in host mode
- * it provides a 64->32 bit mapping
- */
-#define native_safe_hw_ptr(x) ((uintptr_t)(x))
-
-/**
- * Multiplies a by b using multiply instruction using the ARM mul instruction regardless of values;
- * i.e. this is a 1 cycle operation.
+/*! \brief Multiply two integers using an assembly `MUL` instruction
+ *  \ingroup pico_platform
+ *
+ * This multiplies a by b using multiply instruction using the ARM mul instruction regardless of values (the compiler
+ * might otherwise choose to perform shifts/adds), i.e. this is a 1 cycle operation.
  *
  * \param a the first operand
  * \param b the second operand
@@ -150,10 +361,14 @@ __force_inline static int32_t __mul_instruction(int32_t a, int32_t b) {
     return a;
 }
 
-/**
- * Efficiently Multiplies value a by possibly constant value b.
+/*! \brief multiply two integer values using the fastest method possible
+ *  \ingroup pico_platform
+ *
+ * Efficiently multiplies value a by possibly constant value b.
+ *
  * If b is known to be constant and not zero or a power of 2, then a mul instruction is used rather than gcc's default
- * which is often a slow combination of shifts and adds
+ * which is often a slow combination of shifts and adds. If b is a power of 2 then a single shift is of course preferable
+ * and will be used
  *
  * \param a the first operand
  * \param b the second operand
@@ -163,18 +378,34 @@ __force_inline static int32_t __mul_instruction(int32_t a, int32_t b) {
 (__builtin_popcount(b) >= 2 ? __mul_instruction(a,b) : (a)*(b)), \
 (a)*(b))
 
-#define WRAPPER_FUNC(x) __wrap_ ## x
-#define REAL_FUNC(x) __real_ ## x
-
+/*! \brief Utility macro to assert two types are equivalent.
+ *  \ingroup pico_platform
+ *
+ *  This macro can be useful in other macros along with `typeof` to assert that two parameters are of equivalent type
+ *  (or that a single parameter is of an expected type)
+ */
 #define __check_type_compatible(type_a, type_b) static_assert(__builtin_types_compatible_p(type_a, type_b), __STRING(type_a) " is not compatible with " __STRING(type_b));
 
-/**
- * Get the current exception level on this core
+/*! \brief Get the current exception level on this core
+ *  \ingroup pico_platform
+ *
  * \return the exception number if the CPU is handling an exception, or 0 otherwise
  */
 uint __get_current_exception(void);
 
+#define WRAPPER_FUNC(x) __wrap_ ## x
+#define REAL_FUNC(x) __real_ ## x
+
 #ifdef __cplusplus
 }
 #endif
+
+#else // __ASSEMBLER__
+
+#define WRAPPER_FUNC_NAME(x) __wrap_##x
+#define SECTION_NAME(x) .text.##x
+#define RAM_SECTION_NAME(x) .time_critical.##x
+
+#endif // !__ASSEMBLER__
+
 #endif
diff --git a/src/rp2_common/pico_runtime/runtime.c b/src/rp2_common/pico_runtime/runtime.c
index 662893402..575e23e08 100644
--- a/src/rp2_common/pico_runtime/runtime.c
+++ b/src/rp2_common/pico_runtime/runtime.c
@@ -20,16 +20,18 @@
 
 #include "pico/mutex.h"
 #include "pico/time.h"
+
+#if LIB_PICO_PRINTF_PICO
 #include "pico/printf.h"
+#else
+#define weak_raw_printf printf
+#define weak_raw_vprintf vprintf
+#endif
 
 #if PICO_ENTER_USB_BOOT_ON_EXIT
 #include "pico/bootrom.h"
 #endif
 
-#ifndef PICO_NO_RAM_VECTOR_TABLE
-#define PICO_NO_RAM_VECTOR_TABLE 0
-#endif
-
 extern char __StackLimit; /* Set by linker.  */
 
 uint32_t __attribute__((section(".ram_vector_table"))) ram_vector_table[48];
@@ -113,15 +115,27 @@ void runtime_init(void) {
             hw_clear_alias(padsbank0_hw)->io[28] = hw_clear_alias(padsbank0_hw)->io[29] = PADS_BANK0_GPIO0_IE_BITS;
 #endif
 
-    extern mutex_t __mutex_array_start;
-    extern mutex_t __mutex_array_end;
-
-    // the first function pointer, not the address of it.
-    for (mutex_t *m = &__mutex_array_start; m < &__mutex_array_end; m++) {
-        if (m->recursion_state) {
-            recursive_mutex_init(m);
+    // this is an array of either mutex_t or recursive_mutex_t (i.e. not necessarily the same size)
+    // however each starts with a lock_core_t, and the spin_lock is initialized to address 1 for a recursive
+    // spinlock and 0 for a regular one.
+
+    static_assert(!(sizeof(mutex_t)&3), "");
+    static_assert(!(sizeof(recursive_mutex_t)&3), "");
+    static_assert(!offsetof(mutex_t, core), "");
+    static_assert(!offsetof(recursive_mutex_t, core), "");
+    extern lock_core_t __mutex_array_start;
+    extern lock_core_t __mutex_array_end;
+
+    for (lock_core_t *l = &__mutex_array_start; l < &__mutex_array_end; ) {
+        if (l->spin_lock) {
+            assert(1 == (uintptr_t)l->spin_lock); // indicator for a recursive mutex
+            recursive_mutex_t *rm = (recursive_mutex_t *)l;
+            recursive_mutex_init(rm);
+            l = &rm[1].core; // next
         } else {
+            mutex_t *m = (mutex_t *)l;
             mutex_init(m);
+            l = &m[1].core; // next
         }
     }
 
@@ -230,7 +244,7 @@ extern void __attribute__((noreturn)) __printflike(1, 0) PICO_PANIC_FUNCTION(__u
 // Use a forwarding method here as it is a little simpler than renaming the symbol as it is used from assembler
 void __attribute__((naked, noreturn)) __printflike(1, 0) panic(__unused const char *fmt, ...) {
     // if you get an undefined reference here, you didn't define your PICO_PANIC_FUNCTION!
-    asm (
+    __asm (
             "push {lr}\n"
 #if !PICO_PANIC_FUNCTION_EMPTY
             "bl " __XSTRING(PICO_PANIC_FUNCTION) "\n"
diff --git a/src/rp2_common/pico_standard_link/CMakeLists.txt b/src/rp2_common/pico_standard_link/CMakeLists.txt
index 78de372c7..a7305403c 100644
--- a/src/rp2_common/pico_standard_link/CMakeLists.txt
+++ b/src/rp2_common/pico_standard_link/CMakeLists.txt
@@ -79,6 +79,10 @@ if (NOT TARGET pico_standard_link)
     # boot_stage2 will be linked if PICO_NO_FLASH would be defined to 0
     target_link_libraries(pico_standard_link INTERFACE $<$<NOT:$<IF:$<STREQUAL:$<TARGET_PROPERTY:PICO_TARGET_BINARY_TYPE>,no_flash>,1,$<AND:$<BOOL:${PICO_NO_FLASH}>,$<STREQUAL:,$<TARGET_PROPERTY:PICO_TARGET_BINARY_TYPE>>>>>:$<IF:$<BOOL:$<TARGET_PROPERTY:PICO_TARGET_BOOT_STAGE2>>,$<TARGET_PROPERTY:PICO_TARGET_BOOT_STAGE2>,bs2_default>_library>)
 
+    # PICO_CMAKE_CONFIG: PICO_USE_DEFAULT_MAX_PAGE_SIZE, Don't shrink linker max page to 4096, type=bool, default=0, advanced=true, group=pico_standard_link
+    if (NOT PICO_USE_DEFAULT_MAX_PAGE_SIZE)
+        target_link_options(pico_standard_link INTERFACE "LINKER:-z,max-page-size=4096")
+    endif()
     # done in compiler now
     #target_link_options(pico_standard_link INTERFACE "LINKER:--build-id=none")
 
diff --git a/src/rp2_common/pico_standard_link/crt0.S b/src/rp2_common/pico_standard_link/crt0.S
index 4134f0b23..f57ddfdef 100644
--- a/src/rp2_common/pico_standard_link/crt0.S
+++ b/src/rp2_common/pico_standard_link/crt0.S
@@ -4,12 +4,11 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include "pico.h"
 #include "hardware/regs/m0plus.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/addressmap.h"
 #include "hardware/regs/sio.h"
 #include "pico/binary_info/defs.h"
-#include "pico/config.h"
 
 #ifdef NDEBUG
 #ifndef COLLAPSE_IRQS
diff --git a/src/rp2_common/pico_stdio/include/pico/stdio.h b/src/rp2_common/pico_stdio/include/pico/stdio.h
index 9f01ae95f..e44c01d05 100644
--- a/src/rp2_common/pico_stdio/include/pico/stdio.h
+++ b/src/rp2_common/pico_stdio/include/pico/stdio.h
@@ -49,6 +49,9 @@ typedef struct stdio_driver stdio_driver_t;
  * Call this method once you have set up your clocks to enable the stdio support for UART, USB
  * and semihosting based on the presence of the respective libraries in the binary.
  *
+ * When stdio_usb is configured, this method can be optionally made to block, waiting for a connection
+ * via the variables specified in \ref stdio_usb_init (i.e. \ref PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS)
+ *
  * \see stdio_uart, stdio_usb, stdio_semihosting
  */
 void stdio_init_all(void);
@@ -74,7 +77,7 @@ int getchar_timeout_us(uint32_t timeout_us);
 /*! \brief Adds or removes a driver from the list of active drivers used for input/output
  * \ingroup pico_stdio
  *
- * \note this method should always be called on an initialized driver
+ * \note this method should always be called on an initialized driver and is not re-entrant
  * \param driver the driver
  * \param enabled true to add, false to remove
  */
@@ -100,6 +103,16 @@ void stdio_filter_driver(stdio_driver_t *driver);
  */
 void stdio_set_translate_crlf(stdio_driver_t *driver, bool translate);
 
+/*! \brief putchar variant that skips any CR/LF conversion if enabled
+ * \ingroup pico_stdio
+ */
+int putchar_raw(int c);
+
+/*! \brief puts variant that skips any CR/LF conversion if enabled
+ * \ingroup pico_stdio
+ */
+int puts_raw(const char *s);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/rp2_common/pico_stdio/stdio.c b/src/rp2_common/pico_stdio/stdio.c
index 4f520ca24..b457b8a16 100644
--- a/src/rp2_common/pico_stdio/stdio.c
+++ b/src/rp2_common/pico_stdio/stdio.c
@@ -10,7 +10,9 @@
 
 #include "pico.h"
 #include "pico/mutex.h"
+#if LIB_PICO_PRINTF_PICO
 #include "pico/printf.h"
+#endif
 #include "pico/stdio.h"
 #include "pico/stdio/driver.h"
 #include "pico/time.h"
@@ -53,12 +55,15 @@ void stdout_serialize_end(void) {
 }
 
 #else
-static bool print_serialize_begin(void) {
+static bool stdout_serialize_begin(void) {
     return true;
 }
-static void print_serialize_end(void) {
+static void stdout_serialize_end(void) {
 }
 #endif
+static void stdio_out_chars_no_crlf(stdio_driver_t *driver, const char *s, int len) {
+    driver->out_chars(s, len);
+}
 
 static void stdio_out_chars_crlf(stdio_driver_t *driver, const char *s, int len) {
 #if PICO_STDIO_ENABLE_CRLF_SUPPORT
@@ -89,7 +94,7 @@ static void stdio_out_chars_crlf(stdio_driver_t *driver, const char *s, int len)
 #endif
 }
 
-static bool stdio_put_string(const char *s, int len, bool newline) {
+static bool stdio_put_string(const char *s, int len, bool newline, bool no_cr) {
     bool serialized = stdout_serialize_begin();
     if (!serialized) {
 #if PICO_STDIO_IGNORE_NESTED_STDOUT
@@ -97,13 +102,14 @@ static bool stdio_put_string(const char *s, int len, bool newline) {
 #endif
     }
     if (len == -1) len = (int)strlen(s);
+    void (*out_func)(stdio_driver_t *, const char *, int) = no_cr ? stdio_out_chars_no_crlf : stdio_out_chars_crlf;
     for (stdio_driver_t *driver = drivers; driver; driver = driver->next) {
         if (!driver->out_chars) continue;
         if (filter && filter != driver) continue;
-        stdio_out_chars_crlf(driver, s, len);
+        out_func(driver, s, len);
         if (newline) {
             const char c = '\n';
-            stdio_out_chars_crlf(driver, &c, 1);
+            out_func(driver, &c, 1);
         }
     }
     if (serialized) {
@@ -134,13 +140,26 @@ static int stdio_get_until(char *buf, int len, absolute_time_t until) {
 
 int WRAPPER_FUNC(putchar)(int c) {
     char cc = (char)c;
-    stdio_put_string(&cc, 1, false);
+    stdio_put_string(&cc, 1, false, false);
     return c;
 }
 
 int WRAPPER_FUNC(puts)(const char *s) {
     int len = (int)strlen(s);
-    stdio_put_string(s, len, true);
+    stdio_put_string(s, len, true, false);
+    stdio_flush();
+    return len;
+}
+
+int putchar_raw(int c) {
+    char cc = (char)c;
+    stdio_put_string(&cc, 1, false, true);
+    return c;
+}
+
+int puts_raw(const char *s) {
+    int len = (int)strlen(s);
+    stdio_put_string(s, len, true, true);
     stdio_flush();
     return len;
 }
@@ -154,7 +173,7 @@ int _read(int handle, char *buffer, int length) {
 
 int _write(int handle, char *buffer, int length) {
     if (handle == 1) {
-        stdio_put_string(buffer, length, false);
+        stdio_put_string(buffer, length, false, false);
         return length;
     }
     return -1;
@@ -243,7 +262,7 @@ int __printflike(1, 0) WRAPPER_FUNC(printf)(const char* format, ...)
     return ret;
 }
 
-void stdio_init_all() {
+void stdio_init_all(void) {
     // todo add explicit custom, or registered although you can call stdio_enable_driver explicitly anyway
     // These are well known ones
 #if LIB_PICO_STDIO_UART
diff --git a/src/rp2_common/pico_stdio_semihosting/stdio_semihosting.c b/src/rp2_common/pico_stdio_semihosting/stdio_semihosting.c
index 89367702e..4eb673f2d 100644
--- a/src/rp2_common/pico_stdio_semihosting/stdio_semihosting.c
+++ b/src/rp2_common/pico_stdio_semihosting/stdio_semihosting.c
@@ -18,7 +18,7 @@
 //    );
 //}
 
-static void __attribute__((naked)) semihosting_putc(char c) {
+static void __attribute__((naked)) semihosting_putc(__unused const char *c) {
     __asm (
 
     "mov r1, r0\n"
@@ -30,8 +30,8 @@ static void __attribute__((naked)) semihosting_putc(char c) {
 
 
 static void stdio_semihosting_out_chars(const char *buf, int length) {
-    for (uint i = 0; i <length; i++) {
-        semihosting_putc(buf[i]);
+    for (int i = 0; i < length; i++) {
+        semihosting_putc(&buf[i]);
     }
 }
 
diff --git a/src/rp2_common/pico_stdio_usb/CMakeLists.txt b/src/rp2_common/pico_stdio_usb/CMakeLists.txt
index 2e33f5ab3..b6abadda1 100644
--- a/src/rp2_common/pico_stdio_usb/CMakeLists.txt
+++ b/src/rp2_common/pico_stdio_usb/CMakeLists.txt
@@ -14,5 +14,6 @@ if (TARGET tinyusb_device_unmarked)
         pico_stdio
         pico_time
         pico_unique_id
+        pico_usb_reset_interface_headers
     )
 endif()
diff --git a/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb.h b/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb.h
index 6a1effa5b..2aeb6476a 100644
--- a/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb.h
+++ b/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb.h
@@ -54,6 +54,16 @@
 #define PICO_STDIO_USB_RESET_MAGIC_BAUD_RATE 1200
 #endif
 
+// PICO_CONFIG: PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS, Maximum number of milliseconds to wait during initialization for a CDC connection from the host (negative means indefinite) during initialization, default=0, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS
+#define PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS 0
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_POST_CONNECT_WAIT_DELAY_MS, Number of extra milliseconds to wait when using PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS after a host CDC connection is detected (some host terminals seem to sometimes lose transmissions sent right after connection), default=50, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_POST_CONNECT_WAIT_DELAY_MS
+#define PICO_STDIO_USB_POST_CONNECT_WAIT_DELAY_MS 50
+#endif
+
 // PICO_CONFIG: PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED, Optionally define a pin to use as bootloader activity LED when BOOTSEL mode is entered via USB (either VIA_BAUD_RATE or VIA_VENDOR_INTERFACE), type=int, min=0, max=29, group=pico_stdio_usb
 
 // PICO_CONFIG: PICO_STDIO_USB_RESET_BOOTSEL_FIXED_ACTIVITY_LED, Whether the pin specified by PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED is fixed or can be modified by picotool over the VENDOR USB interface, type=bool, default=0, group=pico_stdio_usb
@@ -94,10 +104,22 @@ extern "C" {
 extern stdio_driver_t stdio_usb;
 
 /*! \brief Explicitly initialize USB stdio and add it to the current set of stdin drivers
- *  \ingroup pico_stdio_uart
+ *  \ingroup pico_stdio_usb
+ *
+ *  \ref PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS can be set to cause this method to wait for a CDC connection
+ *  from the host before returning, which is useful if you don't want any initial stdout output to be discarded
+ *  before the connection is established.
+ *
+ *  \return true if the USB CDC was initialized, false if an error occurred
  */
 bool stdio_usb_init(void);
 
+/*! \brief Check if there is an active stdio CDC connection to a host
+ *  \ingroup pico_stdio_usb
+ *
+ *  \return true if stdio is connected over CDC
+ */
+bool stdio_usb_connected(void);
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb/reset_interface.h b/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb/reset_interface.h
index c8e248d37..e0cca103c 100644
--- a/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb/reset_interface.h
+++ b/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb/reset_interface.h
@@ -7,17 +7,7 @@
 #ifndef _PICO_STDIO_USB_RESET_INTERFACE_H
 #define _PICO_STDIO_USB_RESET_INTERFACE_H
 
-// We use VENDOR, 0, 0 for PICOBOOT, so lets use VENDOR, 0, 1 for RESET
+// definitions have been moved here
+#include "pico/usb_reset_interface.h"
 
-// VENDOR sub-class for the reset interface
-#define RESET_INTERFACE_SUBCLASS 0x00
-// VENDOR protocol for the reset interface
-#define RESET_INTERFACE_PROTOCOL 0x01
-
-// CONTROL requests:
-
-// reset to BOOTSEL
-#define RESET_REQUEST_BOOTSEL 0x01
-// regular flash boot
-#define RESET_REQUEST_FLASH 0x02
 #endif
\ No newline at end of file
diff --git a/src/rp2_common/pico_stdio_usb/reset_interface.c b/src/rp2_common/pico_stdio_usb/reset_interface.c
index 2f2e72b19..06dce86a9 100644
--- a/src/rp2_common/pico_stdio_usb/reset_interface.c
+++ b/src/rp2_common/pico_stdio_usb/reset_interface.c
@@ -38,7 +38,7 @@ static uint16_t resetd_open(uint8_t __unused rhport, tusb_desc_interface_t const
 }
 
 // Support for parameterized reset via vendor interface control request
-static bool resetd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) {
+static bool resetd_control_xfer_cb(uint8_t __unused rhport, uint8_t stage, tusb_control_request_t const * request) {
     // nothing to do with DATA & ACK stage
     if (stage != CONTROL_STAGE_SETUP) return true;
 
diff --git a/src/rp2_common/pico_stdio_usb/stdio_usb.c b/src/rp2_common/pico_stdio_usb/stdio_usb.c
index 2cca2c22a..913d606c4 100644
--- a/src/rp2_common/pico_stdio_usb/stdio_usb.c
+++ b/src/rp2_common/pico_stdio_usb/stdio_usb.c
@@ -41,10 +41,10 @@ static void stdio_usb_out_chars(const char *buf, int length) {
     if (tud_cdc_connected()) {
         for (int i = 0; i < length;) {
             int n = length - i;
-            int avail = tud_cdc_write_available();
+            int avail = (int) tud_cdc_write_available();
             if (n > avail) n = avail;
             if (n) {
-                int n2 = tud_cdc_write(buf + i, n);
+                int n2 = (int) tud_cdc_write(buf + i, (uint32_t)n);
                 tud_task();
                 tud_cdc_write_flush();
                 i += n2;
@@ -73,7 +73,7 @@ int stdio_usb_in_chars(char *buf, int length) {
     }
     int rc = PICO_ERROR_NO_DATA;
     if (tud_cdc_connected() && tud_cdc_available()) {
-        int count = tud_cdc_read(buf, length);
+        int count = (int) tud_cdc_read(buf, (uint32_t) length);
         rc =  count ? count : PICO_ERROR_NO_DATA;
     }
     mutex_exit(&stdio_usb_mutex);
@@ -103,9 +103,29 @@ bool stdio_usb_init(void) {
     bool rc = add_alarm_in_us(PICO_STDIO_USB_TASK_INTERVAL_US, timer_task, NULL, true);
     if (rc) {
         stdio_set_driver_enabled(&stdio_usb, true);
+#if PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS
+#if PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS > 0
+        absolute_time_t until = make_timeout_time_ms(PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS);
+#else
+        absolute_time_t until = at_the_end_of_time;
+#endif
+        do {
+            if (stdio_usb_connected()) {
+#if PICO_STDIO_USB_POST_CONNECT_WAIT_DELAY_MS != 0
+                sleep_ms(PICO_STDIO_USB_POST_CONNECT_WAIT_DELAY_MS);
+#endif
+                break;
+            }
+            sleep_ms(10);
+        } while (!time_reached(until));
+#endif
     }
     return rc;
 }
+
+bool stdio_usb_connected(void) {
+    return tud_cdc_connected();
+}
 #else
 #include "pico/stdio_usb.h"
 #warning stdio USB was configured, but is being disabled as TinyUSB is explicitly linked
diff --git a/src/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c b/src/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c
index d06d70048..b3cfed01f 100644
--- a/src/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c
+++ b/src/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c
@@ -143,7 +143,7 @@ const uint16_t *tud_descriptor_string_cb(uint8_t index, __unused uint16_t langid
     }
 
     // first byte is length (including header), second byte is string type
-    desc_str[0] = (TUSB_DESC_STRING << 8) | (2 * len + 2);
+    desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * len + 2));
 
     return desc_str;
 }
diff --git a/src/rp2_common/pico_unique_id/include/pico/unique_id.h b/src/rp2_common/pico_unique_id/include/pico/unique_id.h
index 31b09ed9e..4132a60e0 100644
--- a/src/rp2_common/pico_unique_id/include/pico/unique_id.h
+++ b/src/rp2_common/pico_unique_id/include/pico/unique_id.h
@@ -7,6 +7,8 @@
 #ifndef _PICO_UNIQUE_ID_H_
 #define _PICO_UNIQUE_ID_H_
 
+#include "pico.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/src/rp2_common/tinyusb/CMakeLists.txt b/src/rp2_common/tinyusb/CMakeLists.txt
index c4d238d09..80a6e7819 100644
--- a/src/rp2_common/tinyusb/CMakeLists.txt
+++ b/src/rp2_common/tinyusb/CMakeLists.txt
@@ -15,12 +15,13 @@ elseif (NOT EXISTS ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH})
 endif()
 
 if (EXISTS ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH})
-    message("TinyUSB available at ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH}; adding USB support.")
+    message("TinyUSB available at ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH}; enabling build support for USB.")
 
     pico_register_common_scope_var(PICO_TINYUSB_PATH)
 
     set(BOARD pico_sdk)
-    include(${PICO_TINYUSB_PATH}/hw/bsp/rp2040/family.cmake)
+    set(FAMILY rp2040)
+    include(${PICO_TINYUSB_PATH}/hw/bsp/family_support.cmake)
 
     add_library(tinyusb_common INTERFACE)
     target_link_libraries(tinyusb_common INTERFACE tinyusb_common_base)
diff --git a/test/kitchen_sink/CMakeLists.txt b/test/kitchen_sink/CMakeLists.txt
index 68d7a6108..024d42c19 100644
--- a/test/kitchen_sink/CMakeLists.txt
+++ b/test/kitchen_sink/CMakeLists.txt
@@ -97,7 +97,13 @@ pico_set_program_name(kitchen_sink "Wombat tentacles")
 pico_add_extra_outputs(kitchen_sink)
 
 add_executable(kitchen_sink_extra_stdio)
-target_link_libraries(kitchen_sink_extra_stdio kitchen_sink_libs) # no kitchen_sink_options as TinyUSB has warnings
+if (COMMAND suppress_tinyusb_warnings)
+    # Explicitly suppress warnings in TinyUSB files which have them (this has to be done
+    # from the project that uses them per CMake "feature"). Note the function comes from
+    # TinyUSB itself, so we have to guard against TinyUSB not being present with the above if
+    suppress_tinyusb_warnings()
+endif()
+target_link_libraries(kitchen_sink_extra_stdio kitchen_sink_libs kitchen_sink_options)
 pico_add_extra_outputs(kitchen_sink_extra_stdio)
 pico_enable_stdio_usb(kitchen_sink_extra_stdio 1)
 pico_enable_stdio_semihosting(kitchen_sink_extra_stdio 1)
@@ -111,3 +117,4 @@ add_executable(kitchen_sink_no_flash)
 pico_set_binary_type(kitchen_sink_no_flash no_flash)
 target_link_libraries(kitchen_sink_no_flash kitchen_sink_libs kitchen_sink_options)
 pico_add_extra_outputs(kitchen_sink_no_flash)
+
diff --git a/test/kitchen_sink/kitchen_sink.c b/test/kitchen_sink/kitchen_sink.c
index e607b80a0..57d4ef7f5 100644
--- a/test/kitchen_sink/kitchen_sink.c
+++ b/test/kitchen_sink/kitchen_sink.c
@@ -18,6 +18,7 @@
 #include "hardware/interp.h"
 #include "hardware/irq.h"
 #include "hardware/pio.h"
+#include "hardware/pio_instructions.h"
 #include "hardware/pll.h"
 #include "hardware/pwm.h"
 #include "hardware/resets.h"
@@ -40,11 +41,45 @@
 #include "pico/malloc.h"
 #include "pico/multicore.h"
 #include "pico/printf.h"
+#include "pico/runtime.h"
+#include "pico/stdio.h"
 #include "pico/stdlib.h"
 #include "pico/sync.h"
 #include "pico/time.h"
 #include "pico/unique_id.h"
 
+#include "hardware/structs/adc.h"
+#include "hardware/structs/bus_ctrl.h"
+#include "hardware/structs/clocks.h"
+#include "hardware/structs/dma.h"
+#include "hardware/structs/i2c.h"
+#include "hardware/structs/interp.h"
+#include "hardware/structs/iobank0.h"
+#include "hardware/structs/ioqspi.h"
+#include "hardware/structs/mpu.h"
+#include "hardware/structs/padsbank0.h"
+#include "hardware/structs/pads_qspi.h"
+#include "hardware/structs/pio.h"
+#include "hardware/structs/pll.h"
+#include "hardware/structs/psm.h"
+#include "hardware/structs/pwm.h"
+#include "hardware/structs/resets.h"
+#include "hardware/structs/rosc.h"
+#include "hardware/structs/rtc.h"
+#include "hardware/structs/scb.h"
+#include "hardware/structs/sio.h"
+#include "hardware/structs/spi.h"
+#include "hardware/structs/ssi.h"
+#include "hardware/structs/syscfg.h"
+#include "hardware/structs/systick.h"
+#include "hardware/structs/timer.h"
+#include "hardware/structs/uart.h"
+#include "hardware/structs/usb.h"
+#include "hardware/structs/vreg_and_chip_reset.h"
+#include "hardware/structs/watchdog.h"
+#include "hardware/structs/xip_ctrl.h"
+#include "hardware/structs/xosc.h"
+        
 bi_decl(bi_block_device(
                            BINARY_INFO_MAKE_TAG('K', 'S'),
                            "foo",
@@ -84,7 +119,7 @@ void __isr dma_handler_b(void) {
     printf("HELLO B\n");
     if (dma_hw->ints1 & 1) {
         dma_hw->ints1 = 1;
-        printf("B WINS DNA_TO %08x\n", (uint) dma_to);
+        printf("B WINS DMA_TO %08x\n", (uint) dma_to);
 //        irq_remove_handler(DMA_IRQ_1, dma_handler_b);
     }
 }
diff --git a/test/pico_divider_test/pico_divider_nesting_test.c b/test/pico_divider_test/pico_divider_nesting_test.c
index 0e0db9499..3b5a745e2 100644
--- a/test/pico_divider_test/pico_divider_nesting_test.c
+++ b/test/pico_divider_test/pico_divider_nesting_test.c
@@ -158,6 +158,23 @@ void test_nesting() {
             if (0xffffffffu != a * 11 + b) {
                 FAILED();
             }
+            static uint64_t z64;
+            z64 -= 47;
+            uint64_t a64 = z64 / -13635;
+            uint64_t b64 = z64 % -13635;
+            if (z64 != a64 * -13635 + b64) {
+                FAILED();
+            }
+            // specifically check 64/32 divide
+            static uint64_t c64 = 0x13ffffffffull;
+            static uint32_t cd = 1;
+            a64 = c64 / cd;
+            b64 = c64 % cd;
+            if (c64 != a64 * cd + b64) {
+                FAILED();
+            }
+            cd++;
+
         }
         // these use the divider
         for(uint i=0;i<=100;i+=20) {
diff --git a/tools/CMakeLists.txt b/tools/CMakeLists.txt
index 2e908b200..f66f9d0b2 100644
--- a/tools/CMakeLists.txt
+++ b/tools/CMakeLists.txt
@@ -27,10 +27,10 @@ function(pico_generate_pio_header TARGET PIO)
             )
     add_dependencies(${TARGET} ${HEADER_GEN_TARGET})
     get_target_property(target_type ${TARGET} TYPE)
-    if ("EXECUTABLE" STREQUAL "${target_type}")
-        target_include_directories(${TARGET} PRIVATE ${HEADER_DIR})
-    else()
+    if ("INTERFACE_LIBRARY" STREQUAL "${target_type}")
         target_include_directories(${TARGET} INTERFACE ${HEADER_DIR})
+    else()
+        target_include_directories(${TARGET} PUBLIC ${HEADER_DIR})
     endif()
 endfunction()
 
@@ -41,6 +41,6 @@ function(pico_add_uf2_output TARGET)
     endif()
     if (ELF2UF2_FOUND)
         add_custom_command(TARGET ${TARGET} POST_BUILD
-                COMMAND ELF2UF2 ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} ${TARGET}.uf2)
+                COMMAND ELF2UF2 $<TARGET_FILE:${TARGET}> $<IF:$<BOOL:$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>>,$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>,$<TARGET_PROPERTY:${TARGET},NAME>>.uf2)
     endif()
 endfunction()
diff --git a/tools/elf2uf2/main.cpp b/tools/elf2uf2/main.cpp
index b66f082ce..2c0ddcd0d 100644
--- a/tools/elf2uf2/main.cpp
+++ b/tools/elf2uf2/main.cpp
@@ -143,6 +143,9 @@ int read_and_check_elf32_ph_entries(FILE *in, const elf32_header &eh, const addr
     }
     if (eh.ph_num) {
         std::vector<elf32_ph_entry> entries(eh.ph_num);
+        if (fseek(in, eh.ph_offset, SEEK_SET)) {
+            return fail_read_error();
+        }
         if (eh.ph_num != fread(&entries[0], sizeof(struct elf32_ph_entry), eh.ph_num, in)) {
             return fail_read_error();
         }
diff --git a/tools/pioasm/gen/parser.cpp b/tools/pioasm/gen/parser.cpp
index 1e41a0979..c9bd036ee 100644
--- a/tools/pioasm/gen/parser.cpp
+++ b/tools/pioasm/gen/parser.cpp
@@ -1945,9 +1945,9 @@ namespace yy {
      -52,    97,   132,   -52,   -52,   -52,   -52,    87,   -52,   -52,
        1,     5,     5,     5,     5,   -52,     5,     5,   -52,   -52,
      -52,   -52,    29,   118,     5,   -52,   170,   -52,   -52,   -52,
-     107,   177,     1,     1,     1,     1,     1,     1,     1,   -52,
+     182,   177,     1,     1,     1,     1,     1,     1,     1,   -52,
      -52,   -51,   -52,   177,   119,   -52,   -52,   -52,   -52,   -52,
-     -52,   -52,    82,   -52,   -52,   -52,   107,   107,   184,   184,
+     -52,   -52,    82,   -52,   -52,   -52,   182,   182,   107,   107,
      -52,   -52,   -52,   -52,   -52,   -52,   -52,   -52,   -52,   -52,
      -52,   -52,   -52,   -52,   -52
   };
@@ -1979,9 +1979,9 @@ namespace yy {
   const short
   parser::yypgoto_[] =
   {
-     -52,   -52,   -52,    98,   -52,   -52,   -52,    -7,   -14,   168,
-     -52,    99,   102,   -52,   148,    25,   -52,   -52,   -52,   -52,
-     -52,   -52,   -52,   -52,   128,   -52,   199
+     -52,   -52,   -52,   102,   -52,   -52,   -52,    -7,   -14,   172,
+     -52,    99,   103,   -52,   146,    25,   -52,   -52,   -52,   -52,
+     -52,   -52,   -52,   -52,   128,   -52,   198
   };
 
   const short
@@ -2014,8 +2014,8 @@ namespace yy {
       12,    13,    14,    15,    16,    17,    18,    19,    20,   149,
      163,   176,   142,   143,   144,   145,   146,   147,   148,   165,
      142,   143,   144,   145,   146,   147,   148,   142,   143,   144,
-     145,   146,   147,   148,   142,   143,   135,    99,   146,   147,
-     148,   125,   139,   131,   138,    36
+     145,   146,   147,   148,   144,   145,   146,   147,   148,   125,
+     135,    99,   139,   131,    36,   138
   };
 
   const unsigned char
@@ -2040,8 +2040,8 @@ namespace yy {
       31,    32,    33,    34,    35,    36,    37,    38,    39,     7,
       52,    52,    10,    11,    12,    13,    14,    15,    16,     9,
       10,    11,    12,    13,    14,    15,    16,    10,    11,    12,
-      13,    14,    15,    16,    10,    11,    98,    29,    14,    15,
-      16,    53,   103,    75,   102,     6
+      13,    14,    15,    16,    12,    13,    14,    15,    16,    53,
+      98,    29,   103,    75,     6,   102
   };
 
   const signed char
diff --git a/tools/pioasm/main.cpp b/tools/pioasm/main.cpp
index 1c86bea22..e7ff6866b 100644
--- a/tools/pioasm/main.cpp
+++ b/tools/pioasm/main.cpp
@@ -37,14 +37,14 @@ int main(int argc, char *argv[]) {
     for (; !res && i < argc; i++) {
         if (argv[i][0] != '-') break;
         if (argv[i] == std::string("-o")) {
-            if (i++ < argc) {
+            if (++i < argc) {
                 format = argv[i];
             } else {
                 std::cerr << "error: -o requires format value" << std::endl;
                 res = 1;
             }
         } else if (argv[i] == std::string("-p")) {
-            if (i++ < argc) {
+            if (++i < argc) {
                 options.emplace_back(argv[i]);
             } else {
                 std::cerr << "error: -p requires parameter value" << std::endl;
diff --git a/tools/pioasm/parser.yy b/tools/pioasm/parser.yy
index f1f51dd2a..467ca890f 100644
--- a/tools/pioasm/parser.yy
+++ b/tools/pioasm/parser.yy
@@ -124,8 +124,8 @@
 
 
 %left REVERSE
-%left MULTIPLY DIVIDE
 %left PLUS MINUS
+%left MULTIPLY DIVIDE
 %left AND OR XOR
 
 %printer { yyo << "..."; } <*>;
diff --git a/tools/pioasm/pio_assembler.cpp b/tools/pioasm/pio_assembler.cpp
index 7a838310a..469d733a8 100644
--- a/tools/pioasm/pio_assembler.cpp
+++ b/tools/pioasm/pio_assembler.cpp
@@ -127,7 +127,7 @@ void program::set_wrap(const yy::location &l) {
         throw syntax_error(l, msg.str());
     }
     if (instructions.empty()) {
-        throw syntax_error(l, ".wrap cannot be pleaced before the first program instruction");
+        throw syntax_error(l, ".wrap cannot be placed before the first program instruction");
     }
     wrap = resolvable_int(l, instructions.size() - 1);
 }
diff --git a/tools/pioasm/python_output.cpp b/tools/pioasm/python_output.cpp
index fb94e522c..38f7ffea1 100644
--- a/tools/pioasm/python_output.cpp
+++ b/tools/pioasm/python_output.cpp
@@ -195,9 +195,12 @@ struct python_output : public output_format {
                         if (arg2 & 0x8u) {
                             invalid = true;
                         } else {
-                            guts = "irq, " + std::to_string(arg2 & 7u);
+                            guts = "irq, ";
+                            auto irq = std::to_string(arg2 & 7u);
                             if (arg2 & 0x10u) {
-                                guts += " rel";
+                                guts += "rel(" + irq + ")";
+                            } else {
+                                guts += irq;
                             }
                         }
                         break;
@@ -233,12 +236,11 @@ struct python_output : public output_format {
                     std::string guts = "";
                     if (arg1 & 4u) {
                         op("pull");
-                        if (arg1 & 2u) guts = "ifempty";
+                        if (arg1 & 2u) guts = "ifempty, ";
                     } else {
                         op("push");
-                        if (arg1 & 2u) guts = "iffull";
+                        if (arg1 & 2u) guts = "iffull, ";
                     }
-                    guts += ", ";
                     guts += ((arg1 & 0x1u) ? "block" : "noblock");
                     op_guts(guts);
                 }
@@ -279,15 +281,17 @@ struct python_output : public output_format {
                     op("irq");
                     std::string guts;
                     if (arg1 & 0x2u) {
-                        guts += "clear ";
+                        guts += "clear, ";
                     } else if (arg1 & 0x1u) {
-                        guts += "wait ";
+                        guts += "wait, ";
                     } else {
-                        guts += "nowait ";
+                        guts += "nowait, ";
                     }
-                    guts += std::to_string(arg2 & 7u);
+                    auto irq = std::to_string(arg2 & 7u);
                     if (arg2 & 0x10u) {
-                        guts += " rel";
+                        guts += "rel(" + irq + ")";
+                    } else {
+                        guts += irq;
                     }
                     op_guts(guts);
                 }

From 658a21b946caf205f38d65565220d2a61eb3fba7 Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Tue, 17 May 2022 12:59:00 -0500
Subject: [PATCH 02/51] Update rtc_set_datetime docs to point out that the
 written value may not be immediately visible (#832)

---
 src/rp2_common/hardware_rtc/include/hardware/rtc.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/rp2_common/hardware_rtc/include/hardware/rtc.h b/src/rp2_common/hardware_rtc/include/hardware/rtc.h
index 8757e36e0..2a72a8eb9 100644
--- a/src/rp2_common/hardware_rtc/include/hardware/rtc.h
+++ b/src/rp2_common/hardware_rtc/include/hardware/rtc.h
@@ -47,6 +47,10 @@ void rtc_init(void);
 /*! \brief Set the RTC to the specified time
  *  \ingroup hardware_rtc
  *
+ * \note Note that after setting the RTC date and time, a subsequent read of the values (e.g. via rtc_get_datetime()) may not
+ * reflect the new setting until up to three cycles of the potentially-much-slower RTC clock domain have passed. This represents a period
+ * of 64 microseconds with the default RTC clock configuration.
+ *
  * \param t Pointer to a \ref datetime_t structure contains time to set
  * \return true if set, false if the passed in datetime was invalid.
  */

From b2ad632c244e00fa363617b3dbde256fd8ff6f25 Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Tue, 17 May 2022 13:04:38 -0500
Subject: [PATCH 03/51] Minor additions to PIO documentation (#831)

---
 src/rp2_common/hardware_pio/include/hardware/pio.h | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/src/rp2_common/hardware_pio/include/hardware/pio.h b/src/rp2_common/hardware_pio/include/hardware/pio.h
index ebe6afd8f..e42c60fc2 100644
--- a/src/rp2_common/hardware_pio/include/hardware/pio.h
+++ b/src/rp2_common/hardware_pio/include/hardware/pio.h
@@ -95,6 +95,9 @@ typedef pio_hw_t *PIO;
 
 /** \brief PIO Configuration structure
  *  \ingroup sm_config
+ *
+ * This structure is an in-memory representation of the configuration that can be applied to a PIO
+ * state machine later using pio_sm_set_config() or pio_sm_init().
  */
 typedef struct {
     uint32_t clkdiv;
@@ -902,7 +905,7 @@ static inline void pio_sm_set_wrap(PIO pio, uint sm, uint wrap_target, uint wrap
 }
 
 /*! \brief Set the current 'out' pins for a state machine
- *  \ingroup sm_config
+ *  \ingroup hardware_pio
  *
  * Can overlap with the 'in', 'set' and 'sideset' pins
  *
@@ -923,7 +926,7 @@ static inline void pio_sm_set_out_pins(PIO pio, uint sm, uint out_base, uint out
 
 
 /*! \brief Set the current 'set' pins for a state machine
- *  \ingroup sm_config
+ *  \ingroup hardware_pio
  *
  * Can overlap with the 'in', 'out' and 'sideset' pins
  *
@@ -943,7 +946,7 @@ static inline void pio_sm_set_set_pins(PIO pio, uint sm, uint set_base, uint set
 }
 
 /*! \brief Set the current 'in' pins for a state machine
- *  \ingroup sm_config
+ *  \ingroup hardware_pio
  *
  * Can overlap with the 'out', 'set' and 'sideset' pins
  *
@@ -960,7 +963,7 @@ static inline void pio_sm_set_in_pins(PIO pio, uint sm, uint in_base) {
 }
 
 /*! \brief Set the current 'sideset' pins for a state machine
- *  \ingroup sm_config
+ *  \ingroup hardware_pio
  *
  * Can overlap with the 'in', 'out' and 'set' pins
  *

From 530204ec0c2011ebb413cd0e3ed4d84ef14372e1 Mon Sep 17 00:00:00 2001
From: Andrew Scheller <andrew.scheller@raspberrypi.com>
Date: Wed, 18 May 2022 01:24:52 +0100
Subject: [PATCH 04/51] Small tweak to busy_wait_at_least_cycles doxygen (#834)

---
 src/rp2_common/pico_platform/include/pico/platform.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/rp2_common/pico_platform/include/pico/platform.h b/src/rp2_common/pico_platform/include/pico/platform.h
index de64e3003..ffc7660cb 100644
--- a/src/rp2_common/pico_platform/include/pico/platform.h
+++ b/src/rp2_common/pico_platform/include/pico/platform.h
@@ -405,12 +405,12 @@ uint __get_current_exception(void);
  *
  * This method is useful for introducing very short delays.
  *
- * This method busy-waits in a tight loop for the give number of system clock cycles. The total wait time is only accurate to within 2 cycles,
+ * This method busy-waits in a tight loop for the given number of system clock cycles. The total wait time is only accurate to within 2 cycles,
  * and this method uses a loop counter rather than a hardware timer, so the method will always take longer than expected if an
- * interrupt is handled on the calling core when during the busy-wait; you can of course disable interrupts to prevent this.
+ * interrupt is handled on the calling core during the busy-wait; you can of course disable interrupts to prevent this.
  *
- * You can use \ref clock_get_hz(clk_sys) to determine the number of clock cycles per second if you want to convert to cycles
- * from an actual time duration.
+ * You can use \ref clock_get_hz(clk_sys) to determine the number of clock cycles per second if you want to convert an actual
+ * time duration to a number of cycles.
  *
  * \param minimum_cycles the minimum number of system clock cycles to delay for
  */

From 7880405292cc441d98e91c87634e69404df98254 Mon Sep 17 00:00:00 2001
From: Andrew Scheller <andrew.scheller@raspberrypi.com>
Date: Wed, 18 May 2022 01:26:00 +0100
Subject: [PATCH 05/51] Doxygen typo (#835)

---
 src/rp2_common/hardware_watchdog/include/hardware/watchdog.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/rp2_common/hardware_watchdog/include/hardware/watchdog.h b/src/rp2_common/hardware_watchdog/include/hardware/watchdog.h
index 747838be8..7ce89ffc1 100644
--- a/src/rp2_common/hardware_watchdog/include/hardware/watchdog.h
+++ b/src/rp2_common/hardware_watchdog/include/hardware/watchdog.h
@@ -97,7 +97,7 @@ bool watchdog_caused_reboot(void);
  * This would not be present if a watchdog reset is initiated by \ref watchdog_reboot or by the RP2040 bootrom
  * (e.g. dragging a UF2 onto the RPI-RP2 drive).
  *
- * @return true If the watchdog timer or a watchdog force caused (see \reg watchdog_caused_reboot) the last reboot
+ * @return true If the watchdog timer or a watchdog force caused (see \ref watchdog_caused_reboot) the last reboot
  *              and the watchdog reboot happened after \ref watchdog_enable was called
  * @return false If there has been no watchdog reboot since the last power on reset, or the watchdog reboot was not caused
  *               by a watchdog timeout after \ref watchdog_enable was called.

From 1e6c122fc97a058e0dbad1dc3e0960b54365d9f3 Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Wed, 18 May 2022 10:39:17 -0500
Subject: [PATCH 06/51] gate inclusion of pico.h in binary info, so as not to
 break picotool builds (#836)

---
 src/common/pico_binary_info/include/pico/binary_info/code.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/common/pico_binary_info/include/pico/binary_info/code.h b/src/common/pico_binary_info/include/pico/binary_info/code.h
index 0f1cd1c73..9478477c9 100644
--- a/src/common/pico_binary_info/include/pico/binary_info/code.h
+++ b/src/common/pico_binary_info/include/pico/binary_info/code.h
@@ -7,7 +7,12 @@
 #ifndef _PICO_BINARY_INFO_CODE_H
 #define _PICO_BINARY_INFO_CODE_H
 
+// pico.h is not available when PICO_NO_BINARY_INFO=1 is used for builds outside of the SDK (e.g. picotool)
+// and only needed anyway (because of macro definitions) in PICO_NO_BINARY_INFO=0 builds
+#if !PICO_NO_BINARY_INFO
 #include "pico.h"
+#endif
+
 #include "pico/binary_info/structure.h"
 
 #if !PICO_NO_BINARY_INFO

From 426e46126b5a1efaea4544cdb71ab81b61983034 Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Tue, 17 May 2022 13:42:49 -0500
Subject: [PATCH 07/51] SDK 1.3.1 release

---
 pico_sdk_version.cmake | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pico_sdk_version.cmake b/pico_sdk_version.cmake
index a9154cc64..e2ecdac3b 100644
--- a/pico_sdk_version.cmake
+++ b/pico_sdk_version.cmake
@@ -9,7 +9,7 @@ set(PICO_SDK_VERSION_MINOR 3)
 set(PICO_SDK_VERSION_REVISION 1)
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base
 # PICO_CONFIG: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base
-set(PICO_SDK_VERSION_PRE_RELEASE_ID develop)
+#set(PICO_SDK_VERSION_PRE_RELEASE_ID develop)
 
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base
 # PICO_CONFIG: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base

From 4e4cf11d9bb31dc89696f01f89fa4654b66a7afd Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Wed, 18 May 2022 15:52:03 -0500
Subject: [PATCH 08/51] Start SDK 1.3.2 development

---
 pico_sdk_version.cmake | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/pico_sdk_version.cmake b/pico_sdk_version.cmake
index e2ecdac3b..bd6fdbf12 100644
--- a/pico_sdk_version.cmake
+++ b/pico_sdk_version.cmake
@@ -6,10 +6,10 @@ set(PICO_SDK_VERSION_MAJOR 1)
 set(PICO_SDK_VERSION_MINOR 3)
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, group=pico_base
 # PICO_CONFIG: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, group=pico_base
-set(PICO_SDK_VERSION_REVISION 1)
+set(PICO_SDK_VERSION_REVISION 2)
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base
 # PICO_CONFIG: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base
-#set(PICO_SDK_VERSION_PRE_RELEASE_ID develop)
+set(PICO_SDK_VERSION_PRE_RELEASE_ID develop)
 
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base
 # PICO_CONFIG: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base

From f3c446ae1433caef846d3d0723dc0108da8fef47 Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Mon, 6 Jun 2022 08:20:00 -0500
Subject: [PATCH 09/51] move get_core_num() into platform.h (#852)

---
 src/host/hardware_sync/include/hardware/sync.h       |  2 --
 src/host/pico_platform/include/pico/platform.h       |  3 +++
 src/rp2_common/hardware_sync/include/hardware/sync.h |  9 ---------
 src/rp2_common/pico_platform/include/pico/platform.h | 11 +++++++++++
 4 files changed, 14 insertions(+), 11 deletions(-)

diff --git a/src/host/hardware_sync/include/hardware/sync.h b/src/host/hardware_sync/include/hardware/sync.h
index a27ea0100..58426f5e2 100644
--- a/src/host/hardware_sync/include/hardware/sync.h
+++ b/src/host/hardware_sync/include/hardware/sync.h
@@ -86,8 +86,6 @@ bool is_spin_locked(const spin_lock_t *lock);
 
 void spin_unlock(spin_lock_t *lock, uint32_t saved_irq);
 
-uint get_core_num();
-
 spin_lock_t *spin_lock_init(uint lock_num);
 
 void clear_spin_locks(void);
diff --git a/src/host/pico_platform/include/pico/platform.h b/src/host/pico_platform/include/pico/platform.h
index a4d3eaf67..b5e81370d 100644
--- a/src/host/pico_platform/include/pico/platform.h
+++ b/src/host/pico_platform/include/pico/platform.h
@@ -139,6 +139,9 @@ static inline int32_t __mul_instruction(int32_t a,int32_t b)
 
 static inline void __compiler_memory_barrier(void) {
 }
+
+uint get_core_num();
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/rp2_common/hardware_sync/include/hardware/sync.h b/src/rp2_common/hardware_sync/include/hardware/sync.h
index 8f91d5595..eee675e4b 100644
--- a/src/rp2_common/hardware_sync/include/hardware/sync.h
+++ b/src/rp2_common/hardware_sync/include/hardware/sync.h
@@ -304,15 +304,6 @@ __force_inline static void spin_unlock(spin_lock_t *lock, uint32_t saved_irq) {
     restore_interrupts(saved_irq);
 }
 
-/*! \brief Get the current core number
- *  \ingroup hardware_sync
- *
- * \return The core number the call was made from
- */
-__force_inline static uint get_core_num(void) {
-    return (*(uint32_t *) (SIO_BASE + SIO_CPUID_OFFSET));
-}
-
 /*! \brief Initialise a spin lock
  *  \ingroup hardware_sync
  *
diff --git a/src/rp2_common/pico_platform/include/pico/platform.h b/src/rp2_common/pico_platform/include/pico/platform.h
index ffc7660cb..1236fcd55 100644
--- a/src/rp2_common/pico_platform/include/pico/platform.h
+++ b/src/rp2_common/pico_platform/include/pico/platform.h
@@ -17,6 +17,8 @@
  */
 
 #include "hardware/platform_defs.h"
+#include "hardware/regs/addressmap.h"
+#include "hardware/regs/sio.h"
 
 // Marker for builds targeting the RP2040
 #define PICO_RP2040 1
@@ -423,6 +425,15 @@ static inline void busy_wait_at_least_cycles(uint32_t minimum_cycles) {
     );
 }
 
+/*! \brief Get the current core number
+ *  \ingroup pico_platform
+ *
+ * \return The core number the call was made from
+ */
+__force_inline static uint get_core_num(void) {
+    return (*(uint32_t *) (SIO_BASE + SIO_CPUID_OFFSET));
+}
+
 #else // __ASSEMBLER__
 
 #define WRAPPER_FUNC_NAME(x) __wrap_##x

From d3dcbb829211e9c3531acee6a175277db1424e1a Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Tue, 7 Jun 2022 14:27:38 -0500
Subject: [PATCH 10/51] Add new user_irq claim APIs to make it easier for
 independent code using them to interoperate (#854)

---
 .../include/hardware/platform_defs.h          |  1 +
 .../hardware_irq/include/hardware/irq.h       | 63 +++++++++++++++++++
 src/rp2_common/hardware_irq/irq.c             | 31 +++++++++
 .../pico_stdio_usb/include/pico/stdio_usb.h   |  4 +-
 src/rp2_common/pico_stdio_usb/stdio_usb.c     | 19 ++++--
 5 files changed, 112 insertions(+), 6 deletions(-)

diff --git a/src/rp2040/hardware_regs/include/hardware/platform_defs.h b/src/rp2040/hardware_regs/include/hardware/platform_defs.h
index 08c715944..21f77cacd 100644
--- a/src/rp2040/hardware_regs/include/hardware/platform_defs.h
+++ b/src/rp2040/hardware_regs/include/hardware/platform_defs.h
@@ -21,6 +21,7 @@
 #define NUM_DMA_CHANNELS _u(12)
 #define NUM_DMA_TIMERS _u(4)
 #define NUM_IRQS _u(32)
+#define NUM_USER_IRQS _u(6)
 #define NUM_PIOS _u(2)
 #define NUM_PIO_STATE_MACHINES _u(4)
 #define NUM_PWM_SLICES _u(8)
diff --git a/src/rp2_common/hardware_irq/include/hardware/irq.h b/src/rp2_common/hardware_irq/include/hardware/irq.h
index f4451b835..4f834661b 100644
--- a/src/rp2_common/hardware_irq/include/hardware/irq.h
+++ b/src/rp2_common/hardware_irq/include/hardware/irq.h
@@ -289,6 +289,69 @@ void irq_set_pending(uint num);
  * \note This is an internal method and user should generally not call it.
  */
 void irq_init_priorities(void);
+
+/*! \brief Claim ownership of a user IRQ on the calling core
+ *  \ingroup hardware_irq
+ *  
+ * User IRQs are numbered 26-31 and are not connected to any hardware, but can be triggered by \ref irq_set_pending.
+ *
+ * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therfore all functions
+ * dealing with Uer IRQs affect only the calling core
+ * 
+ * This method explicitly claims ownership of a user IRQ, so other code can know it is being used.
+ *
+ * \param irq_num the user IRQ to claim
+ */
+void user_irq_claim(uint irq_num);
+
+/*! \brief Mark a user IRQ as no longer used on the calling core
+ *  \ingroup hardware_irq
+ *
+ * User IRQs are numbered 26-31 and are not connected to any hardware, but can be triggered by \ref irq_set_pending.
+ *
+ * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therfore all functions
+ * dealing with Uer IRQs affect only the calling core
+ * 
+ * This method explicitly releases ownership of a user IRQ, so other code can know it is free to use.
+ * 
+ * \note it is customary to have disabled the irq and removed the handler prior to calling this method.
+ *
+ * \param irq_num the irq irq_num to unclaim
+ */
+void user_irq_unclaim(uint irq_num);
+
+/*! \brief Claim ownership of a free user IRQ on the calling core
+ *  \ingroup hardware_irq
+ *  
+ * User IRQs are numbered 26-31 and are not connected to any hardware, but can be triggered by \ref irq_set_pending.
+ *
+ * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therfore all functions
+ * dealing with Uer IRQs affect only the calling core
+ * 
+ * This method explicitly claims ownership of an unused user IRQ if there is one, so other code can know it is being used.
+ *
+ * \param required if true the function will panic if none are available
+ * \return the user IRQ number or -1 if required was false, and none were free
+ */
+int user_irq_claim_unused(bool required);
+
+/*
+*! \brief Check if a user IRQ is in use on the calling core
+ *  \ingroup hardware_irq
+ *  
+ * User IRQs are numbered 26-31 and are not connected to any hardware, but can be triggered by \ref irq_set_pending.
+ *
+ * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therfore all functions
+ * dealing with Uer IRQs affect only the calling core
+ *
+ * \param irq_num the irq irq_num
+ * \return true if the irq_num is claimed, false otherwise
+ * \sa user_irq_claim
+ * \sa user_irq_unclaim
+ * \sa user_irq_claim_unused
+ */
+bool user_irq_is_claimed(uint irq_num);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/rp2_common/hardware_irq/irq.c b/src/rp2_common/hardware_irq/irq.c
index def098ba2..170fcf1ce 100644
--- a/src/rp2_common/hardware_irq/irq.c
+++ b/src/rp2_common/hardware_irq/irq.c
@@ -8,12 +8,15 @@
 #include "hardware/regs/m0plus.h"
 #include "hardware/platform_defs.h"
 #include "hardware/structs/scb.h"
+#include "hardware/claim.h"
 
 #include "pico/mutex.h"
 #include "pico/assert.h"
 
 extern void __unhandled_user_irq(void);
 
+static uint8_t user_irq_claimed[NUM_CORES];
+
 static inline irq_handler_t *get_vtable(void) {
     return (irq_handler_t *) scb_hw->vtor;
 }
@@ -410,3 +413,31 @@ void irq_init_priorities() {
     }
 #endif
 }
+
+#define FIRST_USER_IRQ (NUM_IRQS - NUM_USER_IRQS)
+
+static uint get_user_irq_claim_index(uint irq_num) {
+    invalid_params_if(IRQ, irq_num < FIRST_USER_IRQ || irq_num >= NUM_IRQS);
+    // we count backwards from the last, to match the existing hard coded uses of user IRQs in the SDK which were previously using 31
+    static_assert(NUM_IRQS - FIRST_USER_IRQ <= 8, ""); // we only use a single byte's worth of claim bits today.
+    return NUM_IRQS - irq_num  - 1u;
+}
+
+void user_irq_claim(uint irq_num) {
+    hw_claim_or_assert(&user_irq_claimed[get_core_num()], get_user_irq_claim_index(irq_num), "User IRQ is already claimed");
+}
+
+void user_irq_unclaim(uint irq_num) {
+    hw_claim_clear(&user_irq_claimed[get_core_num()], get_user_irq_claim_index(irq_num));
+}
+
+int user_irq_claim_unused(bool required) {
+    int bit = hw_claim_unused_from_range(&user_irq_claimed[get_core_num()], required, 0, NUM_USER_IRQS - 1, "No user IRQs are available");
+    if (bit >= 0) bit =  (int)NUM_IRQS - bit - 1;
+    return bit;
+}
+
+bool user_irq_is_claimed(uint irq_num) {
+    return hw_is_claimed(&user_irq_claimed[get_core_num()], get_user_irq_claim_index(irq_num));
+}
+
diff --git a/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb.h b/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb.h
index c1ace0350..8ac824447 100644
--- a/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb.h
+++ b/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb.h
@@ -39,9 +39,9 @@
 #define PICO_STDIO_USB_TASK_INTERVAL_US 1000
 #endif
 
-// PICO_CONFIG: PICO_STDIO_USB_LOW_PRIORITY_IRQ, low priority (non hardware) IRQ number to claim for tud_task() background execution, default=31, advanced=true, group=pico_stdio_usb
+// PICO_CONFIG: PICO_STDIO_USB_LOW_PRIORITY_IRQ, Explicit User IRQ number to claim for tud_task() background execution instead of letting the implementation pick a free one dynamically (deprecated), advanced=true, group=pico_stdio_usb
 #ifndef PICO_STDIO_USB_LOW_PRIORITY_IRQ
-#define PICO_STDIO_USB_LOW_PRIORITY_IRQ 31
+// this variable is no longer set by default (one is claimed dynamically), but will be respected if specified
 #endif
 
 // PICO_CONFIG: PICO_STDIO_USB_ENABLE_RESET_VIA_BAUD_RATE, Enable/disable resetting into BOOTSEL mode if the host sets the baud rate to a magic value (PICO_STDIO_USB_RESET_MAGIC_BAUD_RATE), type=bool, default=1, group=pico_stdio_usb
diff --git a/src/rp2_common/pico_stdio_usb/stdio_usb.c b/src/rp2_common/pico_stdio_usb/stdio_usb.c
index 913d606c4..df3920fc8 100644
--- a/src/rp2_common/pico_stdio_usb/stdio_usb.c
+++ b/src/rp2_common/pico_stdio_usb/stdio_usb.c
@@ -13,7 +13,13 @@
 #include "pico/mutex.h"
 #include "hardware/irq.h"
 
-static_assert(PICO_STDIO_USB_LOW_PRIORITY_IRQ > RTC_IRQ, ""); // note RTC_IRQ is currently the last one
+#ifdef PICO_STDIO_USB_LOW_PRIORITY_IRQ
+static_assert(PICO_STDIO_USB_LOW_PRIORITY_IRQ >= NUM_IRQS - NUM_USER_IRQS, "");
+#define low_priority_irq_num PICO_STDIO_USB_LOW_PRIORITY_IRQ
+#else
+static uint8_t low_priority_irq_num;
+#endif
+
 static mutex_t stdio_usb_mutex;
 
 static void low_priority_worker_irq(void) {
@@ -27,7 +33,7 @@ static void low_priority_worker_irq(void) {
 }
 
 static int64_t timer_task(__unused alarm_id_t id, __unused void *user_data) {
-    irq_set_pending(PICO_STDIO_USB_LOW_PRIORITY_IRQ);
+    irq_set_pending(low_priority_irq_num);
     return PICO_STDIO_USB_TASK_INTERVAL_US;
 }
 
@@ -96,8 +102,13 @@ bool stdio_usb_init(void) {
     // initialize TinyUSB
     tusb_init();
 
-    irq_set_exclusive_handler(PICO_STDIO_USB_LOW_PRIORITY_IRQ, low_priority_worker_irq);
-    irq_set_enabled(PICO_STDIO_USB_LOW_PRIORITY_IRQ, true);
+#ifdef PICO_STDIO_USB_LOW_PRIORITY_IRQ
+    user_irq_claim(PICO_STDIO_USB_LOW_PRIORITY_IRQ);
+#else
+    low_priority_irq_num = (uint8_t) user_irq_claim_unused(true);
+#endif
+    irq_set_exclusive_handler(low_priority_irq_num, low_priority_worker_irq);
+    irq_set_enabled(low_priority_irq_num, true);
 
     mutex_init(&stdio_usb_mutex);
     bool rc = add_alarm_in_us(PICO_STDIO_USB_TASK_INTERVAL_US, timer_task, NULL, true);

From 6389927cf9aeee2952a781200af596d1024d7c18 Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Wed, 8 Jun 2022 12:59:45 -0500
Subject: [PATCH 11/51] Add some optional header includes, to make per-target
 changes to config easier (#851)

---
 src/common/pico_base/include/pico.h        | 9 +++++++++
 src/common/pico_base/include/pico/config.h | 5 +++++
 2 files changed, 14 insertions(+)

diff --git a/src/common/pico_base/include/pico.h b/src/common/pico_base/include/pico.h
index 1b7365120..073ee5fb1 100644
--- a/src/common/pico_base/include/pico.h
+++ b/src/common/pico_base/include/pico.h
@@ -16,9 +16,18 @@
  * This header may be included by assembly code
 */
 
+#define	__PICO_STRING(x)	#x
+#define	__PICO_XSTRING(x)	__PICO_STRING(x)
+
 #include "pico/types.h"
 #include "pico/version.h"
+
+// PICO_CONFIG: PICO_CONFIG_HEADER, unquoted path to header include in place of the default pico/config.h which may be desirable for build systems which can't easily generate the config_autogen header, default=none, group=pico_base
+#ifdef PICO_CONFIG_HEADER
+#include __PICO_XSTRING(PICO_CONFIG_HEADER)
+#else
 #include "pico/config.h"
+#endif
 #include "pico/platform.h"
 #include "pico/error.h"
 
diff --git a/src/common/pico_base/include/pico/config.h b/src/common/pico_base/include/pico/config.h
index 8d6926941..8526bb5cf 100644
--- a/src/common/pico_base/include/pico/config.h
+++ b/src/common/pico_base/include/pico/config.h
@@ -18,4 +18,9 @@
 
 #include "pico/config_autogen.h"
 
+// PICO_CONFIG: PICO_CONFIG_RTOS_ADAPTER_HEADER, unquoted path to header include in the default pico/config.h for RTOS integration defines that must be included in all sources, default=none, group=pico_base
+#ifdef PICO_CONFIG_RTOS_ADAPTER_HEADER
+#include __PICO_XSTRING(PICO_CONFIG_RTOS_ADAPTER_HEADER)
+#endif
+
 #endif
\ No newline at end of file

From ef47dfeeaf8c73e976bd22846c6a3b8702bc031a Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Wed, 8 Jun 2022 13:03:11 -0500
Subject: [PATCH 12/51] Add new GPIO APIs for adding shared GPIO handlers, and
 improve docs (#850)

Co-authored-by: Adam Nielsen <malvineous@shikadi.net>
---
 src/rp2_common/hardware_gpio/CMakeLists.txt   |   3 +-
 src/rp2_common/hardware_gpio/gpio.c           | 100 +++---
 .../hardware_gpio/include/hardware/gpio.h     | 287 ++++++++++++++++--
 3 files changed, 327 insertions(+), 63 deletions(-)

diff --git a/src/rp2_common/hardware_gpio/CMakeLists.txt b/src/rp2_common/hardware_gpio/CMakeLists.txt
index 1bfb078f3..97a935575 100644
--- a/src/rp2_common/hardware_gpio/CMakeLists.txt
+++ b/src/rp2_common/hardware_gpio/CMakeLists.txt
@@ -1 +1,2 @@
-pico_simple_hardware_target(gpio)
\ No newline at end of file
+pico_simple_hardware_target(gpio)
+target_link_libraries(hardware_gpio INTERFACE hardware_irq)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_gpio/gpio.c b/src/rp2_common/hardware_gpio/gpio.c
index 4197a4b92..aa6e98c21 100644
--- a/src/rp2_common/hardware_gpio/gpio.c
+++ b/src/rp2_common/hardware_gpio/gpio.c
@@ -14,11 +14,13 @@
 #include "pico/binary_info.h"
 #endif
 
-static gpio_irq_callback_t _callbacks[NUM_CORES];
+static gpio_irq_callback_t callbacks[NUM_CORES];
+// a 1 bit means the IRQ is handled by a raw IRQ handler
+static uint32_t raw_irq_mask[NUM_CORES];
 
 // Get the raw value from the pin, bypassing any muxing or overrides.
 int gpio_get_pad(uint gpio) {
-    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    check_gpio_param(gpio);
     hw_set_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS);
     return (iobank0_hw->io[gpio].status & IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS)
             >> IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB;
@@ -28,7 +30,7 @@ int gpio_get_pad(uint gpio) {
 // Select function for this GPIO, and ensure input/output are enabled at the pad.
 // This also clears the input/output/irq override bits.
 void gpio_set_function(uint gpio, enum gpio_function fn) {
-    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    check_gpio_param(gpio);
     invalid_params_if(GPIO, ((uint32_t)fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB) & ~IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS);
     // Set input enable on, output disable off
     hw_write_masked(&padsbank0_hw->io[gpio],
@@ -42,14 +44,14 @@ void gpio_set_function(uint gpio, enum gpio_function fn) {
 /// \end::gpio_set_function[]
 
 enum gpio_function gpio_get_function(uint gpio) {
-    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    check_gpio_param(gpio);
     return (enum gpio_function) ((iobank0_hw->io[gpio].ctrl & IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS) >> IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB);
 }
 
 // Note that, on RP2040, setting both pulls enables a "bus keep" function,
 // i.e. weak pull to whatever is current high/low state of GPIO.
 void gpio_set_pulls(uint gpio, bool up, bool down) {
-    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    check_gpio_param(gpio);
     hw_write_masked(
             &padsbank0_hw->io[gpio],
             (bool_to_bit(up) << PADS_BANK0_GPIO0_PUE_LSB) | (bool_to_bit(down) << PADS_BANK0_GPIO0_PDE_LSB),
@@ -59,7 +61,7 @@ void gpio_set_pulls(uint gpio, bool up, bool down) {
 
 // Direct override for per-GPIO IRQ signal
 void gpio_set_irqover(uint gpio, uint value) {
-    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    check_gpio_param(gpio);
     hw_write_masked(&iobank0_hw->io[gpio].ctrl,
                    value << IO_BANK0_GPIO0_CTRL_IRQOVER_LSB,
                    IO_BANK0_GPIO0_CTRL_IRQOVER_BITS
@@ -68,7 +70,7 @@ void gpio_set_irqover(uint gpio, uint value) {
 
 // Direct overrides for pad controls
 void gpio_set_inover(uint gpio, uint value) {
-    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    check_gpio_param(gpio);
     hw_write_masked(&iobank0_hw->io[gpio].ctrl,
                    value << IO_BANK0_GPIO0_CTRL_INOVER_LSB,
                    IO_BANK0_GPIO0_CTRL_INOVER_BITS
@@ -76,7 +78,7 @@ void gpio_set_inover(uint gpio, uint value) {
 }
 
 void gpio_set_outover(uint gpio, uint value) {
-    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    check_gpio_param(gpio);
     hw_write_masked(&iobank0_hw->io[gpio].ctrl,
                    value << IO_BANK0_GPIO0_CTRL_OUTOVER_LSB,
                    IO_BANK0_GPIO0_CTRL_OUTOVER_BITS
@@ -84,7 +86,7 @@ void gpio_set_outover(uint gpio, uint value) {
 }
 
 void gpio_set_oeover(uint gpio, uint value) {
-    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    check_gpio_param(gpio);
     hw_write_masked(&iobank0_hw->io[gpio].ctrl,
                    value << IO_BANK0_GPIO0_CTRL_OEOVER_LSB,
                    IO_BANK0_GPIO0_CTRL_OEOVER_BITS
@@ -92,7 +94,7 @@ void gpio_set_oeover(uint gpio, uint value) {
 }
 
 void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled) {
-    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    check_gpio_param(gpio);
     if (enabled)
         hw_set_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_SCHMITT_BITS);
     else
@@ -101,12 +103,12 @@ void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled) {
 
 
 bool gpio_is_input_hysteresis_enabled(uint gpio) {
-    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    check_gpio_param(gpio);
     return (padsbank0_hw->io[gpio] & PADS_BANK0_GPIO0_SCHMITT_BITS) != 0;
 }
 
 void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew) {
-    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    check_gpio_param(gpio);
     hw_write_masked(&padsbank0_hw->io[gpio],
                     (uint)slew << PADS_BANK0_GPIO0_SLEWFAST_LSB,
                     PADS_BANK0_GPIO0_SLEWFAST_BITS
@@ -114,7 +116,7 @@ void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew) {
 }
 
 enum gpio_slew_rate gpio_get_slew_rate(uint gpio) {
-    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    check_gpio_param(gpio);
     return (enum gpio_slew_rate)((padsbank0_hw->io[gpio]
             & PADS_BANK0_GPIO0_SLEWFAST_BITS)
             >> PADS_BANK0_GPIO0_SLEWFAST_LSB);
@@ -124,7 +126,7 @@ enum gpio_slew_rate gpio_get_slew_rate(uint gpio) {
 // Enum encoding should match hardware encoding on RP2040
 static_assert(PADS_BANK0_GPIO0_DRIVE_VALUE_8MA == GPIO_DRIVE_STRENGTH_8MA, "");
 void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive) {
-    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    check_gpio_param(gpio);
     hw_write_masked(&padsbank0_hw->io[gpio],
                     (uint)drive << PADS_BANK0_GPIO0_DRIVE_LSB,
                     PADS_BANK0_GPIO0_DRIVE_BITS
@@ -132,25 +134,28 @@ void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive) {
 }
 
 enum gpio_drive_strength gpio_get_drive_strength(uint gpio) {
-    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    check_gpio_param(gpio);
     return (enum gpio_drive_strength)((padsbank0_hw->io[gpio]
             & PADS_BANK0_GPIO0_DRIVE_BITS)
             >> PADS_BANK0_GPIO0_DRIVE_LSB);
 }
 
-static void gpio_irq_handler(void) {
-    io_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ?
-                                           &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl;
-    for (uint gpio = 0; gpio < NUM_BANK0_GPIOS; gpio++) {
-        io_ro_32 *status_reg = &irq_ctrl_base->ints[gpio / 8];
-        uint events = (*status_reg >> 4 * (gpio % 8)) & 0xf;
-        if (events) {
-            // TODO: If both cores care about this event then the second core won't get the irq?
-            gpio_acknowledge_irq(gpio, events);
-            gpio_irq_callback_t callback = _callbacks[get_core_num()];
-            if (callback) {
-                callback(gpio, events);
+static void gpio_default_irq_handler(void) {
+    uint core = get_core_num();
+    gpio_irq_callback_t callback = callbacks[core];
+    io_irq_ctrl_hw_t *irq_ctrl_base = core ? &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl;
+    for (uint gpio = 0; gpio < NUM_BANK0_GPIOS; gpio+=8) {
+        uint32_t events8 = irq_ctrl_base->ints[gpio >> 3u];
+        // note we assume events8 is 0 for non-existent GPIO
+        for(uint i=gpio;events8 && i<gpio+8;i++) {
+            uint32_t events = events8 & 0xfu;
+            if (events && !(raw_irq_mask[core] & (1u << i))) {
+                gpio_acknowledge_irq(i, events);
+                if (callback) {
+                    callback(gpio, events);
+                }
             }
+            events8 >>= 4;
         }
     }
 }
@@ -178,21 +183,48 @@ void gpio_set_irq_enabled(uint gpio, uint32_t events, bool enabled) {
 
 void gpio_set_irq_enabled_with_callback(uint gpio, uint32_t events, bool enabled, gpio_irq_callback_t callback) {
     gpio_set_irq_enabled(gpio, events, enabled);
+    gpio_set_irq_callback(callback);
+    if (enabled) irq_set_enabled(IO_IRQ_BANK0, true);
+}
+
+void gpio_set_irq_callback(gpio_irq_callback_t callback) {
+    uint core = get_core_num();
+    if (callbacks[core]) {
+        if (!callback) {
+            irq_remove_handler(IO_IRQ_BANK0, gpio_default_irq_handler);
+        }
+        callbacks[core] = callback;
+    } else if (callback) {
+        callbacks[core] = callback;
+        irq_add_shared_handler(IO_IRQ_BANK0, gpio_default_irq_handler, GPIO_IRQ_CALLBACK_ORDER_PRIORITY);
+    }
+}
+
+void gpio_add_raw_irq_handler_with_order_priority_masked(uint gpio_mask, irq_handler_t handler, uint8_t order_priority) {
+    hard_assert(!(raw_irq_mask[get_core_num()] & gpio_mask)); // should not add multiple handlers for the same event
+    raw_irq_mask[get_core_num()] |= gpio_mask;
+    irq_add_shared_handler(IO_IRQ_BANK0, handler, order_priority);
+}
+
+void gpio_add_raw_irq_handler_masked(uint gpio_mask, irq_handler_t handler) {
+    gpio_add_raw_irq_handler_with_order_priority_masked(gpio_mask, handler, GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY);
+}
 
-    // TODO: Do we want to support a callback per GPIO pin?
-    // Install IRQ handler
-    _callbacks[get_core_num()] = callback;
-    irq_set_exclusive_handler(IO_IRQ_BANK0, gpio_irq_handler);
-    irq_set_enabled(IO_IRQ_BANK0, true);
+void gpio_remove_raw_irq_handler_masked(uint gpio_mask, irq_handler_t handler) {
+    assert(raw_irq_mask[get_core_num()] & gpio_mask); // should not remove handlers that are not added
+    irq_remove_handler(IO_IRQ_BANK0, handler);
+    raw_irq_mask[get_core_num()] &= ~gpio_mask;
 }
 
 void gpio_set_dormant_irq_enabled(uint gpio, uint32_t events, bool enabled) {
+    check_gpio_param(gpio);
     io_irq_ctrl_hw_t *irq_ctrl_base = &iobank0_hw->dormant_wake_irq_ctrl;
     _gpio_set_irq_enabled(gpio, events, enabled, irq_ctrl_base);
 }
 
 void gpio_acknowledge_irq(uint gpio, uint32_t events) {
-    iobank0_hw->intr[gpio / 8] = events << 4 * (gpio % 8);
+    check_gpio_param(gpio);
+    iobank0_hw->intr[gpio / 8] = events << (4 * (gpio % 8));
 }
 
 #define DEBUG_PIN_MASK (((1u << PICO_DEBUG_PIN_COUNT)-1) << PICO_DEBUG_PIN_BASE)
@@ -222,7 +254,7 @@ void gpio_deinit(uint gpio) {
 }
 
 void gpio_init_mask(uint gpio_mask) {
-    for(uint i=0;i<32;i++) {
+    for(uint i=0;i<NUM_BANK0_GPIOS;i++) {
         if (gpio_mask & 1) {
             gpio_init(i);
         }
diff --git a/src/rp2_common/hardware_gpio/include/hardware/gpio.h b/src/rp2_common/hardware_gpio/include/hardware/gpio.h
index 24b4e5c24..09a9b96a6 100644
--- a/src/rp2_common/hardware_gpio/include/hardware/gpio.h
+++ b/src/rp2_common/hardware_gpio/include/hardware/gpio.h
@@ -11,6 +11,7 @@
 #include "hardware/structs/sio.h"
 #include "hardware/structs/padsbank0.h"
 #include "hardware/structs/iobank0.h"
+#include "hardware/irq.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -103,7 +104,7 @@ enum gpio_function {
 #define GPIO_OUT 1
 #define GPIO_IN 0
 
-/*! \brief  GPIO Interrupt level definitions
+/*! \brief  GPIO Interrupt level definitions (GPIO events)
  *  \ingroup hardware_gpio
  *  \brief GPIO Interrupt levels
  *
@@ -129,10 +130,11 @@ enum gpio_irq_level {
  *  \ingroup hardware_gpio
  *
  * \param gpio Which GPIO caused this interrupt
- * \param events Which events caused this interrupt. See \ref gpio_set_irq_enabled for details.
+ * \param event_mask Which events caused this interrupt. See \ref gpio_irq_level for details.
  * \sa gpio_set_irq_enabled_with_callback()
+ * \sa gpio_set_irq_callback()
  */
-typedef void (*gpio_irq_callback_t)(uint gpio, uint32_t events);
+typedef void (*gpio_irq_callback_t)(uint gpio, uint32_t event_mask);
 
 enum gpio_override {
     GPIO_OVERRIDE_NORMAL = 0,      ///< peripheral signal selected via \ref gpio_set_function
@@ -166,6 +168,10 @@ enum gpio_drive_strength {
     GPIO_DRIVE_STRENGTH_12MA = 3 ///< 12 mA nominal drive strength
 };
 
+static inline void check_gpio_param(__unused uint gpio) {
+    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+}
+
 // ----------------------------------------------------------------------------
 // Pad Controls + IO Muxing
 // ----------------------------------------------------------------------------
@@ -347,63 +353,288 @@ void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive);
  */
 enum gpio_drive_strength gpio_get_drive_strength(uint gpio);
 
-/*! \brief Enable or disable interrupts for specified GPIO
+/*! \brief Enable or disable specific interrupt events for specified GPIO
  *  \ingroup hardware_gpio
  *
- * \note The IO IRQs are independent per-processor. This configures IRQs for
+ * This function sets which GPIO events cause a GPIO interrupt on the calling core. See
+ * \ref gpio_set_irq_callback, \ref gpio_set_irq_enabled_with_callback and
+ * \ref gpio_add_raw_irq_handler to set up a GPIO interrupt handler to handle the events.
+ *
+ * \note The IO IRQs are independent per-processor. This configures the interrupt events for
  * the processor that calls the function.
  *
  * \param gpio GPIO number
- * \param events Which events will cause an interrupt
+ * \param event_mask Which events will cause an interrupt
  * \param enabled Enable or disable flag
  *
- * Events is a bitmask of the following:
+ * Events is a bitmask of the following \ref gpio_irq_level values:
  *
- * bit | interrupt
- * ----|----------
- *   0 | Low level
- *   1 | High level
- *   2 | Edge low
- *   3 | Edge high
+ * bit | constant            | interrupt
+ * ----|----------------------------------------------------------
+ *   0 | GPIO_IRQ_LEVEL_LOW  | Continuously while level is low
+ *   1 | GPIO_IRQ_LEVEL_HIGH | Continuously while level is high
+ *   2 | GPIO_IRQ_EDGE_FALL  | On each transition from high to low
+ *   3 | GPIO_IRQ_EDGE_RISE  | On each transition from low to high
+ *
+ * which are specified in \ref gpio_irq_level
  */
-void gpio_set_irq_enabled(uint gpio, uint32_t events, bool enabled);
+void gpio_set_irq_enabled(uint gpio, uint32_t event_mask, bool enabled);
+
+// PICO_CONFIG: GPIO_IRQ_CALLBACK_ORDER_PRIORITY, the irq priority order of the default IRQ callback, min=0, max=255, default=PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY, group=hardware_gpio
+#ifndef GPIO_IRQ_CALLBACK_ORDER_PRIORITY
+#define GPIO_IRQ_CALLBACK_ORDER_PRIORITY PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY
+#endif
 
-/*! \brief Enable interrupts for specified GPIO
+// PICO_CONFIG: GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, the irq priority order of raw IRQ handlers if the priortiy is not specified, min=0, max=255, default=PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, group=hardware_gpio
+#ifndef GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY
+#define GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY
+#endif
+
+/*! \brief Set the generic callback used for GPIO IRQ events for the current core
  *  \ingroup hardware_gpio
  *
- * \note The IO IRQs are independent per-processor. This configures IRQs for
+ * This function sets the callback used for all GPIO IRQs on the current core that are not explicitly
+ * hooked via \ref gpio_add_raw_irq_handler or other gpio_add_raw_irq_handler_ functions.
+ *
+ * This function is called with the GPIO number and event mask for each of the (not explicitly hooked)
+ * GPIOs that have events enabled and that are pending (see \ref gpio_get_irq_event_mask).
+ *
+ * \note The IO IRQs are independent per-processor. This function affects
  * the processor that calls the function.
  *
- * \param gpio GPIO number
- * \param events Which events will cause an interrupt. See \ref gpio_set_irq_enabled for details.
- * \param enabled Enable or disable flag
- * \param callback user function to call on GPIO irq. Note only one of these can be set per processor.
+ * \param callback default user function to call on GPIO irq. Note only one of these can be set per processor.
+ */
+void gpio_set_irq_callback(gpio_irq_callback_t callback);
+
+/*! \brief Convenience function which performs multiple GPIO IRQ related initializations
+ *  \ingroup hardware_gpio
+ *
+ * This method is a slightly eclectic mix of initialization, that:
+ *
+ * \li Updates whether the specified events for the specified GPIO causes an interrupt on the calling core based
+ * on the enable flag.
+ *
+ * \li Sets the callback handler for the calling core to callback (or clears the handler if the callback is NULL).
+ *
+ * \li Enables GPIO IRQs on the current core if enabled is true.
+ *
+ * This method is commonly used to perform a one time setup, and following that any additional IRQs/events are enabled
+ * via \ref gpio_set_irq_enabled. All GPIOs/events added in this way on the same core share the same callback; for multiple
+ * independent handlers for different GPIOs you should use \ref gpio_add_raw_irq_handler and related functions.
+ *
+ * This method is equivalent to:
  *
- * \note Currently the GPIO parameter is ignored, and this callback will be called for any enabled GPIO IRQ on any pin.
+ * \code{.c}
+ * gpio_set_irq_enabled(gpio, event_mask, enabled);
+ * gpio_set_irq_callback(callback);
+ * if (enabled) irq_set_enabled(IO_IRQ_BANK0, true);
+ * \endcode
  *
+ * \note The IO IRQs are independent per-processor. This method affects only the processor that calls the function.
+ *
+ * \param gpio GPIO number
+ * \param event_mask Which events will cause an interrupt. See \ref gpio_irq_level for details.
+ * \param enabled Enable or disable flag
+ * \param callback user function to call on GPIO irq. if NULL, the callback is removed
  */
-void gpio_set_irq_enabled_with_callback(uint gpio, uint32_t events, bool enabled, gpio_irq_callback_t callback);
+void gpio_set_irq_enabled_with_callback(uint gpio, uint32_t event_mask, bool enabled, gpio_irq_callback_t callback);
 
-/*! \brief Enable dormant wake up interrupt for specified GPIO
+/*! \brief Enable dormant wake up interrupt for specified GPIO and events
  *  \ingroup hardware_gpio
  *
  * This configures IRQs to restart the XOSC or ROSC when they are
  * disabled in dormant mode
  *
  * \param gpio GPIO number
- * \param events Which events will cause an interrupt. See \ref gpio_set_irq_enabled for details.
+ * \param event_mask Which events will cause an interrupt. See \ref gpio_irq_level for details.
  * \param enabled Enable/disable flag
  */
-void gpio_set_dormant_irq_enabled(uint gpio, uint32_t events, bool enabled);
+void gpio_set_dormant_irq_enabled(uint gpio, uint32_t event_mask, bool enabled);
+
+/*! \brief Return the current interrupt status (pending events) for the given GPIO
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \return Bitmask of events that are currently pending for the GPIO. See \ref gpio_irq_level for details.
+ * \sa gpio_acknowledge_irq
+ */
+static inline uint32_t gpio_get_irq_event_mask(uint gpio) {
+    check_gpio_param(gpio);
+    io_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ?
+                                      &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl;
+    io_ro_32 *status_reg = &irq_ctrl_base->ints[gpio >> 3u];
+    return (*status_reg >> (4 * (gpio & 7u))) & 0xfu;
+}
 
-/*! \brief Acknowledge a GPIO interrupt
+/*! \brief Acknowledge a GPIO interrupt for the specified events on the calling core
  *  \ingroup hardware_gpio
  *
+ * \note This may be called with a mask of any of valid bits specified in \ref gpio_irq_level, however
+ * it has no effect on \a level sensitive interrupts which remain pending while the GPIO is at the specified
+ * level. When handling \a level sensitive interrupts, you should generally disable the interrupt (see
+ * \ref gpio_set_irq_enabled) and then set it up again later once the GPIO level has changed (or to catch
+ * the opposite level).
+ *
  * \param gpio GPIO number
  * \param events Bitmask of events to clear. See \ref gpio_set_irq_enabled for details.
-  *
+ *
+ * \note For callbacks set with \ref gpio_set_irq_enabled_with_callback, or \ref gpio_set_irq_callback,this function is called automatically.
+ * \param event_mask Bitmask of events to clear. See \ref gpio_irq_level for details.
+ */
+void gpio_acknowledge_irq(uint gpio, uint32_t event_mask);
+
+/*! \brief Adds a raw GPIO IRQ handler for the specified GPIOs on the current core
+ *  \ingroup hardware_gpio
+ *
+ * In addition to the default mechanism of a single GPIO IRQ event callback per core (see \ref gpio_set_irq_callback),
+ * it is possible to add explicit GPIO IRQ handlers which are called independent of the default callback. The order
+ * relative to the default callback can be controlled via the order_priority parameter (the default callback has the priority
+ * \ref GPIO_IRQ_CALLBACK_ORDER_PRIORITY which defaults to the lowest priority with the intention of it running last).
+ *
+ * This method adds such an explicit GPIO IRQ handler, and disables the "default" callback for the specified GPIOs.
+ *
+ * \note Multiple raw handlers should not be added for the same GPIOs, and this method will assert if you attempt to.
+ *
+ * A raw handler should check for whichever GPIOs and events it handles, and acknowledge them itself; it might look something like:
+ *
+ * \code{.c}
+ * void my_irq_handler(void) {
+ *     if (gpio_get_irq_event_mask(my_gpio_num) & my_gpio_event_mask) {
+ *        gpio_acknowledge_irq(my_gpio_num, my_gpio_event_mask);
+ *       // handle the IRQ
+ *     }
+ *     if (gpio_get_irq_event_mask(my_gpio_num2) & my_gpio_event_mask2) {
+ *        gpio_acknowledge_irq(my_gpio_num2, my_gpio_event_mask2);
+ *       // handle the IRQ
+ *     }
+ * }
+ * \endcode
+ *
+ * @param gpio_mask a bit mask of the GPIO numbers that will no longer be passed to the default callback for this core
+ * @param handler the handler to add to the list of GPIO IRQ handlers for this core
+ * @param order_priority the priority order to determine the relative position of the handler in the list of GPIO IRQ handlers for this core.
+ */
+void gpio_add_raw_irq_handler_with_order_priority_masked(uint gpio_mask, irq_handler_t handler, uint8_t order_priority);
+
+/*! \brief Adds a raw GPIO IRQ handler for a specific GPIO on the current core
+ *  \ingroup hardware_gpio
+ *
+ * In addition to the default mechanism of a single GPIO IRQ event callback per core (see \ref gpio_set_irq_callback),
+ * it is possible to add explicit GPIO IRQ handlers which are called independent of the default callback. The order
+ * relative to the default callback can be controlled via the order_priority parameter(the default callback has the priority
+ * \ref GPIO_IRQ_CALLBACK_ORDER_PRIORITY which defaults to the lowest priority with the intention of it running last).
+ *
+ * This method adds such a callback, and disables the "default" callback for the specified GPIO.
+ *
+ * \note Multiple raw handlers should not be added for the same GPIO, and this method will assert if you attempt to.
+ *
+ * A raw handler should check for whichever GPIOs and events it handles, and acknowledge them itself; it might look something like:
+ *
+ * \code{.c}
+ * void my_irq_handler(void) {
+ *     if (gpio_get_irq_event_mask(my_gpio_num) & my_gpio_event_mask) {
+ *        gpio_acknowledge_irq(my_gpio_num, my_gpio_event_mask);
+ *       // handle the IRQ
+ *     }
+ * }
+ * \endcode
+ *
+ * @param gpio the GPIO number that will no longer be passed to the default callback for this core
+ * @param handler the handler to add to the list of GPIO IRQ handlers for this core
+ * @param order_priority the priority order to determine the relative position of the handler in the list of GPIO IRQ handlers for this core.
  */
-void gpio_acknowledge_irq(uint gpio, uint32_t events);
+static inline void gpio_add_raw_irq_handler_with_order_priority(uint gpio, irq_handler_t handler, uint8_t order_priority) {
+    check_gpio_param(gpio);
+    gpio_add_raw_irq_handler_with_order_priority_masked(1u << gpio, handler, order_priority);
+}
+
+/*! \brief Adds a raw GPIO IRQ handler for the specified GPIOs on the current core
+ *  \ingroup hardware_gpio
+ *
+ * In addition to the default mechanism of a single GPIO IRQ event callback per core (see \ref gpio_set_irq_callback),
+ * it is possible to add explicit GPIO IRQ handlers which are called independent of the default event callback.
+ *
+ * This method adds such a callback, and disables the "default" callback for the specified GPIOs.
+ *
+ * \note Multiple raw handlers should not be added for the same GPIOs, and this method will assert if you attempt to.
+ *
+ * A raw handler should check for whichever GPIOs and events it handles, and acknowledge them itself; it might look something like:
+ *
+ * \code{.c}
+ * void my_irq_handler(void) {
+ *     if (gpio_get_irq_event_mask(my_gpio_num) & my_gpio_event_mask) {
+ *        gpio_acknowledge_irq(my_gpio_num, my_gpio_event_mask);
+ *       // handle the IRQ
+ *     }
+ *     if (gpio_get_irq_event_mask(my_gpio_num2) & my_gpio_event_mask2) {
+ *        gpio_acknowledge_irq(my_gpio_num2, my_gpio_event_mask2);
+ *       // handle the IRQ
+ *     }
+ * }
+ * \endcode
+ *
+ * @param gpio_mask a bit mask of the GPIO numbers that will no longer be passed to the default callback for this core
+ * @param handler the handler to add to the list of GPIO IRQ handlers for this core
+ */
+void gpio_add_raw_irq_handler_masked(uint gpio_mask, irq_handler_t handler);
+
+/*! \brief Adds a raw GPIO IRQ handler for a specific GPIO on the current core
+ *  \ingroup hardware_gpio
+ *
+ * In addition to the default mechanism of a single GPIO IRQ event callback per core (see \ref gpio_set_irq_callback),
+ * it is possible to add explicit GPIO IRQ handlers which are called independent of the default event callback.
+ *
+ * This method adds such a callback, and disables the "default" callback for the specified GPIO.
+ *
+ * \note Multiple raw handlers should not be added for the same GPIO, and this method will assert if you attempt to.
+ *
+ * A raw handler should check for whichever GPIOs and events it handles, and acknowledge them itself; it might look something like:
+ *
+ * \code{.c}
+ * void my_irq_handler(void) {
+ *     if (gpio_get_irq_event_mask(my_gpio_num) & my_gpio_event_mask) {
+ *        gpio_acknowledge_irq(my_gpio_num, my_gpio_event_mask);
+ *       // handle the IRQ
+ *     }
+ * }
+ * \endcode
+ *
+ * @param gpio the GPIO number that will no longer be passed to the default callback for this core
+ * @param handler the handler to add to the list of GPIO IRQ handlers for this core
+ */
+static inline void gpio_add_raw_irq_handler(uint gpio, irq_handler_t handler) {
+    check_gpio_param(gpio);
+    gpio_add_raw_irq_handler_masked(1u << gpio, handler);
+}
+
+/*! \brief Removes a raw GPIO IRQ handler for the specified GPIOs on the current core
+ *  \ingroup hardware_gpio
+ *
+ * In addition to the default mechanism of a single GPIO IRQ event callback per core (see \ref gpio_set_irq_callback),
+ * it is possible to add explicit GPIO IRQ handlers which are called independent of the default event callback.
+ *
+ * This method removes such a callback, and enables the "default" callback for the specified GPIOs.
+ *
+ * @param gpio_mask a bit mask of the GPIO numbers that will now be passed to the default callback for this core
+ * @param handler the handler to remove from the list of GPIO IRQ handlers for this core
+ */
+void gpio_remove_raw_irq_handler_masked(uint gpio_mask, irq_handler_t handler);
+
+/*! \brief Removes a raw GPIO IRQ handler for the specified GPIO on the current core
+ *  \ingroup hardware_gpio
+ *
+ * In addition to the default mechanism of a single GPIO IRQ event callback per core (see \ref gpio_set_irq_callback),
+ * it is possible to add explicit GPIO IRQ handlers which are called independent of the default event callback.
+ *
+ * This method removes such a callback, and enables the "default" callback for the specified GPIO.
+ *
+ * @param gpio the GPIO number that will now be passed to the default callback for this core
+ * @param handler the handler to remove from the list of GPIO IRQ handlers for this core
+ */
+static inline void gpio_remove_raw_irq_handler(uint gpio, irq_handler_t handler) {
+    check_gpio_param(gpio);
+    gpio_remove_raw_irq_handler_masked(1u << gpio, handler);
+}
 
 /*! \brief Initialise a GPIO for (enabled I/O and set func to GPIO_FUNC_SIO)
  *  \ingroup hardware_gpio

From 672e48e9e9d1e0870892ca620b6300dbcf5fdc2d Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Wed, 8 Jun 2022 13:23:36 -0500
Subject: [PATCH 13/51] Add sem_try_acquire(). Fixes #846 (#856)

Co-authored-by: Geoff Simmons <geoff@uplex.de>
---
 src/common/pico_sync/include/pico/sem.h | 11 ++++++++++
 src/common/pico_sync/sem.c              | 11 ++++++++++
 test/CMakeLists.txt                     |  3 ++-
 test/pico_sem_test/CMakeLists.txt       |  4 ++++
 test/pico_sem_test/pico_sem_test.c      | 29 +++++++++++++++++++++++++
 5 files changed, 57 insertions(+), 1 deletion(-)
 create mode 100644 test/pico_sem_test/CMakeLists.txt
 create mode 100644 test/pico_sem_test/pico_sem_test.c

diff --git a/src/common/pico_sync/include/pico/sem.h b/src/common/pico_sync/include/pico/sem.h
index 6244e3246..f9f724b46 100644
--- a/src/common/pico_sync/include/pico/sem.h
+++ b/src/common/pico_sync/include/pico/sem.h
@@ -122,6 +122,17 @@ bool sem_acquire_timeout_us(semaphore_t *sem, uint32_t timeout_us);
  */
 bool sem_acquire_block_until(semaphore_t *sem, absolute_time_t until);
 
+/*! \brief Attempt to acquire a permit from a semaphore without blocking
+ *  \ingroup sem
+ *
+ * This function will return false without blocking if no permits are
+ * available, otherwise it will acquire a permit and return true.
+ *
+ * \param sem Pointer to semaphore structure
+ * \return true if permit was acquired.
+ */
+bool sem_try_acquire(semaphore_t *sem);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/common/pico_sync/sem.c b/src/common/pico_sync/sem.c
index 06b4946ef..5578a49b1 100644
--- a/src/common/pico_sync/sem.c
+++ b/src/common/pico_sync/sem.c
@@ -52,6 +52,17 @@ bool __time_critical_func(sem_acquire_block_until)(semaphore_t *sem, absolute_ti
     } while (true);
 }
 
+bool __time_critical_func(sem_try_acquire)(semaphore_t *sem) {
+    uint32_t save = spin_lock_blocking(sem->core.spin_lock);
+    if (sem->permits > 0) {
+        sem->permits--;
+        lock_internal_spin_unlock_with_notify(&sem->core, save);
+        return true;
+    }
+    spin_unlock(sem->core.spin_lock, save);
+    return false;
+}
+
 // todo this should really have a blocking variant for when permits are maxed out
 bool __time_critical_func(sem_release)(semaphore_t *sem) {
     uint32_t save = spin_lock_blocking(sem->core.spin_lock);
diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt
index 73966057c..a61388a58 100644
--- a/test/CMakeLists.txt
+++ b/test/CMakeLists.txt
@@ -9,4 +9,5 @@ if (PICO_ON_DEVICE)
     add_subdirectory(hardware_irq_test)
     add_subdirectory(hardware_pwm_test)
     add_subdirectory(cmsis_test)
-endif()
\ No newline at end of file
+    add_subdirectory(pico_sem_test)
+endif()
diff --git a/test/pico_sem_test/CMakeLists.txt b/test/pico_sem_test/CMakeLists.txt
new file mode 100644
index 000000000..786963c37
--- /dev/null
+++ b/test/pico_sem_test/CMakeLists.txt
@@ -0,0 +1,4 @@
+add_executable(pico_sem_test pico_sem_test.c)
+
+target_link_libraries(pico_sem_test PRIVATE pico_test pico_sync)
+pico_add_extra_outputs(pico_sem_test)
diff --git a/test/pico_sem_test/pico_sem_test.c b/test/pico_sem_test/pico_sem_test.c
new file mode 100644
index 000000000..8647c195f
--- /dev/null
+++ b/test/pico_sem_test/pico_sem_test.c
@@ -0,0 +1,29 @@
+/**
+ * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+
+#include "pico/sem.h"
+#include "pico/test.h"
+#include "pico/stdio.h"
+
+PICOTEST_MODULE_NAME("SEM", "semaphore test");
+
+int main() {
+    semaphore_t sem;
+
+    stdio_init_all();
+    sem_init(&sem, 1, 1);
+
+    PICOTEST_START();
+
+    PICOTEST_START_SECTION("sem_try_acquire");
+        PICOTEST_CHECK(sem_try_acquire(&sem), "available permit not acquired");
+        PICOTEST_CHECK(!sem_try_acquire(&sem), "success with no permits");
+    PICOTEST_END_SECTION();
+
+    PICOTEST_END_TEST();
+}

From 6c19d20aa5d6ced2b83a426a55bd19c24b416f2e Mon Sep 17 00:00:00 2001
From: Andrew Scheller <github@loowis.durge.org>
Date: Mon, 13 Jun 2022 15:48:01 +0100
Subject: [PATCH 14/51] Fix up filename displayed by extract_config.py when an
 invalid attribute is found (#853)

(and tidy up the code a bit at the same time)
---
 tools/extract_configs.py | 27 ++++++++++++++++-----------
 1 file changed, 16 insertions(+), 11 deletions(-)

diff --git a/tools/extract_configs.py b/tools/extract_configs.py
index e45ae7c28..0c6942aeb 100755
--- a/tools/extract_configs.py
+++ b/tools/extract_configs.py
@@ -38,7 +38,7 @@
 
 
 
-def ValidateAttrs(config_attrs):
+def ValidateAttrs(config_attrs, file_path, linenum):
     _type = config_attrs.get('type', 'int')
 
     # Validate attrs
@@ -192,26 +192,31 @@ def ValidateAttrs(config_attrs):
         if val in all_defines:
             resolved_defines[d] = all_defines[val]
 
-for config_name in all_configs:
+for config_name, config_obj in all_configs.items():
+    file_path = os.path.join(scandir, config_obj['filename'])
+    linenum = config_obj['line_number']
 
-    ValidateAttrs(all_configs[config_name]['attrs'])
+    ValidateAttrs(config_obj['attrs'], file_path, linenum)
 
     # Check that default values match up
-    if 'default' in all_configs[config_name]['attrs']:
+    if 'default' in config_obj['attrs']:
+        config_default = config_obj['attrs']['default']
         if config_name in all_defines:
-            if all_configs[config_name]['attrs']['default'] not in all_defines[config_name] and (config_name not in resolved_defines or all_configs[config_name]['attrs']['default'] not in resolved_defines[config_name]):
-                if '/' in all_configs[config_name]['attrs']['default'] or ' ' in all_configs[config_name]['attrs']['default']:
+            defines_obj = all_defines[config_name]
+            if config_default not in defines_obj and (config_name not in resolved_defines or config_default not in resolved_defines[config_name]):
+                if '/' in config_default or ' ' in config_default:
                     continue
                 # There _may_ be multiple matching defines, but arbitrarily display just one in the error message
-                first_define_value = list(all_defines[config_name].keys())[0]
-                raise Exception('Found {} at {}:{} with a default of {}, but #define says {} (at {}:{})'.format(config_name, os.path.join(scandir, all_configs[config_name]['filename']), all_configs[config_name]['line_number'], all_configs[config_name]['attrs']['default'], first_define_value, all_defines[config_name][first_define_value][0], all_defines[config_name][first_define_value][1]))
+                first_define_value = list(defines_obj.keys())[0]
+                first_define_file_path, first_define_linenum = defines_obj[first_define_value]
+                raise Exception('Found {} at {}:{} with a default of {}, but #define says {} (at {}:{})'.format(config_name, file_path, linenum, config_default, first_define_value, first_define_file_path, first_define_linenum))
         else:
-            raise Exception('Found {} at {}:{} with a default of {}, but no matching #define found'.format(config_name, os.path.join(scandir, all_configs[config_name]['filename']), all_configs[config_name]['line_number'], all_configs[config_name]['attrs']['default']))
+            raise Exception('Found {} at {}:{} with a default of {}, but no matching #define found'.format(config_name, file_path, linenum, config_default))
 
 with open(outfile, 'w', newline='') as csvfile:
     fieldnames = ('name', 'location', 'description', 'type') + tuple(sorted(all_attrs - set(['type'])))
     writer = csv.DictWriter(csvfile, fieldnames=fieldnames, extrasaction='ignore', dialect='excel-tab')
 
     writer.writeheader()
-    for config_name in sorted(all_configs):
-        writer.writerow({'name': config_name, 'location': '{}:{}'.format(all_configs[config_name]['filename'], all_configs[config_name]['line_number']), 'description': all_configs[config_name]['description'], **all_configs[config_name]['attrs']})
+    for config_name, config_obj in sorted(all_configs.items()):
+        writer.writerow({'name': config_name, 'location': '{}:{}'.format(config_obj['filename'], config_obj['line_number']), 'description': config_obj['description'], **config_obj['attrs']})

From babc4a17944327dbed360c5bd7b2117fee0f0609 Mon Sep 17 00:00:00 2001
From: Andrew Scheller <github@loowis.durge.org>
Date: Mon, 13 Jun 2022 15:49:43 +0100
Subject: [PATCH 15/51] Remove 'default=none' from PICO_CONFIG lines (#865)

---
 src/common/pico_base/include/pico.h        | 2 +-
 src/common/pico_base/include/pico/config.h | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/common/pico_base/include/pico.h b/src/common/pico_base/include/pico.h
index 073ee5fb1..784566e03 100644
--- a/src/common/pico_base/include/pico.h
+++ b/src/common/pico_base/include/pico.h
@@ -22,7 +22,7 @@
 #include "pico/types.h"
 #include "pico/version.h"
 
-// PICO_CONFIG: PICO_CONFIG_HEADER, unquoted path to header include in place of the default pico/config.h which may be desirable for build systems which can't easily generate the config_autogen header, default=none, group=pico_base
+// PICO_CONFIG: PICO_CONFIG_HEADER, unquoted path to header include in place of the default pico/config.h which may be desirable for build systems which can't easily generate the config_autogen header, group=pico_base
 #ifdef PICO_CONFIG_HEADER
 #include __PICO_XSTRING(PICO_CONFIG_HEADER)
 #else
diff --git a/src/common/pico_base/include/pico/config.h b/src/common/pico_base/include/pico/config.h
index 8526bb5cf..10a9c6af3 100644
--- a/src/common/pico_base/include/pico/config.h
+++ b/src/common/pico_base/include/pico/config.h
@@ -18,9 +18,9 @@
 
 #include "pico/config_autogen.h"
 
-// PICO_CONFIG: PICO_CONFIG_RTOS_ADAPTER_HEADER, unquoted path to header include in the default pico/config.h for RTOS integration defines that must be included in all sources, default=none, group=pico_base
+// PICO_CONFIG: PICO_CONFIG_RTOS_ADAPTER_HEADER, unquoted path to header include in the default pico/config.h for RTOS integration defines that must be included in all sources, group=pico_base
 #ifdef PICO_CONFIG_RTOS_ADAPTER_HEADER
 #include __PICO_XSTRING(PICO_CONFIG_RTOS_ADAPTER_HEADER)
 #endif
 
-#endif
\ No newline at end of file
+#endif

From bdd97466357549c20d79e4740913f09e1656652f Mon Sep 17 00:00:00 2001
From: Luke Wren <wren6991@gmail.com>
Date: Fri, 17 Jun 2022 15:50:12 +0100
Subject: [PATCH 16/51] Don't copy .data for NO_FLASH binaries, as it's loaded
 in-place (#859)

---
 src/rp2_common/pico_standard_link/crt0.S | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/rp2_common/pico_standard_link/crt0.S b/src/rp2_common/pico_standard_link/crt0.S
index f57ddfdef..b2992f65f 100644
--- a/src/rp2_common/pico_standard_link/crt0.S
+++ b/src/rp2_common/pico_standard_link/crt0.S
@@ -225,6 +225,9 @@ _reset_handler:
     cmp r0, #0
     bne hold_non_core0_in_bootrom
 
+    // In a NO_FLASH binary, don't perform .data copy, since it's loaded
+    // in-place by the SRAM load. Still need to clear .bss
+#if !PICO_NO_FLASH
     adr r4, data_cpy_table
 
     // assume there is at least one entry
@@ -235,6 +238,7 @@ _reset_handler:
     bl data_cpy
     b 1b
 2:
+#endif
 
     // Zero out the BSS
     ldr r1, =__bss_start__
@@ -266,6 +270,7 @@ _exit:
     bkpt #0
     b 1b
 
+#if !PICO_NO_FLASH
 data_cpy_loop:
     ldm r1!, {r0}
     stm r2!, {r0}
@@ -273,6 +278,10 @@ data_cpy:
     cmp r2, r3
     blo data_cpy_loop
     bx lr
+#endif
+
+// Note the data copy table is still included for NO_FLASH builds, even though
+// we skip the copy, because it is listed in binary info
 
 .align 2
 data_cpy_table:

From 705b5cedcdfaa3c5b8b6c2718010f2c8c162855d Mon Sep 17 00:00:00 2001
From: "Earle F. Philhower, III" <earlephilhower@yahoo.com>
Date: Fri, 17 Jun 2022 07:50:53 -0700
Subject: [PATCH 17/51] Wrap realloc() call with malloc_mutex in multicore
 (#864)

Protect against heap corruption by mutex-protecting the realloc() call
(like malloc/free are already).

Fixes #863
Fixes https://github.com/maxgerhardt/platform-raspberrypi/issues/7
Fixes https://github.com/earlephilhower/arduino-pico/issues/614
---
 src/rp2_common/pico_malloc/CMakeLists.txt |  1 +
 src/rp2_common/pico_malloc/pico_malloc.c  | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/src/rp2_common/pico_malloc/CMakeLists.txt b/src/rp2_common/pico_malloc/CMakeLists.txt
index deeb30f3f..57ac26784 100644
--- a/src/rp2_common/pico_malloc/CMakeLists.txt
+++ b/src/rp2_common/pico_malloc/CMakeLists.txt
@@ -10,6 +10,7 @@ if (NOT TARGET pico_malloc)
 
     pico_wrap_function(pico_malloc malloc)
     pico_wrap_function(pico_malloc calloc)
+    pico_wrap_function(pico_malloc realloc)
     pico_wrap_function(pico_malloc free)
 
     target_link_libraries(pico_malloc INTERFACE pico_sync)
diff --git a/src/rp2_common/pico_malloc/pico_malloc.c b/src/rp2_common/pico_malloc/pico_malloc.c
index 4928a8e9a..a05398663 100644
--- a/src/rp2_common/pico_malloc/pico_malloc.c
+++ b/src/rp2_common/pico_malloc/pico_malloc.c
@@ -16,6 +16,7 @@ auto_init_mutex(malloc_mutex);
 
 extern void *__real_malloc(size_t size);
 extern void *__real_calloc(size_t count, size_t size);
+extern void *__real_realloc(void *mem, size_t size);
 extern void __real_free(void *mem);
 
 extern char __StackLimit; /* Set by linker.  */
@@ -62,6 +63,23 @@ void *__wrap_calloc(size_t count, size_t size) {
     return rc;
 }
 
+void *__wrap_realloc(void *mem, size_t size) {
+#if PICO_USE_MALLOC_MUTEX
+    mutex_enter_blocking(&malloc_mutex);
+#endif
+    void *rc = __real_realloc(mem, size);
+#if PICO_USE_MALLOC_MUTEX
+    mutex_exit(&malloc_mutex);
+#endif
+#if PICO_DEBUG_MALLOC
+    if (!rc || ((uint8_t *)rc) + size > (uint8_t*)PICO_DEBUG_MALLOC_LOW_WATER) {
+        printf("realloc %p %d->%p\n", mem, (uint) size, rc);
+    }
+#endif
+    check_alloc(rc, size);
+    return rc;
+}
+
 void __wrap_free(void *mem) {
 #if PICO_USE_MALLOC_MUTEX
     mutex_enter_blocking(&malloc_mutex);

From 7daa20ce4c53cf7a6799563edafed5ad1b495f17 Mon Sep 17 00:00:00 2001
From: arturo182 <github@solder.party>
Date: Fri, 17 Jun 2022 19:58:13 +0200
Subject: [PATCH 18/51] Add board definition for the RP2040 Stamp Round Carrier
 (#837)

---
 .../solderparty_rp2040_stamp_round_carrier.h  | 79 +++++++++++++++++++
 1 file changed, 79 insertions(+)
 create mode 100644 src/boards/include/boards/solderparty_rp2040_stamp_round_carrier.h

diff --git a/src/boards/include/boards/solderparty_rp2040_stamp_round_carrier.h b/src/boards/include/boards/solderparty_rp2040_stamp_round_carrier.h
new file mode 100644
index 000000000..bb9d3351c
--- /dev/null
+++ b/src/boards/include/boards/solderparty_rp2040_stamp_round_carrier.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+//
+//------------------------------------------------------------------------------------------
+// Board definition for the Solder Party RP2040 Stamp Round Carrier
+//
+// This header may be included by other board headers as "boards/solderparty_rp2040_stamp_round_carrier.h"
+
+#ifndef _BOARDS_SOLDERPARTY_RP2040_STAMP_ROUND_CARRIER_H
+#define _BOARDS_SOLDERPARTY_RP2040_STAMP_ROUND_CARRIER_H
+
+// For board detection
+#define SOLDERPARTY_RP2040_STAMP_ROUND_CARRIER
+
+// --- User LED ---
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN   25
+#endif
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 16
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 17
+#endif
+
+// --- Neopixel Ring ---
+#ifndef PICO_DEFAULT_WS2812_PIN
+#define PICO_DEFAULT_WS2812_PIN 24
+#endif
+
+// --- On-Stamp Neopixel ---
+#ifndef SOLDERPARTY_RP2040_STAMP_WS2812_PIN
+#define SOLDERPARTY_RP2040_STAMP_WS2812_PIN 21
+#endif
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C       0
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN   0
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN   1
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 1
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 10
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 11
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 8
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 9
+#endif
+
+#include "solderparty_rp2040_stamp.h"
+
+#endif

From 0bdd463898bf435ede1770bcd0c4ba024a04441e Mon Sep 17 00:00:00 2001
From: Datanoise <de.retrospektive@gmail.com>
Date: Sat, 18 Jun 2022 01:03:46 +0200
Subject: [PATCH 19/51] Add DatanoiseTV DSP Board. (#866)

---
 .../include/boards/datanoisetv_rp2040_dsp.h   | 60 +++++++++++++++++++
 1 file changed, 60 insertions(+)
 create mode 100644 src/boards/include/boards/datanoisetv_rp2040_dsp.h

diff --git a/src/boards/include/boards/datanoisetv_rp2040_dsp.h b/src/boards/include/boards/datanoisetv_rp2040_dsp.h
new file mode 100644
index 000000000..49a357bc6
--- /dev/null
+++ b/src/boards/include/boards/datanoisetv_rp2040_dsp.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+//
+//------------------------------------------------------------------------------------------
+// Board definition for the DatanoiseTV RP2040 DSP Board
+//
+// This header may be included by other board headers as "boards/datanoisetv_rp2040_dsp.h"
+
+#ifndef _BOARDS_DATANOISETV_RP2040_DSP_H
+#define _BOARDS_DATANOISETV_RP2040_DSP_H
+
+// For board detection
+#define DATANOISETV_RP2040_DSP
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C       0
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN   24 
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN   25
+#endif
+
+// -- FLASH --
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
+#endif
+
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+
+// --- I2S ---
+#ifndef PICO_AUDIO_I2S_DATA_PIN
+#define PICO_AUDIO_I2S_DATA_PIN 16
+#endif
+#ifndef PICO_AUDIO_I2S_CLOCK_PIN_BASE
+#define PICO_AUDIO_I2S_CLOCK_PIN_BASE 17
+#endif
+
+#include "boards/pico.h"
+
+#endif

From 7858601a58fed753c5aaa5ff6828cc0492821bef Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Mon, 20 Jun 2022 09:51:51 -0500
Subject: [PATCH 20/51] stdio_usb improvements (#871)

Use shared IRQ if available to avoid 1ms timer. Allow use of stdio_usb with user's tinyusb setup if it has CDC
---
 .../hardware_irq/include/hardware/irq.h       |  8 +++
 src/rp2_common/hardware_irq/irq.c             | 11 ++++
 .../pico_stdio_usb/include/tusb_config.h      |  3 +
 .../pico_stdio_usb/reset_interface.c          |  3 +
 src/rp2_common/pico_stdio_usb/stdio_usb.c     | 57 +++++++++++++++----
 5 files changed, 72 insertions(+), 10 deletions(-)

diff --git a/src/rp2_common/hardware_irq/include/hardware/irq.h b/src/rp2_common/hardware_irq/include/hardware/irq.h
index 4f834661b..66679feb0 100644
--- a/src/rp2_common/hardware_irq/include/hardware/irq.h
+++ b/src/rp2_common/hardware_irq/include/hardware/irq.h
@@ -252,6 +252,14 @@ void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_prior
  */
 void irq_remove_handler(uint num, irq_handler_t handler);
 
+/*! \brief Determine if the current handler for the given number is shared
+ *  \ingroup hardware_irq
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \param return true if the specified IRQ has a shared handler
+ */
+bool irq_has_shared_handler(uint num);
+
 /*! \brief Get the current IRQ handler for the specified IRQ from the currently installed hardware vector table (VTOR)
  * of the execution core
  *  \ingroup hardware_irq
diff --git a/src/rp2_common/hardware_irq/irq.c b/src/rp2_common/hardware_irq/irq.c
index 170fcf1ce..251cdf7b7 100644
--- a/src/rp2_common/hardware_irq/irq.c
+++ b/src/rp2_common/hardware_irq/irq.c
@@ -95,10 +95,21 @@ static int8_t irq_hander_chain_free_slot_head;
 static inline bool is_shared_irq_raw_handler(irq_handler_t raw_handler) {
     return (uintptr_t)raw_handler - (uintptr_t)irq_handler_chain_slots < sizeof(irq_handler_chain_slots);
 }
+
+bool irq_has_shared_handler(uint irq_num) {
+    check_irq_param(irq_num);
+    irq_handler_t handler = irq_get_vtable_handler(irq_num);
+    return handler && is_shared_irq_raw_handler(handler);
+}
+
 #else
 #define is_shared_irq_raw_handler(h) false
+bool irq_has_shared_handler(uint irq_num) {
+    return false;
+}
 #endif
 
+
 irq_handler_t irq_get_vtable_handler(uint num) {
     check_irq_param(num);
     return get_vtable()[16 + num];
diff --git a/src/rp2_common/pico_stdio_usb/include/tusb_config.h b/src/rp2_common/pico_stdio_usb/include/tusb_config.h
index c0a28435c..c0d2ed3e3 100644
--- a/src/rp2_common/pico_stdio_usb/include/tusb_config.h
+++ b/src/rp2_common/pico_stdio_usb/include/tusb_config.h
@@ -29,6 +29,7 @@
 
 #include "pico/stdio_usb.h"
 
+#if !defined(LIB_TINYUSB_HOST) && !defined(LIB_TINYUSB_DEVICE)
 #define CFG_TUSB_RHPORT0_MODE   (OPT_MODE_DEVICE)
 
 #define CFG_TUD_CDC             (1)
@@ -38,3 +39,5 @@
 // We use a vendor specific interface but with our own driver
 #define CFG_TUD_VENDOR            (0)
 #endif
+
+#endif
diff --git a/src/rp2_common/pico_stdio_usb/reset_interface.c b/src/rp2_common/pico_stdio_usb/reset_interface.c
index 06dce86a9..cc2517799 100644
--- a/src/rp2_common/pico_stdio_usb/reset_interface.c
+++ b/src/rp2_common/pico_stdio_usb/reset_interface.c
@@ -7,6 +7,8 @@
 
 #include "pico/bootrom.h"
 
+#if !defined(LIB_TINYUSB_HOST) && !defined(LIB_TINYUSB_DEVICE)
+
 #if PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE && !(PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_BOOTSEL || PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_FLASH_BOOT)
 #warning PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE has been selected but neither PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_BOOTSEL nor PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_FLASH_BOOT have been selected.
 #endif
@@ -110,3 +112,4 @@ void tud_cdc_line_coding_cb(__unused uint8_t itf, cdc_line_coding_t const* p_lin
 }
 #endif
 
+#endif
\ No newline at end of file
diff --git a/src/rp2_common/pico_stdio_usb/stdio_usb.c b/src/rp2_common/pico_stdio_usb/stdio_usb.c
index df3920fc8..cd2e2c93f 100644
--- a/src/rp2_common/pico_stdio_usb/stdio_usb.c
+++ b/src/rp2_common/pico_stdio_usb/stdio_usb.c
@@ -4,15 +4,27 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#if !defined(LIB_TINYUSB_HOST) && !defined(LIB_TINYUSB_DEVICE)
+#ifndef LIB_TINYUSB_HOST
 #include "tusb.h"
+#include "pico/stdio_usb.h"
+
+// these may not be set if the user is providing tud support (i.e. LIB_TINYUSB_DEVICE is 1 because
+// the user linked in tinyusb_device) but they haven't selected CDC
+#if (CFG_TUD_ENABLED | TUSB_OPT_DEVICE_ENABLED) && CFG_TUD_CDC
 
+#include "pico/binary_info.h"
 #include "pico/time.h"
 #include "pico/stdio/driver.h"
-#include "pico/binary_info.h"
 #include "pico/mutex.h"
 #include "hardware/irq.h"
 
+static mutex_t stdio_usb_mutex;
+#ifndef NDEBUG
+static uint8_t stdio_usb_core_num;
+#endif
+
+// when tinyusb_device is explicitly linked we do no background tud processing
+#if !LIB_TINYUSB_DEVICE
 #ifdef PICO_STDIO_USB_LOW_PRIORITY_IRQ
 static_assert(PICO_STDIO_USB_LOW_PRIORITY_IRQ >= NUM_IRQS - NUM_USER_IRQS, "");
 #define low_priority_irq_num PICO_STDIO_USB_LOW_PRIORITY_IRQ
@@ -20,8 +32,6 @@ static_assert(PICO_STDIO_USB_LOW_PRIORITY_IRQ >= NUM_IRQS - NUM_USER_IRQS, "");
 static uint8_t low_priority_irq_num;
 #endif
 
-static mutex_t stdio_usb_mutex;
-
 static void low_priority_worker_irq(void) {
     // if the mutex is already owned, then we are in user code
     // in this file which will do a tud_task itself, so we'll just do nothing
@@ -32,10 +42,16 @@ static void low_priority_worker_irq(void) {
     }
 }
 
+static void usb_irq(void) {
+    irq_set_pending(low_priority_irq_num);
+}
+
 static int64_t timer_task(__unused alarm_id_t id, __unused void *user_data) {
+    assert(stdio_usb_core_num == get_core_num()); // if this fails, you have initialized stdio_usb on the wrong core
     irq_set_pending(low_priority_irq_num);
     return PICO_STDIO_USB_TASK_INTERVAL_US;
 }
+#endif
 
 static void stdio_usb_out_chars(const char *buf, int length) {
     static uint64_t last_avail_time;
@@ -95,13 +111,23 @@ stdio_driver_t stdio_usb = {
 };
 
 bool stdio_usb_init(void) {
+#ifndef NDEBUG
+    stdio_usb_core_num = (uint8_t)get_core_num();
+#endif
 #if !PICO_NO_BI_STDIO_USB
     bi_decl_if_func_used(bi_program_feature("USB stdin / stdout"));
 #endif
 
-    // initialize TinyUSB
+#if !defined(LIB_TINYUSB_DEVICE)
+    // initialize TinyUSB, as user hasn't explicitly linked it
     tusb_init();
+#else
+    assert(tud_inited()); // we expect the caller to have initialized if they are using TinyUSB
+#endif
 
+    mutex_init(&stdio_usb_mutex);
+    bool rc = true;
+#if !LIB_TINYUSB_DEVICE
 #ifdef PICO_STDIO_USB_LOW_PRIORITY_IRQ
     user_irq_claim(PICO_STDIO_USB_LOW_PRIORITY_IRQ);
 #else
@@ -110,8 +136,13 @@ bool stdio_usb_init(void) {
     irq_set_exclusive_handler(low_priority_irq_num, low_priority_worker_irq);
     irq_set_enabled(low_priority_irq_num, true);
 
-    mutex_init(&stdio_usb_mutex);
-    bool rc = add_alarm_in_us(PICO_STDIO_USB_TASK_INTERVAL_US, timer_task, NULL, true);
+    if (irq_has_shared_handler(USBCTRL_IRQ)) {
+        // we can use a shared handler to notice when there may be work to do
+        irq_add_shared_handler(USBCTRL_IRQ, usb_irq, PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY);
+    } else {
+        rc = add_alarm_in_us(PICO_STDIO_USB_TASK_INTERVAL_US, timer_task, NULL, true);
+    }
+#endif
     if (rc) {
         stdio_set_driver_enabled(&stdio_usb, true);
 #if PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS
@@ -138,9 +169,15 @@ bool stdio_usb_connected(void) {
     return tud_cdc_connected();
 }
 #else
-#include "pico/stdio_usb.h"
-#warning stdio USB was configured, but is being disabled as TinyUSB is explicitly linked
+#warning stdio USB was configured along with user use of TinyUSB device mode, but CDC is not enabled
 bool stdio_usb_init(void) {
     return false;
 }
-#endif
+#endif // CFG_TUD_ENABLED && CFG_TUD_CDC
+#else
+#warning stdio USB was configured, but is being disabled as TinyUSB host is explicitly linked
+bool stdio_usb_init(void) {
+    return false;
+}
+#endif // !LIB_TINYUSB_HOST
+

From b3c56e716909f650d571cbb83ae78bc2e430fbf8 Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Mon, 20 Jun 2022 09:52:06 -0500
Subject: [PATCH 21/51] Add stderr support and remove 1us timeout for timeouts
 of 0us (#858)

---
 src/rp2_common/pico_stdio/stdio.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/src/rp2_common/pico_stdio/stdio.c b/src/rp2_common/pico_stdio/stdio.c
index e2eb5ffb9..52a1c0cc0 100644
--- a/src/rp2_common/pico_stdio/stdio.c
+++ b/src/rp2_common/pico_stdio/stdio.c
@@ -29,6 +29,10 @@
 #include "pico/stdio_semihosting.h"
 #endif
 
+#define STDIO_HANDLE_STDIN  0
+#define STDIO_HANDLE_STDOUT 1
+#define STDIO_HANDLE_STDERR 2
+
 static stdio_driver_t *drivers;
 static stdio_driver_t *filter;
 
@@ -131,11 +135,13 @@ static int stdio_get_until(char *buf, int len, absolute_time_t until) {
                 }
             }
         }
+        if (time_reached(until)) {
+            return PICO_ERROR_TIMEOUT;
+        }
         // we sleep here in case the in_chars methods acquire mutexes or disable IRQs and
         // potentially starve out what they are waiting on (have seen this with USB)
         busy_wait_us(1);
-    } while (!time_reached(until));
-    return PICO_ERROR_TIMEOUT;
+    } while (true);
 }
 
 int WRAPPER_FUNC(putchar)(int c) {
@@ -165,14 +171,14 @@ int puts_raw(const char *s) {
 }
 
 int _read(int handle, char *buffer, int length) {
-    if (handle == 0) {
+    if (handle == STDIO_HANDLE_STDIN) {
         return stdio_get_until(buffer, length, at_the_end_of_time);
     }
     return -1;
 }
 
 int _write(int handle, char *buffer, int length) {
-    if (handle == 1) {
+    if (handle == STDIO_HANDLE_STDOUT || handle == STDIO_HANDLE_STDERR) {
         stdio_put_string(buffer, length, false, false);
         return length;
     }

From 96443999935a269efce0fe3ac77bea362dcbee96 Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Mon, 20 Jun 2022 09:52:25 -0500
Subject: [PATCH 22/51] Suppress new GCC 12 warning (#842)

---
 src/rp2_common/hardware_rtc/rtc.c             | 42 +++++++++----------
 src/rp2_common/pico_bootrom/bootrom.c         |  3 --
 .../pico_bootrom/include/pico/bootrom.h       | 12 +++++-
 .../pico_platform/include/pico/platform.h     |  3 ++
 4 files changed, 35 insertions(+), 25 deletions(-)

diff --git a/src/rp2_common/hardware_rtc/rtc.c b/src/rp2_common/hardware_rtc/rtc.c
index 5429acd4b..be9250f6e 100644
--- a/src/rp2_common/hardware_rtc/rtc.c
+++ b/src/rp2_common/hardware_rtc/rtc.c
@@ -65,13 +65,13 @@ bool rtc_set_datetime(datetime_t *t) {
     }
 
     // Write to setup registers
-    rtc_hw->setup_0 = (((uint)t->year)  << RTC_SETUP_0_YEAR_LSB ) |
-                      (((uint)t->month) << RTC_SETUP_0_MONTH_LSB) |
-                      (((uint)t->day)   << RTC_SETUP_0_DAY_LSB);
-    rtc_hw->setup_1 = (((uint)t->dotw)  << RTC_SETUP_1_DOTW_LSB) |
-                      (((uint)t->hour)  << RTC_SETUP_1_HOUR_LSB) |
-                      (((uint)t->min)   << RTC_SETUP_1_MIN_LSB)  |
-                      (((uint)t->sec)   << RTC_SETUP_1_SEC_LSB);
+    rtc_hw->setup_0 = (((uint32_t)t->year)  << RTC_SETUP_0_YEAR_LSB ) |
+                      (((uint32_t)t->month) << RTC_SETUP_0_MONTH_LSB) |
+                      (((uint32_t)t->day)   << RTC_SETUP_0_DAY_LSB);
+    rtc_hw->setup_1 = (((uint32_t)t->dotw)  << RTC_SETUP_1_DOTW_LSB) |
+                      (((uint32_t)t->hour)  << RTC_SETUP_1_HOUR_LSB) |
+                      (((uint32_t)t->min)   << RTC_SETUP_1_MIN_LSB)  |
+                      (((uint32_t)t->sec)   << RTC_SETUP_1_SEC_LSB);
 
     // Load setup values into rtc clock domain
     rtc_hw->ctrl = RTC_CTRL_LOAD_BITS;
@@ -95,13 +95,13 @@ bool rtc_get_datetime(datetime_t *t) {
     uint32_t rtc_0 = rtc_hw->rtc_0;
     uint32_t rtc_1 = rtc_hw->rtc_1;
 
-    t->dotw  = (rtc_0 & RTC_RTC_0_DOTW_BITS ) >> RTC_RTC_0_DOTW_LSB;
-    t->hour  = (rtc_0 & RTC_RTC_0_HOUR_BITS ) >> RTC_RTC_0_HOUR_LSB;
-    t->min   = (rtc_0 & RTC_RTC_0_MIN_BITS  ) >> RTC_RTC_0_MIN_LSB;
-    t->sec   = (rtc_0 & RTC_RTC_0_SEC_BITS  ) >> RTC_RTC_0_SEC_LSB;
-    t->year  = (rtc_1 & RTC_RTC_1_YEAR_BITS ) >> RTC_RTC_1_YEAR_LSB;
-    t->month = (rtc_1 & RTC_RTC_1_MONTH_BITS) >> RTC_RTC_1_MONTH_LSB;
-    t->day   = (rtc_1 & RTC_RTC_1_DAY_BITS  ) >> RTC_RTC_1_DAY_LSB;
+    t->dotw  = (int8_t) ((rtc_0 & RTC_RTC_0_DOTW_BITS ) >> RTC_RTC_0_DOTW_LSB);
+    t->hour  = (int8_t) ((rtc_0 & RTC_RTC_0_HOUR_BITS ) >> RTC_RTC_0_HOUR_LSB);
+    t->min   = (int8_t) ((rtc_0 & RTC_RTC_0_MIN_BITS  ) >> RTC_RTC_0_MIN_LSB);
+    t->sec   = (int8_t) ((rtc_0 & RTC_RTC_0_SEC_BITS  ) >> RTC_RTC_0_SEC_LSB);
+    t->year  = (int16_t) ((rtc_1 & RTC_RTC_1_YEAR_BITS ) >> RTC_RTC_1_YEAR_LSB);
+    t->month = (int8_t) ((rtc_1 & RTC_RTC_1_MONTH_BITS) >> RTC_RTC_1_MONTH_LSB);
+    t->day   = (int8_t) ((rtc_1 & RTC_RTC_1_DAY_BITS  ) >> RTC_RTC_1_DAY_LSB);
 
     return true;
 }
@@ -148,13 +148,13 @@ void rtc_set_alarm(datetime_t *t, rtc_callback_t user_callback) {
     rtc_disable_alarm();
 
     // Only add to setup if it isn't -1
-    rtc_hw->irq_setup_0 = ((t->year  < 0) ? 0 : (((uint)t->year)  << RTC_IRQ_SETUP_0_YEAR_LSB )) |
-                          ((t->month < 0) ? 0 : (((uint)t->month) << RTC_IRQ_SETUP_0_MONTH_LSB)) |
-                          ((t->day   < 0) ? 0 : (((uint)t->day)   << RTC_IRQ_SETUP_0_DAY_LSB  ));
-    rtc_hw->irq_setup_1 = ((t->dotw  < 0) ? 0 : (((uint)t->dotw)  << RTC_IRQ_SETUP_1_DOTW_LSB)) |
-                          ((t->hour  < 0) ? 0 : (((uint)t->hour)  << RTC_IRQ_SETUP_1_HOUR_LSB)) |
-                          ((t->min   < 0) ? 0 : (((uint)t->min)   << RTC_IRQ_SETUP_1_MIN_LSB )) |
-                          ((t->sec   < 0) ? 0 : (((uint)t->sec)   << RTC_IRQ_SETUP_1_SEC_LSB ));
+    rtc_hw->irq_setup_0 = ((t->year  < 0) ? 0 : (((uint32_t)t->year)  << RTC_IRQ_SETUP_0_YEAR_LSB )) |
+                          ((t->month < 0) ? 0 : (((uint32_t)t->month) << RTC_IRQ_SETUP_0_MONTH_LSB)) |
+                          ((t->day   < 0) ? 0 : (((uint32_t)t->day)   << RTC_IRQ_SETUP_0_DAY_LSB  ));
+    rtc_hw->irq_setup_1 = ((t->dotw  < 0) ? 0 : (((uint32_t)t->dotw)  << RTC_IRQ_SETUP_1_DOTW_LSB)) |
+                          ((t->hour  < 0) ? 0 : (((uint32_t)t->hour)  << RTC_IRQ_SETUP_1_HOUR_LSB)) |
+                          ((t->min   < 0) ? 0 : (((uint32_t)t->min)   << RTC_IRQ_SETUP_1_MIN_LSB )) |
+                          ((t->sec   < 0) ? 0 : (((uint32_t)t->sec)   << RTC_IRQ_SETUP_1_SEC_LSB ));
 
     // Set the match enable bits for things we care about
     if (t->year  >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_YEAR_ENA_BITS);
diff --git a/src/rp2_common/pico_bootrom/bootrom.c b/src/rp2_common/pico_bootrom/bootrom.c
index af7d09148..5def61a09 100644
--- a/src/rp2_common/pico_bootrom/bootrom.c
+++ b/src/rp2_common/pico_bootrom/bootrom.c
@@ -12,9 +12,6 @@
 // Returns the 32 bit pointer into the ROM if found or NULL otherwise.
 typedef void *(*rom_table_lookup_fn)(uint16_t *table, uint32_t code);
 
-// Convert a 16 bit pointer stored at the given rom address into a 32 bit pointer
-#define rom_hword_as_ptr(rom_address) (void *)(uintptr_t)(*(uint16_t *)rom_address)
-
 void *rom_func_lookup(uint32_t code) {
     return rom_func_lookup_inline(code);
 }
diff --git a/src/rp2_common/pico_bootrom/include/pico/bootrom.h b/src/rp2_common/pico_bootrom/include/pico/bootrom.h
index e55789315..448456860 100644
--- a/src/rp2_common/pico_bootrom/include/pico/bootrom.h
+++ b/src/rp2_common/pico_bootrom/include/pico/bootrom.h
@@ -116,8 +116,18 @@ bool rom_funcs_lookup(uint32_t *table, unsigned int count);
 // Returns the 32 bit pointer into the ROM if found or NULL otherwise.
 typedef void *(*rom_table_lookup_fn)(uint16_t *table, uint32_t code);
 
+#if defined(__GNUC__) && (__GNUC__ >= 12)
 // Convert a 16 bit pointer stored at the given rom address into a 32 bit pointer
-#define rom_hword_as_ptr(rom_address) (void *)(uintptr_t)(*(uint16_t *)rom_address)
+static inline void *rom_hword_as_ptr(uint16_t rom_address) {
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Warray-bounds"
+    return (void *)(uintptr_t)*(uint16_t *)(uintptr_t)rom_address;
+#pragma GCC diagnostic pop
+}
+#else
+// Convert a 16 bit pointer stored at the given rom address into a 32 bit pointer
+#define rom_hword_as_ptr(rom_address) (void *)(uintptr_t)(*(uint16_t *)(uintptr_t)(rom_address))
+#endif
 
 /*!
  * \brief Lookup a bootrom function by code. This method is forceably inlined into the caller for FLASH/RAM sensitive code usage
diff --git a/src/rp2_common/pico_platform/include/pico/platform.h b/src/rp2_common/pico_platform/include/pico/platform.h
index 1236fcd55..1d9e1bc7d 100644
--- a/src/rp2_common/pico_platform/include/pico/platform.h
+++ b/src/rp2_common/pico_platform/include/pico/platform.h
@@ -336,7 +336,10 @@ uint8_t rp2040_chip_version(void);
  * @return the RP2040 rom version number (1 for RP2040-B0, 2 for RP2040-B1, 3 for RP2040-B2)
  */
 static inline uint8_t rp2040_rom_version(void) {
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Warray-bounds"
     return *(uint8_t*)0x13;
+#pragma GCC diagnostic pop
 }
 
 /*! \brief No-op function for the body of tight loops

From 8f09099757467457f95c118c1de14ca70c7feab0 Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Mon, 20 Jun 2022 09:52:43 -0500
Subject: [PATCH 23/51] sem_acquire has no reason to do a notify! (#857)

---
 src/common/pico_sync/sem.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/common/pico_sync/sem.c b/src/common/pico_sync/sem.c
index 5578a49b1..ec49fdba5 100644
--- a/src/common/pico_sync/sem.c
+++ b/src/common/pico_sync/sem.c
@@ -23,7 +23,7 @@ void __time_critical_func(sem_acquire_blocking)(semaphore_t *sem) {
         uint32_t save = spin_lock_blocking(sem->core.spin_lock);
         if (sem->permits > 0) {
             sem->permits--;
-            lock_internal_spin_unlock_with_notify(&sem->core, save);
+            spin_unlock(sem->core.spin_lock, save);
             break;
         }
         lock_internal_spin_unlock_with_wait(&sem->core, save);
@@ -43,7 +43,7 @@ bool __time_critical_func(sem_acquire_block_until)(semaphore_t *sem, absolute_ti
         uint32_t save = spin_lock_blocking(sem->core.spin_lock);
         if (sem->permits > 0) {
             sem->permits--;
-            lock_internal_spin_unlock_with_notify(&sem->core, save);
+            spin_unlock(sem->core.spin_lock, save);
             return true;
         }
         if (lock_internal_spin_unlock_with_best_effort_wait_or_timeout(&sem->core, save, until)) {
@@ -56,7 +56,7 @@ bool __time_critical_func(sem_try_acquire)(semaphore_t *sem) {
     uint32_t save = spin_lock_blocking(sem->core.spin_lock);
     if (sem->permits > 0) {
         sem->permits--;
-        lock_internal_spin_unlock_with_notify(&sem->core, save);
+        spin_unlock(sem->core.spin_lock, save);
         return true;
     }
     spin_unlock(sem->core.spin_lock, save);

From 33818dd0bd1748bad28afb2a3f85667673187cc6 Mon Sep 17 00:00:00 2001
From: Liam Fraser <liam@raspberrypi.com>
Date: Mon, 20 Jun 2022 16:28:03 +0100
Subject: [PATCH 24/51] Increase PLL min VCO from 400MHz to 750MHz for improved
 stability across operating conditions (#869)

Co-authored-by: graham sanderson <graham.sanderson@raspberrypi.com>
---
 src/rp2040/hardware_regs/include/hardware/regs/pll.h | 4 ++--
 src/rp2040/hardware_regs/rp2040.svd                  | 2 +-
 src/rp2_common/hardware_clocks/clocks.c              | 6 +++---
 src/rp2_common/hardware_clocks/scripts/vcocalc.py    | 2 +-
 src/rp2_common/hardware_pll/include/hardware/pll.h   | 8 ++++++++
 src/rp2_common/hardware_pll/pll.c                    | 3 +++
 src/rp2_common/pico_stdlib/stdlib.c                  | 2 +-
 7 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/src/rp2040/hardware_regs/include/hardware/regs/pll.h b/src/rp2040/hardware_regs/include/hardware/regs/pll.h
index a0f5ad0ef..9dba689ab 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/pll.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/pll.h
@@ -1,5 +1,5 @@
 /**
- * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -17,7 +17,7 @@
 //               GENERAL CONSTRAINTS:
 //               Reference clock frequency min=5MHz, max=800MHz
 //               Feedback divider min=16, max=320
-//               VCO frequency min=400MHz, max=1600MHz
+//               VCO frequency min=750MHz, max=1600MHz
 #define PLL_CS_OFFSET _u(0x00000000)
 #define PLL_CS_BITS   _u(0x8000013f)
 #define PLL_CS_RESET  _u(0x00000001)
diff --git a/src/rp2040/hardware_regs/rp2040.svd b/src/rp2040/hardware_regs/rp2040.svd
index 95e199027..3849776d7 100644
--- a/src/rp2040/hardware_regs/rp2040.svd
+++ b/src/rp2040/hardware_regs/rp2040.svd
@@ -22367,7 +22367,7 @@
             GENERAL CONSTRAINTS:\n
             Reference clock frequency min=5MHz, max=800MHz\n
             Feedback divider min=16, max=320\n
-            VCO frequency min=400MHz, max=1600MHz</description>
+            VCO frequency min=750MHz, max=1600MHz</description>
           <fields>
             <field>
               <access>read-only</access>
diff --git a/src/rp2_common/hardware_clocks/clocks.c b/src/rp2_common/hardware_clocks/clocks.c
index f51331aac..9ba51f03d 100644
--- a/src/rp2_common/hardware_clocks/clocks.c
+++ b/src/rp2_common/hardware_clocks/clocks.c
@@ -148,13 +148,13 @@ void clocks_init(void) {
     /// \tag::pll_settings[]
     // Configure PLLs
     //                   REF     FBDIV VCO            POSTDIV
-    // PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHZ / 6 / 2 = 125MHz
-    // PLL USB: 12 / 1 = 12MHz * 40  = 480 MHz / 5 / 2 =  48MHz
+    // PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHz / 6 / 2 = 125MHz
+    // PLL USB: 12 / 1 = 12MHz * 100 = 1200MHz / 5 / 5 =  48MHz
     /// \end::pll_settings[]
 
     /// \tag::pll_init[]
     pll_init(pll_sys, 1, 1500 * MHZ, 6, 2);
-    pll_init(pll_usb, 1, 480 * MHZ, 5, 2);
+    pll_init(pll_usb, 1, 1200 * MHZ, 5, 5);
     /// \end::pll_init[]
 
     // Configure clocks
diff --git a/src/rp2_common/hardware_clocks/scripts/vcocalc.py b/src/rp2_common/hardware_clocks/scripts/vcocalc.py
index 4d901465d..5d143b384 100755
--- a/src/rp2_common/hardware_clocks/scripts/vcocalc.py
+++ b/src/rp2_common/hardware_clocks/scripts/vcocalc.py
@@ -5,7 +5,7 @@
 parser = argparse.ArgumentParser(description="PLL parameter calculator")
 parser.add_argument("--input", "-i", default=12, help="Input (reference) frequency. Default 12 MHz", type=float)
 parser.add_argument("--vco-max", default=1600, help="Override maximum VCO frequency. Default 1600 MHz", type=float)
-parser.add_argument("--vco-min", default=400, help="Override minimum VCO frequency. Default 400 MHz", type=float)
+parser.add_argument("--vco-min", default=750, help="Override minimum VCO frequency. Default 750 MHz", type=float)
 parser.add_argument("--low-vco", "-l", action="store_true", help="Use a lower VCO frequency when possible. This reduces power consumption, at the cost of increased jitter")
 parser.add_argument("output", help="Output frequency in MHz.", type=float)
 args = parser.parse_args()
diff --git a/src/rp2_common/hardware_pll/include/hardware/pll.h b/src/rp2_common/hardware_pll/include/hardware/pll.h
index ee0c3aef0..0466504d5 100644
--- a/src/rp2_common/hardware_pll/include/hardware/pll.h
+++ b/src/rp2_common/hardware_pll/include/hardware/pll.h
@@ -31,6 +31,14 @@ typedef pll_hw_t *PLL;
 #define pll_sys pll_sys_hw
 #define pll_usb pll_usb_hw
 
+#ifndef PICO_PLL_VCO_MIN_FREQ_MHZ
+#define PICO_PLL_VCO_MIN_FREQ_MHZ 750
+#endif
+
+#ifndef PICO_PLL_VCO_MAX_FREQ_MHZ
+#define PICO_PLL_VCO_MAX_FREQ_MHZ 1600
+#endif
+
 /*! \brief Initialise specified PLL.
  *  \ingroup hardware_pll
  * \param pll pll_sys or pll_usb
diff --git a/src/rp2_common/hardware_pll/pll.c b/src/rp2_common/hardware_pll/pll.c
index f1a09d536..e152b844d 100644
--- a/src/rp2_common/hardware_pll/pll.c
+++ b/src/rp2_common/hardware_pll/pll.c
@@ -13,6 +13,9 @@
 void pll_init(PLL pll, uint refdiv, uint vco_freq, uint post_div1, uint post_div2) {
     uint32_t ref_mhz = XOSC_MHZ / refdiv;
 
+    // Check vco freq is in an acceptable range
+    assert(vco_freq >= (PICO_PLL_VCO_MIN_FREQ_MHZ * MHZ) && vco_freq <= (PICO_PLL_VCO_MAX_FREQ_MHZ * MHZ));
+
     // What are we multiplying the reference clock by to get the vco freq
     // (The regs are called div, because you divide the vco output and compare it to the refclk)
     uint32_t fbdiv = vco_freq / (ref_mhz * MHZ);
diff --git a/src/rp2_common/pico_stdlib/stdlib.c b/src/rp2_common/pico_stdlib/stdlib.c
index 7c9854e7a..159095ce4 100644
--- a/src/rp2_common/pico_stdlib/stdlib.c
+++ b/src/rp2_common/pico_stdlib/stdlib.c
@@ -73,7 +73,7 @@ bool check_sys_clock_khz(uint32_t freq_khz, uint *vco_out, uint *postdiv1_out, u
     uint crystal_freq_khz = clock_get_hz(clk_ref) / 1000;
     for (uint fbdiv = 320; fbdiv >= 16; fbdiv--) {
         uint vco = fbdiv * crystal_freq_khz;
-        if (vco < 400000 || vco > 1600000) continue;
+        if (vco < PICO_PLL_VCO_MIN_FREQ_MHZ * 1000  || vco > PICO_PLL_VCO_MAX_FREQ_MHZ * 1000) continue;
         for (uint postdiv1 = 7; postdiv1 >= 1; postdiv1--) {
             for (uint postdiv2 = postdiv1; postdiv2 >= 1; postdiv2--) {
                 uint out = vco / (postdiv1 * postdiv2);

From 4c49427bf3048a12569f9890188c4be33e082838 Mon Sep 17 00:00:00 2001
From: "Earle F. Philhower, III" <earlephilhower@yahoo.com>
Date: Mon, 20 Jun 2022 10:47:46 -0700
Subject: [PATCH 25/51] Fix auto_init_recursive_mutex definition for C++ (#875)

Co-authored-by: Graham Sanderson <graham.sanderson@gmail.com>
---
 src/common/pico_sync/include/pico/mutex.h | 2 +-
 test/kitchen_sink/kitchen_sink.c          | 9 +++++++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/common/pico_sync/include/pico/mutex.h b/src/common/pico_sync/include/pico/mutex.h
index e834dc513..ca9376020 100644
--- a/src/common/pico_sync/include/pico/mutex.h
+++ b/src/common/pico_sync/include/pico/mutex.h
@@ -289,7 +289,7 @@ static inline bool recursive_mutex_is_initialized(recursive_mutex_t *mtx) {
  *
  * But the initialization of the mutex is performed automatically during runtime initialization
  */
-#define auto_init_recursive_mutex(name) static __attribute__((section(".mutex_array"))) recursive_mutex_t name = { .core.spin_lock = (spin_lock_t *)1 /* marker for runtime_init */ }
+#define auto_init_recursive_mutex(name) static __attribute__((section(".mutex_array"))) recursive_mutex_t name = { .core = { .spin_lock = (spin_lock_t *)1 /* marker for runtime_init */ }, .owner = 0, .enter_count = 0 }
 
 #ifdef __cplusplus
 }
diff --git a/test/kitchen_sink/kitchen_sink.c b/test/kitchen_sink/kitchen_sink.c
index f61ece363..62fe03a07 100644
--- a/test/kitchen_sink/kitchen_sink.c
+++ b/test/kitchen_sink/kitchen_sink.c
@@ -110,6 +110,9 @@ __force_inline int something_inlined(int x) {
     return x * 2;
 }
 
+auto_init_mutex(mutex);
+auto_init_recursive_mutex(recursive_mutex);
+
 int main(void) {
     spiggle();
 
@@ -118,6 +121,12 @@ int main(void) {
     printf("HI %d\n", something_inlined((int)time_us_32()));
     puts("Hello Everything!");
     puts("Hello Everything2!");
+
+    hard_assert(mutex_try_enter(&mutex, NULL));
+    hard_assert(!mutex_try_enter(&mutex, NULL));
+    hard_assert(recursive_mutex_try_enter(&recursive_mutex, NULL));
+    hard_assert(recursive_mutex_try_enter(&recursive_mutex, NULL));
     // this should compile as we are Cortex M0+
     __asm volatile("SVC #3");
+
 }

From e7267f99febc70486923e17a8210088af058c915 Mon Sep 17 00:00:00 2001
From: "Earle F. Philhower, III" <earlephilhower@yahoo.com>
Date: Fri, 24 Jun 2022 01:58:36 -0700
Subject: [PATCH 26/51] Fix GPIO # callback parameter (#880)

Fixes #879
---
 src/rp2_common/hardware_gpio/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/rp2_common/hardware_gpio/gpio.c b/src/rp2_common/hardware_gpio/gpio.c
index aa6e98c21..6e4261fcb 100644
--- a/src/rp2_common/hardware_gpio/gpio.c
+++ b/src/rp2_common/hardware_gpio/gpio.c
@@ -152,7 +152,7 @@ static void gpio_default_irq_handler(void) {
             if (events && !(raw_irq_mask[core] & (1u << i))) {
                 gpio_acknowledge_irq(i, events);
                 if (callback) {
-                    callback(gpio, events);
+                    callback(i, events);
                 }
             }
             events8 >>= 4;

From 85dbbfdf4dc21374d0497c327941c1eaaade2e1d Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Wed, 29 Jun 2022 17:09:33 +0100
Subject: [PATCH 27/51] Update TinyUSB to commit 39069cf4b to pick up recent
 RP2040 fixes (#886)

---
 lib/tinyusb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/tinyusb b/lib/tinyusb
index 4bfab30c0..39069cf4b 160000
--- a/lib/tinyusb
+++ b/lib/tinyusb
@@ -1 +1 @@
-Subproject commit 4bfab30c02279a0530e1a56f4a7c539f2d35a293
+Subproject commit 39069cf4be84a4cd1f1a4f3435ea69e606d2b064

From bc5d1b8485c09bc2c36a4d9ed9abba9b25786f3b Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Thu, 30 Jun 2022 02:56:45 +0100
Subject: [PATCH 28/51] Add channel_config_set_high_priority (#888)

---
 .../hardware_dma/include/hardware/dma.h       | 59 ++++++++++++-------
 1 file changed, 39 insertions(+), 20 deletions(-)

diff --git a/src/rp2_common/hardware_dma/include/hardware/dma.h b/src/rp2_common/hardware_dma/include/hardware/dma.h
index f823caaec..8ebd2e59e 100644
--- a/src/rp2_common/hardware_dma/include/hardware/dma.h
+++ b/src/rp2_common/hardware_dma/include/hardware/dma.h
@@ -118,7 +118,6 @@ bool dma_channel_is_claimed(uint channel);
  *
  * A DMA channel needs to be configured, these functions provide handy helpers to set up configuration
  * structures. See \ref dma_channel_config
- *
  */
 
 /*! \brief Enumeration of available DMA channel transfer sizes.
@@ -136,10 +135,10 @@ typedef struct {
     uint32_t ctrl;
 } dma_channel_config;
 
-/*! \brief  Set DMA channel read increment
+/*! \brief  Set DMA channel read increment in a channel configuration object
  *  \ingroup channel_config
  *
- * \param c Pointer to channel configuration data
+ * \param c Pointer to channel configuration object
  * \param incr True to enable read address increments, if false, each read will be from the same address
  *             Usually disabled for peripheral to memory transfers
  */
@@ -147,10 +146,10 @@ static inline void channel_config_set_read_increment(dma_channel_config *c, bool
     c->ctrl = incr ? (c->ctrl | DMA_CH0_CTRL_TRIG_INCR_READ_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_INCR_READ_BITS);
 }
 
-/*! \brief  Set DMA channel write increment
+/*! \brief  Set DMA channel write increment in a channel configuration object
  *  \ingroup channel_config
  *
- * \param c Pointer to channel configuration data
+ * \param c Pointer to channel configuration object
  * \param incr True to enable write address increments, if false, each write will be to the same address
  *             Usually disabled for memory to peripheral transfers
  * Usually disabled for memory to peripheral transfers
@@ -159,7 +158,7 @@ static inline void channel_config_set_write_increment(dma_channel_config *c, boo
     c->ctrl = incr ? (c->ctrl | DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS);
 }
 
-/*! \brief  Select a transfer request signal
+/*! \brief  Select a transfer request signal in a channel configuration object
  *  \ingroup channel_config
  *
  * The channel uses the transfer request signal to pace its data transfer rate.
@@ -179,13 +178,13 @@ static inline void channel_config_set_dreq(dma_channel_config *c, uint dreq) {
     c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS) | (dreq << DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB);
 }
 
-/*! \brief  Set DMA channel completion channel
+/*! \brief  Set DMA channel chain_to channel in a channel configuration object
  *  \ingroup channel_config
  *
  * When this channel completes, it will trigger the channel indicated by chain_to. Disable by
  * setting chain_to to itself (the same channel)
  *
- * \param c Pointer to channel configuration data
+ * \param c Pointer to channel configuration object
  * \param chain_to Channel to trigger when this channel completes.
  */
 static inline void channel_config_set_chain_to(dma_channel_config *c, uint chain_to) {
@@ -193,13 +192,13 @@ static inline void channel_config_set_chain_to(dma_channel_config *c, uint chain
     c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS) | (chain_to << DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB);
 }
 
-/*! \brief Set the size of each DMA bus transfer
+/*! \brief Set the size of each DMA bus transfer in a channel configuration object
  *  \ingroup channel_config
  *
  * Set the size of each bus transfer (byte/halfword/word). The read and write addresses
  * advance by the specific amount (1/2/4 bytes) with each transfer.
  *
- * \param c Pointer to channel configuration data
+ * \param c Pointer to channel configuration object
  * \param size See enum for possible values.
  */
 static inline void channel_config_set_transfer_data_size(dma_channel_config *c, enum dma_channel_transfer_size size) {
@@ -207,7 +206,7 @@ static inline void channel_config_set_transfer_data_size(dma_channel_config *c,
     c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) | (((uint)size) << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB);
 }
 
-/*! \brief  Set address wrapping parameters
+/*! \brief  Set address wrapping parameters in a channel configuration object
  *  \ingroup channel_config
  *
  * Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address
@@ -217,7 +216,7 @@ static inline void channel_config_set_transfer_data_size(dma_channel_config *c,
  *
  * 0x0 -> No wrapping.
  *
- * \param c Pointer to channel configuration data
+ * \param c Pointer to channel configuration object
  * \param write True to apply to write addresses, false to apply to read addresses
  * \param size_bits 0 to disable wrapping. Otherwise the size in bits of the changing part of the address.
  *        Effectively wraps the address on a (1 << size_bits) byte boundary.
@@ -229,27 +228,27 @@ static inline void channel_config_set_ring(dma_channel_config *c, bool write, ui
               (write ? DMA_CH0_CTRL_TRIG_RING_SEL_BITS : 0);
 }
 
-/*! \brief  Set DMA byte swapping
+/*! \brief  Set DMA byte swapping config in a channel configuration object
  *  \ingroup channel_config
  *
  * No effect for byte data, for halfword data, the two bytes of each halfword are
  * swapped. For word data, the four bytes of each word are swapped to reverse their order.
  *
- * \param c Pointer to channel configuration data
+ * \param c Pointer to channel configuration object
  * \param bswap True to enable byte swapping
  */
 static inline void channel_config_set_bswap(dma_channel_config *c, bool bswap) {
     c->ctrl = bswap ? (c->ctrl | DMA_CH0_CTRL_TRIG_BSWAP_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_BSWAP_BITS);
 }
 
-/*! \brief  Set IRQ quiet mode
+/*! \brief  Set IRQ quiet mode in a channel configuration object
  *  \ingroup channel_config
  *
  * In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead,
  * an IRQ is raised when NULL is written to a trigger register, indicating the end of a control
  * block chain.
  *
- * \param c Pointer to channel configuration data
+ * \param c Pointer to channel configuration object
  * \param irq_quiet True to enable quiet mode, false to disable.
  */
 static inline void channel_config_set_irq_quiet(dma_channel_config *c, bool irq_quiet) {
@@ -257,13 +256,31 @@ static inline void channel_config_set_irq_quiet(dma_channel_config *c, bool irq_
 }
 
 /*!
- *  \brief Enable/Disable the DMA channel
+ *  \brief Set the channel priority in a channel configuration object
+ *  \ingroup channel_config
+ *
+ * When true, gives a channel preferential treatment in issue scheduling: in each scheduling round,
+ * all high priority channels are considered first, and then only a single low
+ * priority channel, before returning to the high priority channels.
+ *
+ * This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed.
+ * If the DMA is not saturated then a low priority channel will see no loss of throughput.
+ *
+ * \param c Pointer to channel configuration object
+ * \param high_priority True to enable high priority
+ */
+static inline void channel_config_set_high_priority(dma_channel_config *c, bool high_priority) {
+    c->ctrl = high_priority ? (c->ctrl | DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS);
+}
+
+/*!
+ *  \brief Enable/Disable the DMA channel in a channel configuration object
  *  \ingroup channel_config
  *
  * When false, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will
  * remain high if already high)
  *
- * \param c Pointer to channel configuration data
+ * \param c Pointer to channel configuration object
  * \param enable True to enable the DMA channel. When enabled, the channel will respond to triggering events, and start transferring data.
  *
  */
@@ -271,12 +288,12 @@ static inline void channel_config_set_enable(dma_channel_config *c, bool enable)
     c->ctrl = enable ? (c->ctrl | DMA_CH0_CTRL_TRIG_EN_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_EN_BITS);
 }
 
-/*! \brief  Enable access to channel by sniff hardware.
+/*! \brief  Enable access to channel by sniff hardware in a channel configuration object
  *  \ingroup channel_config
  *
  * Sniff HW must be enabled and have this channel selected.
  *
- * \param c Pointer to channel configuration data
+ * \param c Pointer to channel configuration object
  * \param sniff_enable True to enable the Sniff HW access to this DMA channel.
  */
 static inline void channel_config_set_sniff_enable(dma_channel_config *c, bool sniff_enable) {
@@ -297,6 +314,7 @@ static inline void channel_config_set_sniff_enable(dma_channel_config *c, bool s
  * Ring | write=false, size=0 (i.e. off)
  * Byte Swap | false
  * Quiet IRQs | false
+ * High Priority | false
  * Channel Enable | true
  * Sniff Enable | false
  *
@@ -315,6 +333,7 @@ static inline dma_channel_config dma_channel_get_default_config(uint channel) {
     channel_config_set_irq_quiet(&c, false);
     channel_config_set_enable(&c, true);
     channel_config_set_sniff_enable(&c, false);
+    channel_config_set_high_priority( &c, false);
     return c;
 }
 

From 77c04e458c08f274beaf0e623d45511f32faa39f Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Thu, 30 Jun 2022 04:43:20 +0100
Subject: [PATCH 29/51] revert TinyUSB update (#889)

---
 lib/tinyusb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/tinyusb b/lib/tinyusb
index 39069cf4b..4bfab30c0 160000
--- a/lib/tinyusb
+++ b/lib/tinyusb
@@ -1 +1 @@
-Subproject commit 39069cf4be84a4cd1f1a4f3435ea69e606d2b064
+Subproject commit 4bfab30c02279a0530e1a56f4a7c539f2d35a293

From 5e9a5e827b3265fca53529883abdcc87608abad5 Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Wed, 29 Jun 2022 23:03:32 -0500
Subject: [PATCH 30/51] Add Pico W and lwIP support

---
 .gitmodules                                   |   6 +
 README.md                                     |  18 +
 docs/Doxyfile.in                              |   3 +-
 docs/index.h                                  |   7 +
 lib/cyw43-driver                              |   1 +
 lib/lwip                                      |   1 +
 src/boards/include/boards/pico_w.h            | 102 ++++
 src/boards/pico_w.cmake                       |   2 +
 src/common/pico_base/include/pico/error.h     |   8 +-
 src/rp2_common/CMakeLists.txt                 |   4 +
 src/rp2_common/cyw43_driver/CMakeLists.txt    |  81 +++
 .../cyw43_driver/cyw43_bus_pio_spi.c          | 545 ++++++++++++++++++
 .../cyw43_driver/cyw43_bus_pio_spi.pio        |  61 ++
 src/rp2_common/hardware_dma/dma.c             |   6 +
 .../hardware_dma/include/hardware/dma.h       |   9 +-
 src/rp2_common/pico_cyw43_arch/CMakeLists.txt |  66 +++
 src/rp2_common/pico_cyw43_arch/cyw43_arch.c   | 145 +++++
 .../pico_cyw43_arch/cyw43_arch_freertos.c     | 251 ++++++++
 .../pico_cyw43_arch/cyw43_arch_poll.c         | 113 ++++
 .../cyw43_arch_threadsafe_background.c        | 319 ++++++++++
 .../include/cyw43_configport.h                |  73 +++
 .../pico_cyw43_arch/include/pico/cyw43_arch.h | 328 +++++++++++
 .../include/pico/cyw43_arch/arch_common.h     |  74 +++
 .../include/pico/cyw43_arch/arch_freertos.h   |  61 ++
 .../include/pico/cyw43_arch/arch_poll.h       |  58 ++
 .../cyw43_arch/arch_threadsafe_background.h   |  67 +++
 .../rp2040_usb_device_enumeration.c           |   9 +-
 src/rp2_common/pico_lwip/CMakeLists.txt       | 278 +++++++++
 src/rp2_common/pico_lwip/doc.h                |  44 ++
 src/rp2_common/pico_lwip/include/arch/cc.h    |  79 +++
 src/rp2_common/pico_lwip/nosys.c              |  26 +
 src/rp2_common/pico_lwip/random.c             |  29 +
 src/rp2_common/tinyusb/CMakeLists.txt         |   1 +
 test/kitchen_sink/CMakeLists.txt              |  36 +-
 test/kitchen_sink/kitchen_sink.c              |   3 +
 test/kitchen_sink/lwipopts.h                  |  14 +
 36 files changed, 2915 insertions(+), 13 deletions(-)
 create mode 160000 lib/cyw43-driver
 create mode 160000 lib/lwip
 create mode 100644 src/boards/include/boards/pico_w.h
 create mode 100644 src/boards/pico_w.cmake
 create mode 100644 src/rp2_common/cyw43_driver/CMakeLists.txt
 create mode 100644 src/rp2_common/cyw43_driver/cyw43_bus_pio_spi.c
 create mode 100644 src/rp2_common/cyw43_driver/cyw43_bus_pio_spi.pio
 create mode 100644 src/rp2_common/pico_cyw43_arch/CMakeLists.txt
 create mode 100644 src/rp2_common/pico_cyw43_arch/cyw43_arch.c
 create mode 100644 src/rp2_common/pico_cyw43_arch/cyw43_arch_freertos.c
 create mode 100644 src/rp2_common/pico_cyw43_arch/cyw43_arch_poll.c
 create mode 100644 src/rp2_common/pico_cyw43_arch/cyw43_arch_threadsafe_background.c
 create mode 100644 src/rp2_common/pico_cyw43_arch/include/cyw43_configport.h
 create mode 100644 src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch.h
 create mode 100644 src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_common.h
 create mode 100644 src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_freertos.h
 create mode 100644 src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_poll.h
 create mode 100644 src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_threadsafe_background.h
 create mode 100644 src/rp2_common/pico_lwip/CMakeLists.txt
 create mode 100644 src/rp2_common/pico_lwip/doc.h
 create mode 100644 src/rp2_common/pico_lwip/include/arch/cc.h
 create mode 100644 src/rp2_common/pico_lwip/nosys.c
 create mode 100644 src/rp2_common/pico_lwip/random.c
 create mode 100644 test/kitchen_sink/lwipopts.h

diff --git a/.gitmodules b/.gitmodules
index 4846c9c02..a37debee4 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +1,9 @@
 [submodule "tinyusb"]
 	path = lib/tinyusb
 	url = https://github.com/hathach/tinyusb.git
+[submodule "lib/cyw43-driver"]
+	path = lib/cyw43-driver
+	url = https://github.com/georgerobotics/cyw43-driver.git
+[submodule "lib/lwip"]
+	path = lib/lwip
+	url = https://github.com/lwip-tcpip/lwip.git
diff --git a/README.md b/README.md
index db6cef68e..26084ca59 100644
--- a/README.md
+++ b/README.md
@@ -110,6 +110,24 @@ instructions for other platforms, and just in general, we recommend you see [Ras
 
           ```
 
+   * Or by cloning the SDK locally, but without copying `pico_sdk_import.cmake`:
+       1. `git clone` this Raspberry Pi Pico SDK repository
+       2. Setup a `CMakeLists.txt` like:
+
+           ```cmake
+           cmake_minimum_required(VERSION 3.13)
+ 
+           # initialize the SDK directly
+           include(/path/to/pico-sdk/pico_sdk_init.cmake)
+ 
+           project(my_project)
+ 
+           # initialize the Raspberry Pi Pico SDK
+           pico_sdk_init()
+ 
+           # rest of your project
+ 
+           ```
 1. Write your code (see [pico-examples](https://github.com/raspberrypi/pico-examples) or the [Raspberry Pi Pico C/C++ SDK](https://rptl.io/pico-c-sdk) documentation for more information)
 
    About the simplest you can do is a single source file (e.g. hello_world.c)
diff --git a/docs/Doxyfile.in b/docs/Doxyfile.in
index cc133f88f..5dc4be72f 100644
--- a/docs/Doxyfile.in
+++ b/docs/Doxyfile.in
@@ -60,4 +60,5 @@ PREDEFINED             = __not_in_flash_func(x) \
                          __time_critical_func(x) \
                          __not_in_flash(x)= \
                          __no_inline_not_in_flash(x)= \
-                         __attribute__(x)=
+                         __attribute__(x)= \
+                         DOXYGEN_GENERATION=
diff --git a/docs/index.h b/docs/index.h
index c7ef735a5..a334fc32e 100644
--- a/docs/index.h
+++ b/docs/index.h
@@ -56,6 +56,13 @@
  * \defgroup tinyusb_host tinyusb_host
  * @}
  *
+ * \defgroup networking Networking Libraries
+ * Functions for implementing networking
+ * @{
+ * \defgroup pico_lwip pico_lwip
+ * \defgroup pico_cyw43_arch pico_cyw43_arch
+ * @}
+ *
  * \defgroup runtime Runtime Infrastructure
  * Libraries that are used to provide efficient implementation of certain
  * language level and C library functions, as well as CMake INTERFACE libraries
diff --git a/lib/cyw43-driver b/lib/cyw43-driver
new file mode 160000
index 000000000..195dfcc10
--- /dev/null
+++ b/lib/cyw43-driver
@@ -0,0 +1 @@
+Subproject commit 195dfcc10bb6f379e3dea45147590db2203d3c7b
diff --git a/lib/lwip b/lib/lwip
new file mode 160000
index 000000000..239918ccc
--- /dev/null
+++ b/lib/lwip
@@ -0,0 +1 @@
+Subproject commit 239918ccc173cb2c2a62f41a40fd893f57faf1d6
diff --git a/src/boards/include/boards/pico_w.h b/src/boards/include/boards/pico_w.h
new file mode 100644
index 000000000..b4a8bd7ae
--- /dev/null
+++ b/src/boards/include/boards/pico_w.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+// This header may be included by other board headers as "boards/pico.h"
+
+#ifndef _BOARDS_PICO_W_H
+#define _BOARDS_PICO_W_H
+
+// For board detection
+#define RASPBERRYPI_PICO_W
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+// no PICO_DEFAULT_LED_PIN - LED is on Wireless chip
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 4
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 5
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 16
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 17
+#endif
+
+// --- FLASH ---
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024)
+#endif
+
+// note the SMSP mode pin is on WL_GPIO1
+// #define PICO_SMPS_MODE_PIN
+
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#ifndef PICO_RP2040_B1_SUPPORTED
+#define PICO_RP2040_B1_SUPPORTED 0
+#endif
+
+#ifndef CYW43_PIN_WL_HOST_WAKE
+#define CYW43_PIN_WL_HOST_WAKE 24
+#endif
+
+#ifndef CYW43_PIN_WL_REG_ON
+#define CYW43_PIN_WL_REG_ON 23
+#endif
+
+#ifndef CYW43_WL_GPIO_COUNT
+#define CYW43_WL_GPIO_COUNT 3
+#endif
+
+#ifndef CYW43_WL_GPIO_LED_PIN
+#define CYW43_WL_GPIO_LED_PIN 0
+#endif
+
+#endif
diff --git a/src/boards/pico_w.cmake b/src/boards/pico_w.cmake
new file mode 100644
index 000000000..15b901dd2
--- /dev/null
+++ b/src/boards/pico_w.cmake
@@ -0,0 +1,2 @@
+set(PICO_CYW43_SUPPORTED "1" CACHE INTERNAL "Try to add support for PICO_CYW43")
+include(${CMAKE_CURRENT_LIST_DIR}/generic_board.cmake)
diff --git a/src/common/pico_base/include/pico/error.h b/src/common/pico_base/include/pico/error.h
index fadb45ec0..a5cbc3915 100644
--- a/src/common/pico_base/include/pico/error.h
+++ b/src/common/pico_base/include/pico/error.h
@@ -10,14 +10,18 @@
 #ifndef __ASSEMBLER__
 
 /*!
- * Common return codes from pico_sdk methods that return a status
+ * \brief Common return codes from pico_sdk methods that return a status
+ * \ingroup pico_base
  */
-enum {
+enum pico_error_codes {
     PICO_OK = 0,
     PICO_ERROR_NONE = 0,
     PICO_ERROR_TIMEOUT = -1,
     PICO_ERROR_GENERIC = -2,
     PICO_ERROR_NO_DATA = -3,
+    PICO_ERROR_NOT_PERMITTED = -4,
+    PICO_ERROR_INVALID_ARG = -5,
+    PICO_ERROR_IO = -6,
 };
 
 #endif // !__ASSEMBLER__
diff --git a/src/rp2_common/CMakeLists.txt b/src/rp2_common/CMakeLists.txt
index 4ca55becb..0d0f9b93d 100644
--- a/src/rp2_common/CMakeLists.txt
+++ b/src/rp2_common/CMakeLists.txt
@@ -58,6 +58,10 @@ if (NOT PICO_BARE_METAL)
     pico_add_subdirectory(tinyusb)
     pico_add_subdirectory(pico_stdio_usb)
 
+    pico_add_subdirectory(cyw43_driver)
+    pico_add_subdirectory(pico_lwip)
+    pico_add_subdirectory(pico_cyw43_arch)
+
     pico_add_subdirectory(pico_stdlib)
 
     pico_add_subdirectory(pico_cxx_options)
diff --git a/src/rp2_common/cyw43_driver/CMakeLists.txt b/src/rp2_common/cyw43_driver/CMakeLists.txt
new file mode 100644
index 000000000..8951df400
--- /dev/null
+++ b/src/rp2_common/cyw43_driver/CMakeLists.txt
@@ -0,0 +1,81 @@
+if (DEFINED ENV{PICO_CYW43_DRIVER_PATH} AND (NOT PICO_CYW43_DRIVER_PATH))
+    set(PICO_CYW43_DRIVER_PATH $ENV{PICO_CYW43_DRIVER_PATH})
+    message("Using PICO_CYW43_DRIVER_PATH from environment ('${PICO_CYW43_DRIVER_PATH}')")
+endif()
+
+set(CYW43_DRIVER_TEST_FILE "src/cyw43.h")
+
+if (NOT PICO_CYW43_DRIVER_PATH)
+    set(PICO_CYW43_DRIVER_PATH ${PICO_SDK_PATH}/lib/cyw43-driver)
+    if (PICO_CYW43_SUPPORTED AND NOT EXISTS ${PICO_CYW43_DRIVER_PATH}/${CYW43_DRIVER_TEST_FILE})
+        message(WARNING "cyw43-driver submodule has not been initialized; Pico W wireless support will be unavailable
+hint: try 'git submodule update --init' from your SDK directory (${PICO_SDK_PATH}).")
+    endif()
+elseif (NOT EXISTS ${PICO_CYW43_DRIVER_PATH}/${CYW43_DRIVER_TEST_FILE})
+    message(WARNING "PICO_CYW43_DRIVER_PATH specified but content not present.")
+endif()
+
+if (EXISTS ${PICO_CYW43_DRIVER_PATH}/${CYW43_DRIVER_TEST_FILE})
+    message("cyw43-driver available at ${PICO_CYW43_DRIVER_PATH}")
+
+    pico_register_common_scope_var(PICO_CYW43_DRIVER_PATH)
+
+    # base driver without our bus
+    add_library(cyw43_driver_base INTERFACE)
+    target_sources(cyw43_driver_base INTERFACE
+            ${PICO_CYW43_DRIVER_PATH}/src/cyw43_ll.c
+            ${PICO_CYW43_DRIVER_PATH}/src/cyw43_stats.c
+            ${PICO_CYW43_DRIVER_PATH}/src/cyw43_lwip.c
+            ${PICO_CYW43_DRIVER_PATH}/src/cyw43_ctrl.c
+            )
+    target_include_directories(cyw43_driver_base INTERFACE
+            ${PICO_CYW43_DRIVER_PATH}/src
+            ${PICO_CYW43_DRIVER_PATH}/firmware
+            )
+
+    # Build the driver for cyw43 for pico w
+
+    # Firmware stuff
+    set(CYW43_FIRMWARE_BIN 43439A0-7.95.49.00.combined)
+    string(REGEX REPLACE [\\\.\-] _ CYW43_FIRMWARE_BIN_ ${CYW43_FIRMWARE_BIN})
+    string(REGEX MATCH [^_]+_?[^_]*_?[^_]*_?[^_]*_?[^_]* CYW43_FIRMWARE_PRETTY ${CYW43_FIRMWARE_BIN_})
+    set(CYW43_FIRMWARE_PRETTY fw_${CYW43_FIRMWARE_PRETTY})
+    set(RESOURCE_SECNAME .big_const)
+    set(RESOURCE_SECFLAGS contents,alloc,load,readonly,data)
+    set(CYW43_FIRMWARE_OBJ ${CMAKE_CURRENT_BINARY_DIR}/cyw43_resource.o)
+
+    add_custom_target(cyw43_firmware_package DEPENDS ${CYW43_FIRMWARE_OBJ})
+
+    # cyw43_resource.o contains the WiFi and BT firmware as a binary blob
+    add_custom_command(
+            OUTPUT ${CYW43_FIRMWARE_OBJ}
+            DEPENDS ${PICO_CYW43_DRIVER_PATH}/firmware/${CYW43_FIRMWARE_BIN}
+            WORKING_DIRECTORY ${PICO_CYW43_DRIVER_PATH}/firmware
+            COMMAND ${CMAKE_OBJCOPY} -I binary -O elf32-littlearm -B arm
+            --readonly-text
+            --rename-section .data=${RESOURCE_SECNAME},${RESOURCE_SECFLAGS}
+            --redefine-sym _binary_${CYW43_FIRMWARE_BIN_}_start=${CYW43_FIRMWARE_PRETTY}_start
+            --redefine-sym _binary_${CYW43_FIRMWARE_BIN_}_end=${CYW43_FIRMWARE_PRETTY}_end
+            --redefine-sym _binary_${CYW43_FIRMWARE_BIN_}_size=${CYW43_FIRMWARE_PRETTY}_size
+            ${CYW43_FIRMWARE_BIN} ${CYW43_FIRMWARE_OBJ}
+    )
+
+    add_library(cyw43_driver_picow INTERFACE)
+    target_sources(cyw43_driver_picow INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/cyw43_bus_pio_spi.c
+            )
+    pico_generate_pio_header(cyw43_driver_picow ${CMAKE_CURRENT_LIST_DIR}/cyw43_bus_pio_spi.pio)
+    add_dependencies(cyw43_driver_picow INTERFACE cyw43_firmware_package)
+    target_link_libraries(cyw43_driver_picow INTERFACE
+            ${CYW43_FIRMWARE_OBJ}
+            )
+    target_link_libraries(cyw43_driver_picow INTERFACE
+            cyw43_driver_base
+            pico_stdlib
+            hardware_pio
+            hardware_dma
+            hardware_exception
+            )
+
+    pico_promote_common_scope_vars()
+endif()
diff --git a/src/rp2_common/cyw43_driver/cyw43_bus_pio_spi.c b/src/rp2_common/cyw43_driver/cyw43_bus_pio_spi.c
new file mode 100644
index 000000000..0fd17f489
--- /dev/null
+++ b/src/rp2_common/cyw43_driver/cyw43_bus_pio_spi.c
@@ -0,0 +1,545 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+
+#include "pico/stdlib.h"
+#include "hardware/gpio.h"
+#include "hardware/pio.h"
+#include "hardware/clocks.h"
+#include "hardware/structs/iobank0.h"
+#include "hardware/sync.h"
+#include "hardware/dma.h"
+#include "cyw43_bus_pio_spi.pio.h"
+#include "cyw43.h"
+#include "cyw43_internal.h"
+#include "cyw43_spi.h"
+#include "cyw43_debug_pins.h"
+
+#if CYW43_SPI_PIO
+#define WL_REG_ON 23
+#define DATA_OUT_PIN 24u
+#define DATA_IN_PIN 24u
+#define IRQ_PIN 24u
+// #define MONITOR_PIN 3u
+#define CLOCK_PIN 29u
+#define CS_PIN 25u
+#define IRQ_SAMPLE_DELAY_NS 100
+
+#define SPI_PROGRAM_NAME spi_gap01_sample0
+#define SPI_PROGRAM_FUNC __CONCAT(SPI_PROGRAM_NAME, _program)
+#define SPI_PROGRAM_GET_DEFAULT_CONFIG_FUNC __CONCAT(SPI_PROGRAM_NAME, _program_get_default_config)
+#define SPI_OFFSET_END __CONCAT(SPI_PROGRAM_NAME, _offset_end)
+#define SPI_OFFSET_LP1_END __CONCAT(SPI_PROGRAM_NAME, _offset_lp1_end)
+
+#define CLOCK_DIV 2
+#define CLOCK_DIV_MINOR 0
+#define PADS_DRIVE_STRENGTH PADS_BANK0_GPIO0_DRIVE_VALUE_12MA
+
+#if !CYW43_USE_SPI
+#error CYW43_USE_SPI should be true
+#endif
+
+#ifndef NDEBUG
+//#define ENABLE_SPI_DUMPING 1
+#endif
+
+// Set to 1 to enable
+#if ENABLE_SPI_DUMPING //NDEBUG
+#if 0
+#define DUMP_SPI_TRANSACTIONS(A) A
+#else
+static bool enable_spi_packet_dumping; // set to true to dump
+#define DUMP_SPI_TRANSACTIONS(A) if (enable_spi_packet_dumping) {A}
+#endif
+
+static uint32_t counter = 0;
+#else
+#define DUMP_SPI_TRANSACTIONS(A)
+#endif
+
+//#define SWAP32(A) ((((A) & 0xff000000U) >> 8) | (((A) & 0xff0000U) << 8) | (((A) & 0xff00U) >> 8) | (((A) & 0xffU) << 8))
+__force_inline static uint32_t __swap16x2(uint32_t a) {
+    __asm ("rev16 %0, %0" : "+l" (a) : : );
+    return a;
+}
+#define SWAP32(a) __swap16x2(a)
+
+#ifndef CYW43_SPI_PIO_PREFERRED_PIO
+#define CYW43_SPI_PIO_PREFERRED_PIO 1
+#endif
+static_assert(CYW43_SPI_PIO_PREFERRED_PIO >=0 && CYW43_SPI_PIO_PREFERRED_PIO < NUM_PIOS, "");
+
+typedef struct {
+    pio_hw_t *pio;
+    uint8_t pio_func_sel;
+    int8_t pio_offset;
+    int8_t pio_sm;
+    int8_t dma_out;
+    int8_t dma_in;
+} bus_data_t;
+
+static bus_data_t bus_data_instance;
+
+int cyw43_spi_init(cyw43_int_t *self) {
+    // Only does something if CYW43_LOGIC_DEBUG=1
+    logic_debug_init();
+
+    static_assert(NUM_PIOS == 2, "");
+
+    pio_hw_t *pios[2] = {pio0, pio1};
+    uint pio_index = CYW43_SPI_PIO_PREFERRED_PIO;
+    // Check we can add the program
+    if (!pio_can_add_program(pios[pio_index], &SPI_PROGRAM_FUNC)) {
+        pio_index ^= 1;
+        if (!pio_can_add_program(pios[pio_index], &SPI_PROGRAM_FUNC)) {
+            return CYW43_FAIL_FAST_CHECK(-CYW43_EIO);
+        }
+    }
+    assert(!self->bus_data);
+    self->bus_data = &bus_data_instance;
+    bus_data_t *bus_data = (bus_data_t *)self->bus_data;
+    bus_data->pio = pios[pio_index];
+    bus_data->dma_in = -1;
+    bus_data->dma_out = -1;
+
+    static_assert(GPIO_FUNC_PIO1 == GPIO_FUNC_PIO0 + 1, "");
+    bus_data->pio_func_sel = GPIO_FUNC_PIO0 + pio_index;
+    bus_data->pio_sm = (int8_t)pio_claim_unused_sm(bus_data->pio, false);
+    if (bus_data->pio_sm < 0) {
+        cyw43_spi_deinit(self);
+        return CYW43_FAIL_FAST_CHECK(-CYW43_EIO);
+    }
+
+    bus_data->pio_offset = pio_add_program(bus_data->pio, &SPI_PROGRAM_FUNC);
+    pio_sm_config config = SPI_PROGRAM_GET_DEFAULT_CONFIG_FUNC(bus_data->pio_offset);
+
+    sm_config_set_clkdiv_int_frac(&config, CLOCK_DIV, CLOCK_DIV_MINOR);
+    hw_write_masked(&padsbank0_hw->io[CLOCK_PIN],
+                    (uint)PADS_DRIVE_STRENGTH << PADS_BANK0_GPIO0_DRIVE_LSB,
+                    PADS_BANK0_GPIO0_DRIVE_BITS
+    );
+    hw_write_masked(&padsbank0_hw->io[CLOCK_PIN],
+                    (uint)1 << PADS_BANK0_GPIO0_SLEWFAST_LSB,
+                    PADS_BANK0_GPIO0_SLEWFAST_BITS
+    );
+
+    sm_config_set_out_pins(&config, DATA_OUT_PIN, 1);
+    sm_config_set_in_pins(&config, DATA_IN_PIN);
+    sm_config_set_set_pins(&config, DATA_OUT_PIN, 1);
+    sm_config_set_sideset(&config, 1, false, false);
+    sm_config_set_sideset_pins(&config, CLOCK_PIN);
+    sm_config_set_in_shift(&config, false, true, 32);
+    sm_config_set_out_shift(&config, false, true, 32);
+    hw_set_bits(&bus_data->pio->input_sync_bypass, 1u << DATA_IN_PIN);
+    pio_sm_set_config(bus_data->pio, bus_data->pio_sm, &config);
+    pio_sm_set_consecutive_pindirs(bus_data->pio, bus_data->pio_sm, CLOCK_PIN, 1, true);
+    gpio_set_function(DATA_OUT_PIN, bus_data->pio_func_sel);
+    gpio_set_function(CLOCK_PIN, bus_data->pio_func_sel);
+
+    // Set data pin to pull down and schmitt
+    gpio_set_pulls(DATA_IN_PIN, false, true);
+    gpio_set_input_hysteresis_enabled(DATA_IN_PIN, true);
+
+    pio_sm_exec(bus_data->pio, bus_data->pio_sm, pio_encode_set(pio_pins, 1));
+
+    bus_data->dma_out = (int8_t) dma_claim_unused_channel(false);
+    bus_data->dma_in = (int8_t) dma_claim_unused_channel(false);
+    if (bus_data->dma_out < 0 || bus_data->dma_in < 0) {
+        cyw43_spi_deinit(self);
+        return CYW43_FAIL_FAST_CHECK(-CYW43_EIO);
+    }
+    return 0;
+}
+
+void cyw43_spi_deinit(cyw43_int_t *self) {
+    if (self->bus_data) {
+        bus_data_t *bus_data = (bus_data_t *)self->bus_data;
+        if (bus_data->pio_sm >= 0) {
+            if (bus_data->pio_offset != -1)
+                pio_remove_program(bus_data->pio, &SPI_PROGRAM_FUNC, bus_data->pio_offset);
+            pio_sm_unclaim(bus_data->pio, bus_data->pio_sm);
+        }
+        if (bus_data->dma_out >= 0) {
+            dma_channel_unclaim(bus_data->dma_out);
+            bus_data->dma_out = -1;
+        }
+        if (bus_data->dma_in >= 0) {
+            dma_channel_unclaim(bus_data->dma_in);
+            bus_data->dma_in = -1;
+        }
+        self->bus_data = NULL;
+    }
+}
+
+static void cs_set(bool value) {
+    gpio_put(CS_PIN, value);
+}
+
+static __noinline void ns_delay(uint32_t ns) {
+    // cycles = ns * clk_sys_hz / 1,000,000,000
+    uint32_t cycles = ns * (clock_get_hz(clk_sys) >> 16u) / (1000000000u >> 16u);
+    busy_wait_at_least_cycles(cycles);
+}
+
+static void start_spi_comms(cyw43_int_t *self) {
+    bus_data_t *bus_data = (bus_data_t *)self->bus_data;
+    // Pull CS low
+    cs_set(false);
+    gpio_set_function(DATA_OUT_PIN, bus_data->pio_func_sel);
+}
+
+// we need to atomically de-assert CS and enable IRQ
+static void stop_spi_comms(void) {
+    // from this point a positive edge will cause an IRQ to be pending
+    cs_set(true);
+
+    // we need to wait a bit in case the irq line is incorrectly high
+    ns_delay(IRQ_SAMPLE_DELAY_NS);
+}
+
+#if ENABLE_SPI_DUMPING
+static void dump_bytes(const uint8_t *bptr, uint32_t len) {
+    unsigned int i = 0;
+
+    for (i = 0; i < len;) {
+        if ((i & 0x0f) == 0) {
+            printf("\n");
+        } else if ((i & 0x07) == 0) {
+            printf(" ");
+        }
+        printf("%02x ", bptr[i++]);
+    }
+    printf("\n");
+}
+#endif
+
+int cyw43_spi_transfer(cyw43_int_t *self, const uint8_t *tx, size_t tx_length, uint8_t *rx,
+                       size_t rx_length) {
+
+    if ((tx == NULL) && (rx == NULL)) {
+        return CYW43_FAIL_FAST_CHECK(-CYW43_EINVAL);
+    }
+
+    bus_data_t *bus_data = (bus_data_t *)self->bus_data;
+    start_spi_comms(self);
+    if (rx != NULL) {
+        if (tx == NULL) {
+            tx = rx;
+            assert(tx_length && tx_length < rx_length);
+        }
+        DUMP_SPI_TRANSACTIONS(
+                printf("[%lu] bus TX/RX %u bytes rx %u:", counter++, tx_length, rx_length);
+                dump_bytes(tx, tx_length);
+        )
+        assert(!(tx_length & 3));
+        assert(!(((uintptr_t)tx) & 3));
+        assert(!(((uintptr_t)rx) & 3));
+        assert(!(rx_length & 3));
+
+        pio_sm_set_enabled(bus_data->pio, bus_data->pio_sm, false);
+        pio_sm_set_wrap(bus_data->pio, bus_data->pio_sm, bus_data->pio_offset, bus_data->pio_offset + SPI_OFFSET_END - 1);
+        pio_sm_clear_fifos(bus_data->pio, bus_data->pio_sm);
+        pio_sm_set_pindirs_with_mask(bus_data->pio, bus_data->pio_sm, 1u << DATA_OUT_PIN, 1u << DATA_OUT_PIN);
+        pio_sm_restart(bus_data->pio, bus_data->pio_sm);
+        pio_sm_clkdiv_restart(bus_data->pio, bus_data->pio_sm);
+        pio_sm_put(bus_data->pio, bus_data->pio_sm, tx_length * 8 - 1);
+        pio_sm_exec(bus_data->pio, bus_data->pio_sm, pio_encode_out(pio_x, 32));
+        pio_sm_put(bus_data->pio, bus_data->pio_sm, (rx_length - tx_length) * 8 - 1);
+        pio_sm_exec(bus_data->pio, bus_data->pio_sm, pio_encode_out(pio_y, 32));
+        pio_sm_exec(bus_data->pio, bus_data->pio_sm, pio_encode_jmp(bus_data->pio_offset));
+        dma_channel_abort(bus_data->dma_out);
+        dma_channel_abort(bus_data->dma_in);
+
+        dma_channel_config out_config = dma_channel_get_default_config(bus_data->dma_out);
+        channel_config_set_bswap(&out_config, true);
+        channel_config_set_dreq(&out_config, pio_get_dreq(bus_data->pio, 0, true));
+
+        dma_channel_configure(bus_data->dma_out, &out_config, &bus_data->pio->txf[0], tx, tx_length / 4, true);
+
+        dma_channel_config in_config = dma_channel_get_default_config(bus_data->dma_in);
+        channel_config_set_bswap(&in_config, true);
+        channel_config_set_dreq(&in_config, pio_get_dreq(bus_data->pio, 0, false));
+        channel_config_set_write_increment(&in_config, true);
+        channel_config_set_read_increment(&in_config, false);
+        dma_channel_configure(bus_data->dma_in, &in_config, rx + tx_length, &bus_data->pio->rxf[0], rx_length / 4 - tx_length / 4, true);
+
+        pio_sm_set_enabled(bus_data->pio, bus_data->pio_sm, true);
+        __compiler_memory_barrier();
+
+        dma_channel_wait_for_finish_blocking(bus_data->dma_out);
+        dma_channel_wait_for_finish_blocking(bus_data->dma_in);
+
+        __compiler_memory_barrier();
+        memset(rx, 0, tx_length); // make sure we don't have garbage in what would have been returned data if using real SPI
+    } else if (tx != NULL) {
+        DUMP_SPI_TRANSACTIONS(
+                printf("[%lu] bus TX only %u bytes:", counter++, tx_length);
+                dump_bytes(tx, tx_length);
+        )
+        assert(!(((uintptr_t)tx) & 3));
+        assert(!(tx_length & 3));
+        pio_sm_set_enabled(bus_data->pio, bus_data->pio_sm, false);
+        pio_sm_set_wrap(bus_data->pio, bus_data->pio_sm, bus_data->pio_offset, bus_data->pio_offset + SPI_OFFSET_LP1_END - 1);
+        pio_sm_clear_fifos(bus_data->pio, bus_data->pio_sm);
+        pio_sm_set_pindirs_with_mask(bus_data->pio, bus_data->pio_sm, 1u << DATA_OUT_PIN, 1u << DATA_OUT_PIN);
+        pio_sm_restart(bus_data->pio, bus_data->pio_sm);
+        pio_sm_clkdiv_restart(bus_data->pio, bus_data->pio_sm);
+        pio_sm_put(bus_data->pio, bus_data->pio_sm, tx_length * 8 - 1);
+        pio_sm_exec(bus_data->pio, bus_data->pio_sm, pio_encode_out(pio_x, 32));
+        pio_sm_put(bus_data->pio, bus_data->pio_sm, 0);
+        pio_sm_exec(bus_data->pio, bus_data->pio_sm, pio_encode_out(pio_y, 32));
+        pio_sm_exec(bus_data->pio, bus_data->pio_sm, pio_encode_jmp(bus_data->pio_offset));
+        dma_channel_abort(bus_data->dma_out);
+
+        dma_channel_config out_config = dma_channel_get_default_config(bus_data->dma_out);
+        channel_config_set_bswap(&out_config, true);
+        channel_config_set_dreq(&out_config, pio_get_dreq(bus_data->pio, 0, true));
+
+        dma_channel_configure(bus_data->dma_out, &out_config, &bus_data->pio->txf[0], tx, tx_length / 4, true);
+
+        bus_data->pio->fdebug = 1u << PIO_FDEBUG_TXSTALL_LSB;
+        pio_sm_set_enabled(bus_data->pio, 0, true);
+        while (!(bus_data->pio->fdebug & (1u << PIO_FDEBUG_TXSTALL_LSB))) {
+            tight_loop_contents(); // todo timeout
+        }
+        __compiler_memory_barrier();
+        pio_sm_set_enabled(bus_data->pio, bus_data->pio_sm, false);
+        pio_sm_set_consecutive_pindirs(bus_data->pio, bus_data->pio_sm, DATA_IN_PIN, 1, false);
+    } else if (rx != NULL) { /* currently do one at a time */
+        DUMP_SPI_TRANSACTIONS(
+                printf("[%lu] bus TX %u bytes:", counter++, rx_length);
+                dump_bytes(rx, rx_length);
+        )
+        panic_unsupported();
+    }
+    pio_sm_exec(bus_data->pio, bus_data->pio_sm, pio_encode_mov(pio_pins, pio_null)); // for next time we turn output on
+
+    stop_spi_comms();
+    DUMP_SPI_TRANSACTIONS(
+            printf("RXed:");
+            dump_bytes(rx, rx_length);
+            printf("\n");
+    )
+
+    return 0;
+}
+
+// Initialise our gpios
+void cyw43_spi_gpio_setup(void) {
+    // Setup WL_REG_ON (23)
+    gpio_init(WL_REG_ON);
+    gpio_set_dir(WL_REG_ON, GPIO_OUT);
+    gpio_pull_up(WL_REG_ON);
+
+    // Setup DO, DI and IRQ (24)
+    gpio_init(DATA_OUT_PIN);
+    gpio_set_dir(DATA_OUT_PIN, GPIO_OUT);
+    gpio_put(DATA_OUT_PIN, false);
+
+    // Setup CS (25)
+    gpio_init(CS_PIN);
+    gpio_set_dir(CS_PIN, GPIO_OUT);
+    gpio_put(CS_PIN, true);
+}
+
+// Reset wifi chip
+void cyw43_spi_reset(void) {
+    gpio_put(WL_REG_ON, false); // off
+    sleep_ms(20);
+    gpio_put(WL_REG_ON, true); // on
+    sleep_ms(250);
+
+    // Setup IRQ (24) - also used for DO, DI
+    gpio_init(IRQ_PIN);
+    gpio_set_dir(IRQ_PIN, GPIO_IN);
+}
+
+static inline uint32_t make_cmd(bool write, bool inc, uint32_t fn, uint32_t addr, uint32_t sz) {
+    return write << 31 | inc << 30 | fn << 28 | (addr & 0x1ffff) << 11 | sz;
+}
+
+#if CYW43_VERBOSE_DEBUG
+static const char *func_name(int fn) {
+    switch (fn)
+    {
+        case BUS_FUNCTION:
+            return "BUS_FUNCTION";
+        case BACKPLANE_FUNCTION:
+            return "BACKPLANE_FUNCTION";
+        case WLAN_FUNCTION:
+            return "WLAN_FUNCTION";
+        default:
+            return "UNKNOWN";
+    }
+}
+#endif
+
+uint32_t read_reg_u32_swap(cyw43_int_t *self, uint32_t fn, uint32_t reg) {
+    uint32_t buf[2] = {0};
+    assert(fn != BACKPLANE_FUNCTION);
+    buf[0] = SWAP32(make_cmd(false, true, fn, reg, 4));
+    int ret = cyw43_spi_transfer(self, NULL, 4, (uint8_t *)buf, 8);
+    if (ret != 0) {
+        return ret;
+    }
+    return SWAP32(buf[1]);
+}
+
+static inline uint32_t _cyw43_read_reg(cyw43_int_t *self, uint32_t fn, uint32_t reg, uint size) {
+    // Padding plus max read size of 32 bits + another 4?
+    static_assert(WHD_BUS_SPI_BACKPLANE_READ_PADD_SIZE % 4 == 0, "");
+    uint32_t buf32[WHD_BUS_SPI_BACKPLANE_READ_PADD_SIZE/4 + 1 + 1];
+    uint8_t *buf = (uint8_t *)buf32;
+    const uint32_t padding = (fn == BACKPLANE_FUNCTION) ? WHD_BUS_SPI_BACKPLANE_READ_PADD_SIZE : 0; // Add response delay
+    buf32[0] = make_cmd(false, true, fn, reg, size + padding);
+
+    if (fn == BACKPLANE_FUNCTION) {
+        logic_debug_set(pin_BACKPLANE_READ, 1);
+    }
+    int ret = cyw43_spi_transfer(self, NULL, 4, buf, 8 + padding);
+    if (fn == BACKPLANE_FUNCTION) {
+        logic_debug_set(pin_BACKPLANE_READ, 0);
+    }
+
+    if (ret != 0) {
+        return ret;
+    }
+    uint32_t result = buf32[padding > 0 ? 2 : 1];
+    CYW43_VDEBUG("cyw43_read_reg_u%d %s 0x%lx=0x%lx\n", size * 8, func_name(fn), reg, result);
+    return result;
+}
+
+uint32_t cyw43_read_reg_u32(cyw43_int_t *self, uint32_t fn, uint32_t reg) {
+    return _cyw43_read_reg(self, fn, reg, 4);
+}
+
+int cyw43_read_reg_u16(cyw43_int_t *self, uint32_t fn, uint32_t reg) {
+    return _cyw43_read_reg(self, fn, reg, 2);
+}
+
+int cyw43_read_reg_u8(cyw43_int_t *self, uint32_t fn, uint32_t reg) {
+    return _cyw43_read_reg(self, fn, reg, 1);
+}
+
+// This is only used to switch the word order on boot
+int write_reg_u32_swap(cyw43_int_t *self, uint32_t fn, uint32_t reg, uint32_t val) {
+    uint32_t buf[2];
+    // Boots up in little endian so command needs swapping too
+    buf[0] = SWAP32(make_cmd(true, true, fn, reg, 4));
+    buf[1] = SWAP32(val);
+    int ret = cyw43_spi_transfer(self, (uint8_t *)buf, 8, NULL, 0);
+    CYW43_VDEBUG("write_reg_u32_swap %s 0x%lx=0x%lx\n", func_name(fn), reg, val);
+    return ret;
+}
+
+static inline int _cyw43_write_reg(cyw43_int_t *self, uint32_t fn, uint32_t reg, uint32_t val, uint size) {
+    uint32_t buf[2];
+    buf[0] = make_cmd(true, true, fn, reg, size);
+    buf[1] = val;
+    if (fn == BACKPLANE_FUNCTION) {
+        // In case of f1 overflow
+        self->last_size = 8;
+        self->last_header[0] = buf[0];
+        self->last_header[1] = buf[1];
+        self->last_backplane_window = self->cur_backplane_window;
+    }
+
+    if (fn == BACKPLANE_FUNCTION) {
+        logic_debug_set(pin_BACKPLANE_WRITE, 1);
+    }
+
+    int ret = cyw43_spi_transfer(self, (uint8_t *)buf, 8, NULL, 0);
+
+    if (fn == BACKPLANE_FUNCTION) {
+        logic_debug_set(pin_BACKPLANE_WRITE, 0);
+    }
+
+    CYW43_VDEBUG("cyw43_write_reg_u%d %s 0x%lx=0x%lx\n", size * 8, func_name(fn), reg, val);
+    return ret;
+}
+
+int cyw43_write_reg_u32(cyw43_int_t *self, uint32_t fn, uint32_t reg, uint32_t val) {
+    return _cyw43_write_reg(self, fn, reg, val, 4);
+}
+
+int cyw43_write_reg_u16(cyw43_int_t *self, uint32_t fn, uint32_t reg, uint16_t val) {
+    return _cyw43_write_reg(self, fn, reg, val, 2);
+}
+
+int cyw43_write_reg_u8(cyw43_int_t *self, uint32_t fn, uint32_t reg, uint32_t val) {
+    return _cyw43_write_reg(self, fn, reg, val, 1);
+}
+
+#if MAX_BLOCK_SIZE > 0x7f8
+#error Block size is wrong for SPI
+#endif
+
+// Assumes we're reading into spid_buf
+int cyw43_read_bytes(cyw43_int_t *self, uint32_t fn, uint32_t addr, size_t len, uint8_t *buf) {
+    assert(fn != BACKPLANE_FUNCTION || (len <= 64 && (addr + len) <= 0x8000));
+    const uint32_t padding = (fn == BACKPLANE_FUNCTION) ? 4 : 0; // Add response delay
+    size_t aligned_len = (len + 3) & ~3;
+    assert(aligned_len > 0 && aligned_len <= 0x7f8);
+    self->spi_header[padding > 0 ? 0 : 1] = make_cmd(false, true, fn, addr, len + padding);
+    if (fn == WLAN_FUNCTION) {
+        logic_debug_set(pin_WIFI_RX, 1);
+    }
+    int ret = cyw43_spi_transfer(self, NULL, 4, (uint8_t *)&self->spi_header[padding > 0 ? 0 : 1], aligned_len + 4 + padding);
+    if (fn == WLAN_FUNCTION) {
+        logic_debug_set(pin_WIFI_RX, 0);
+    }
+    if (ret != 0) {
+        printf("cyw43_read_bytes error %d", ret);
+        return ret;
+    }
+    if (buf != self->spid_buf) { // avoid a copy in the usual case just to add the header
+        memcpy(buf, self->spid_buf, len);
+    }
+    return 0;
+}
+
+// See whd_bus_spi_transfer_bytes
+// Note, uses spid_buf if src isn't using it already
+// Apart from firmware download this appears to only be used for wlan functions?
+int cyw43_write_bytes(cyw43_int_t *self, uint32_t fn, uint32_t addr, size_t len, const uint8_t *src) {
+    assert(fn != BACKPLANE_FUNCTION || (len <= 64 && (addr + len) <= 0x8000));
+    size_t aligned_len = (len + 3) & ~3u;
+    assert(aligned_len > 0 && aligned_len <= 0x7f8);
+    if (fn == WLAN_FUNCTION) {
+        // Wait for FIFO to be ready to accept data
+        int f2_ready_attempts = 1000;
+        while (f2_ready_attempts-- > 0) {
+            uint32_t bus_status = cyw43_read_reg_u32(self, BUS_FUNCTION, SPI_STATUS_REGISTER);
+            if (bus_status & STATUS_F2_RX_READY) {
+                logic_debug_set(pin_F2_RX_READY_WAIT, 0);
+                break;
+            } else {
+                logic_debug_set(pin_F2_RX_READY_WAIT, 1);
+            }
+        }
+        if (f2_ready_attempts <= 0) {
+            printf("F2 not ready\n");
+            return CYW43_FAIL_FAST_CHECK(-CYW43_EIO);
+        }
+    }
+    if (src == self->spid_buf) { // avoid a copy in the usual case just to add the header
+        self->spi_header[1] = make_cmd(true, true, fn, addr, len);
+        logic_debug_set(pin_WIFI_TX, 1);
+        int res = cyw43_spi_transfer(self, (uint8_t *)&self->spi_header[1], aligned_len + 4, NULL, 0);
+        logic_debug_set(pin_WIFI_TX, 0);
+        return res;
+    } else {
+        // todo: would be nice to get rid of this. Only used for firmware download?
+        assert(src < self->spid_buf || src >= (self->spid_buf + sizeof(self->spid_buf)));
+        self->spi_header[1] = make_cmd(true, true, fn, addr, len);
+        memcpy(self->spid_buf, src, len);
+        return cyw43_spi_transfer(self, (uint8_t *)&self->spi_header[1], aligned_len + 4, NULL, 0);
+    }
+}
+#endif
diff --git a/src/rp2_common/cyw43_driver/cyw43_bus_pio_spi.pio b/src/rp2_common/cyw43_driver/cyw43_bus_pio_spi.pio
new file mode 100644
index 000000000..ea0d19549
--- /dev/null
+++ b/src/rp2_common/cyw43_driver/cyw43_bus_pio_spi.pio
@@ -0,0 +1,61 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+.program spi_gap0_sample1
+.side_set 1
+
+; always transmit multiple of 32 bytes
+lp: out pins, 1             side 0
+    jmp x-- lp              side 1
+public lp1_end:
+    set pindirs, 0          side 0
+lp2:
+    in pins, 1              side 1
+    jmp y-- lp2             side 0
+public end:
+
+.program spi_gap01_sample0
+.side_set 1
+
+; always transmit multiple of 32 bytes
+lp: out pins, 1             side 0
+    jmp x-- lp              side 1
+public lp1_end:
+    set pindirs, 0          side 0
+    nop                     side 1
+lp2:
+    in pins, 1              side 0
+    jmp y-- lp2             side 1
+public end:
+
+.program spi_gap010_sample1
+.side_set 1
+
+; always transmit multiple of 32 bytes
+lp: out pins, 1             side 0
+    jmp x-- lp              side 1
+public lp1_end:
+    set pindirs, 0          side 0
+    nop                     side 1
+    nop                     side 0
+lp2:
+    in pins, 1              side 1
+    jmp y-- lp2             side 0
+public end:
+
+.program spi_gap0_sample1_regular
+.side_set 1
+
+; always transmit multiple of 32 bytes
+lp: out pins, 1             side 0
+    jmp x-- lp              side 1
+public lp1_end:
+    set pindirs, 0          side 0
+lp2:
+    in pins, 1              side 1
+    jmp y-- lp2             side 0
+public end:
+
diff --git a/src/rp2_common/hardware_dma/dma.c b/src/rp2_common/hardware_dma/dma.c
index 90fde06b4..f142b5379 100644
--- a/src/rp2_common/hardware_dma/dma.c
+++ b/src/rp2_common/hardware_dma/dma.c
@@ -36,6 +36,12 @@ void dma_channel_unclaim(uint channel) {
     hw_claim_clear((uint8_t *) &_claimed, channel);
 }
 
+void dma_unclaim_mask(uint32_t mask) {
+    for(uint i = 0; mask; i++, mask >>= 1u) {
+        if (mask & 1u) dma_channel_unclaim(i);
+    }
+}
+
 int dma_claim_unused_channel(bool required) {
     return hw_claim_unused_from_range((uint8_t*)&_claimed, required, 0, NUM_DMA_CHANNELS-1, "No DMA channels are available");
 }
diff --git a/src/rp2_common/hardware_dma/include/hardware/dma.h b/src/rp2_common/hardware_dma/include/hardware/dma.h
index 8ebd2e59e..ec735640a 100644
--- a/src/rp2_common/hardware_dma/include/hardware/dma.h
+++ b/src/rp2_common/hardware_dma/include/hardware/dma.h
@@ -88,12 +88,17 @@ void dma_claim_mask(uint32_t channel_mask);
 /*! \brief Mark a dma channel as no longer used
  *  \ingroup hardware_dma
  *
- * Method for cooperative claiming of hardware.
- *
  * \param channel the dma channel to release
  */
 void dma_channel_unclaim(uint channel);
 
+/*! \brief Mark multiple dma channels as no longer used
+ *  \ingroup hardware_dma
+ *
+ * \param channel_mask Bitfield of all channels to unclaim (bit 0 == channel 0, bit 1 == channel 1 etc)
+ */
+void dma_unclaim_mask(uint32_t channel_mask);
+
 /*! \brief Claim a free dma channel
  *  \ingroup hardware_dma
  *
diff --git a/src/rp2_common/pico_cyw43_arch/CMakeLists.txt b/src/rp2_common/pico_cyw43_arch/CMakeLists.txt
new file mode 100644
index 000000000..ede03f12d
--- /dev/null
+++ b/src/rp2_common/pico_cyw43_arch/CMakeLists.txt
@@ -0,0 +1,66 @@
+if (PICO_CYW43_SUPPORTED) # set by BOARD=pico-w
+    if (TARGET cyw43_driver_picow)
+        message("Enabling build support for Pico W wireless.")
+
+        pico_add_impl_library(pico_cyw43_arch)
+        target_sources(pico_cyw43_arch INTERFACE
+                ${CMAKE_CURRENT_LIST_DIR}/cyw43_arch.c
+                ${CMAKE_CURRENT_LIST_DIR}/cyw43_arch_poll.c
+                ${CMAKE_CURRENT_LIST_DIR}/cyw43_arch_threadsafe_background.c
+                ${CMAKE_CURRENT_LIST_DIR}/cyw43_arch_freertos.c
+                )
+
+        target_include_directories(pico_cyw43_arch INTERFACE
+                ${CMAKE_CURRENT_LIST_DIR}/include)
+
+        target_link_libraries(pico_cyw43_arch INTERFACE
+                pico_unique_id
+                cyw43_driver_picow)
+
+        if (NOT TARGET pico_lwip)
+            message(WARNING "lwIP is not available; Full Pico W wireless support will be unavailable too")
+        else()
+            add_library(pico_cyw43_arch_lwip_poll INTERFACE)
+            target_link_libraries(pico_cyw43_arch_lwip_poll INTERFACE
+                    pico_cyw43_arch
+                    pico_lwip
+                    pico_lwip_nosys)
+            target_compile_definitions(pico_cyw43_arch_lwip_poll INTERFACE
+                    CYW43_LWIP=1
+                    PICO_CYW43_ARCH_POLL=1
+                    )
+
+            add_library(pico_cyw43_arch_lwip_threadsafe_background INTERFACE)
+            target_link_libraries(pico_cyw43_arch_lwip_threadsafe_background INTERFACE
+                    pico_cyw43_arch
+                    pico_lwip
+                    pico_lwip_nosys)
+            target_compile_definitions(pico_cyw43_arch_lwip_threadsafe_background INTERFACE
+                    CYW43_LWIP=1
+                    PICO_CYW43_ARCH_THREADSAFE_BACKGROUND=1
+                    )
+
+            add_library(pico_cyw43_arch_lwip_sys_freertos INTERFACE)
+            target_link_libraries(pico_cyw43_arch_lwip_sys_freertos INTERFACE
+                    pico_cyw43_arch
+                    pico_lwip
+                    pico_lwip_contrib_freertos)
+            target_compile_definitions(pico_cyw43_arch_lwip_sys_freertos INTERFACE
+                    CYW43_LWIP=1
+                    LWIP_PROVIDE_ERRNO=1
+                    PICO_CYW43_ARCH_FREERTOS=1
+                    )
+        endif()
+
+        add_library(pico_cyw43_arch_none INTERFACE)
+        target_link_libraries(pico_cyw43_arch_none INTERFACE pico_cyw43_arch)
+        target_compile_definitions(pico_cyw43_arch_none INTERFACE
+                CYW43_LWIP=0
+                PICO_CYW43_ARCH_THREADSAFE_BACKGROUND=1 # none still uses threadsafe_background to make gpio use easy
+                )
+    endif()
+endif()
+
+if (PICO_CYW43_DRIVER_PATH AND EXISTS "${PICO_CYW43_DRIVER_PATH}")
+    pico_add_doxygen(${PICO_CYW43_DRIVER_PATH}/src)
+endif()
\ No newline at end of file
diff --git a/src/rp2_common/pico_cyw43_arch/cyw43_arch.c b/src/rp2_common/pico_cyw43_arch/cyw43_arch.c
new file mode 100644
index 000000000..c328d6e6a
--- /dev/null
+++ b/src/rp2_common/pico_cyw43_arch/cyw43_arch.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "pico/unique_id.h"
+#include "cyw43.h"
+#include "pico/cyw43_arch.h"
+#include "cyw43_ll.h"
+#include "cyw43_stats.h"
+
+#if CYW43_ARCH_DEBUG_ENABLED
+#define CYW43_ARCH_DEBUG(...) printf(__VA_ARGS__)
+#else
+#define CYW43_ARCH_DEBUG(...) ((void)0)
+#endif
+
+static uint32_t country_code = PICO_CYW43_ARCH_DEFAULT_COUNTRY_CODE;
+
+void cyw43_arch_enable_sta_mode() {
+    assert(cyw43_is_initialized(&cyw43_state));
+    cyw43_wifi_set_up(&cyw43_state, CYW43_ITF_STA, true, cyw43_arch_get_country_code());
+}
+
+void cyw43_arch_enable_ap_mode(const char *ssid, const char *password, uint32_t auth) {
+    assert(cyw43_is_initialized(&cyw43_state));
+    cyw43_wifi_ap_set_ssid(&cyw43_state, strlen(ssid), (const uint8_t *) ssid);
+    if (password) {
+        cyw43_wifi_ap_set_password(&cyw43_state, strlen(password), (const uint8_t *) password);
+        cyw43_wifi_ap_set_auth(&cyw43_state, auth);
+    } else {
+        cyw43_wifi_ap_set_auth(&cyw43_state, CYW43_AUTH_OPEN);
+    }
+    cyw43_wifi_set_up(&cyw43_state, CYW43_ITF_AP, true, cyw43_arch_get_country_code());
+}
+
+#if CYW43_ARCH_DEBUG_ENABLED
+// Return a string for the wireless state
+static const char* status_name(int status)
+{
+    switch (status) {
+    case CYW43_LINK_DOWN:
+        return "link down";
+    case CYW43_LINK_JOIN:
+        return "joining";
+    case CYW43_LINK_NOIP:
+        return "no ip";
+    case CYW43_LINK_UP:
+        return "link up";
+    case CYW43_LINK_FAIL:
+        return "link fail";
+    case CYW43_LINK_NONET:
+        return "network fail";
+    case CYW43_LINK_BADAUTH:
+        return "bad auth";
+    }
+    return "unknown";
+}
+#endif
+
+int cyw43_arch_wifi_connect_async(const char *ssid, const char *pw, uint32_t auth) {
+    if (!pw) auth = CYW43_AUTH_OPEN;
+    // Connect to wireless
+    return cyw43_wifi_join(&cyw43_state, strlen(ssid), (const uint8_t *)ssid, pw ? strlen(pw) : 0, (const uint8_t *)pw, auth, NULL, CYW43_ITF_STA);
+}
+
+// Connect to wireless, return with success when an IP address has been assigned
+int cyw43_arch_wifi_connect_until(const char *ssid, const char *pw, uint32_t auth, absolute_time_t until) {
+    int err = cyw43_arch_wifi_connect_async(ssid, pw, auth);
+    if (err) return err;
+
+    int status = CYW43_LINK_UP + 1;
+    while(status >= 0 && status != CYW43_LINK_UP) {
+        int new_status = cyw43_tcpip_link_status(&cyw43_state, CYW43_ITF_STA);
+        if (new_status != status) {
+            status = new_status;
+            CYW43_ARCH_DEBUG("connect status: %s\n", status_name(status));
+        }
+        // in case polling is required
+        cyw43_arch_poll();
+        best_effort_wfe_or_timeout(until);
+        if (time_reached(until)) {
+            return PICO_ERROR_TIMEOUT;
+        }
+    }
+    return status == CYW43_LINK_UP ? 0 : status;
+}
+
+int cyw43_arch_wifi_connect_blocking(const char *ssid, const char *pw, uint32_t auth) {
+    return cyw43_arch_wifi_connect_until(ssid, pw, auth, at_the_end_of_time);
+}
+
+int cyw43_arch_wifi_connect_timeout_ms(const char *ssid, const char *pw, uint32_t auth, uint32_t timeout_ms) {
+    return cyw43_arch_wifi_connect_until(ssid, pw, auth, make_timeout_time_ms(timeout_ms));
+}
+
+// todo maybe add an #ifdef in cyw43_driver
+uint32_t storage_read_blocks(__unused uint8_t *dest, __unused uint32_t block_num, __unused uint32_t num_blocks) {
+    // shouldn't be used
+    panic_unsupported();
+}
+
+// Generate a mac address if one is not set in otp
+void cyw43_hal_generate_laa_mac(__unused int idx, uint8_t buf[6]) {
+    CYW43_DEBUG("Warning. No mac in otp. Generating mac from board id\n");
+    pico_unique_board_id_t board_id;
+    pico_get_unique_board_id(&board_id);
+    memcpy(buf, &board_id.id[2], 6);
+    buf[0] &= (uint8_t)~0x1; // unicast
+    buf[0] |= 0x2; // locally administered
+}
+
+// Return mac address
+void cyw43_hal_get_mac(__unused int idx, uint8_t buf[6]) {
+    // The mac should come from cyw43 otp.
+    // This is loaded into the state after the driver is initialised
+    // cyw43_hal_generate_laa_mac is called by the driver to generate a mac if otp is not set
+    memcpy(buf, cyw43_state.mac, 6);
+}
+
+uint32_t cyw43_arch_get_country_code(void) {
+    return country_code;
+}
+
+int cyw43_arch_init_with_country(uint32_t country) {
+    country_code = country;
+    return cyw43_arch_init();
+}
+
+void cyw43_arch_gpio_put(uint wl_gpio, bool value) {
+    invalid_params_if(CYW43_ARCH, wl_gpio >= CYW43_WL_GPIO_COUNT);
+    cyw43_gpio_set(&cyw43_state, (int)wl_gpio, value);
+}
+
+bool cyw43_arch_gpio_get(uint wl_gpio) {
+    invalid_params_if(CYW43_ARCH, wl_gpio >= CYW43_WL_GPIO_COUNT);
+    bool value = false;
+    cyw43_gpio_get(&cyw43_state, (int)wl_gpio, &value);
+    return value;
+}
diff --git a/src/rp2_common/pico_cyw43_arch/cyw43_arch_freertos.c b/src/rp2_common/pico_cyw43_arch/cyw43_arch_freertos.c
new file mode 100644
index 000000000..88dde6ece
--- /dev/null
+++ b/src/rp2_common/pico_cyw43_arch/cyw43_arch_freertos.c
@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+
+#include "pico/cyw43_arch.h"
+
+#include "hardware/gpio.h"
+#include "hardware/irq.h"
+#include "hardware/sync.h"
+
+#include "cyw43_stats.h"
+
+#if CYW43_LWIP
+#include <lwip/tcpip.h>
+#endif
+
+#if PICO_CYW43_ARCH_FREERTOS
+
+// FreeRTOS includes
+#include "FreeRTOS.h"
+#include "timers.h"
+#include "semphr.h"
+
+#if NO_SYS
+#error example_cyw43_arch_frertos_sys requires NO_SYS=0
+#endif
+
+#ifndef CYW43_TASK_PRIORITY
+#define CYW43_TASK_PRIORITY ( tskIDLE_PRIORITY + 4)
+#endif
+
+#ifndef CYW43_SLEEP_CHECK_MS
+#define CYW43_SLEEP_CHECK_MS 50 // How often to run lwip callback
+#endif
+
+#define CYW43_GPIO_IRQ_HANDLER_PRIORITY 0x40
+
+static void signal_cyw43_task(void);
+
+#if !LWIP_TCPIP_CORE_LOCKING_INPUT
+static SemaphoreHandle_t cyw43_mutex;
+#endif
+static TimerHandle_t timer_handle;
+static TaskHandle_t cyw43_task_handle;
+static volatile bool cyw43_task_should_exit;
+static SemaphoreHandle_t cyw43_worker_ran_sem;
+static uint8_t cyw43_core_num;
+
+// Called in low priority pendsv interrupt only to do lwip processing and check cyw43 sleep
+static void periodic_worker(__unused TimerHandle_t handle)
+{
+#if CYW43_USE_STATS
+    static uint32_t counter;
+    if (counter++ % (30000 / LWIP_SYS_CHECK_MS) == 0) {
+        cyw43_dump_stats();
+    }
+#endif
+
+    CYW43_STAT_INC(LWIP_RUN_COUNT);
+    if (cyw43_poll) {
+        if (cyw43_sleep > 0) {
+            if (--cyw43_sleep == 0) {
+                signal_cyw43_task();
+            }
+        }
+    }
+}
+
+void cyw43_await_background_or_timeout_us(uint32_t timeout_us) {
+    // if we are called from within an IRQ, then don't wait (we are only ever called in a polling loop)
+    assert(!portCHECK_IF_IN_ISR());
+    xSemaphoreTake(cyw43_worker_ran_sem, pdMS_TO_TICKS(timeout_us / 1000));
+}
+
+// GPIO interrupt handler to tell us there's cyw43 has work to do
+static void gpio_irq_handler(void)
+{
+    uint32_t events = gpio_get_irq_event_mask(CYW43_PIN_WL_HOST_WAKE);
+    if (events & GPIO_IRQ_LEVEL_HIGH) {
+        // As we use a high level interrupt, it will go off forever until it's serviced
+        // So disable the interrupt until this is done. It's re-enabled again by CYW43_POST_POLL_HOOK
+        // which is called at the end of cyw43_poll_func
+        gpio_set_irq_enabled(CYW43_PIN_WL_HOST_WAKE, GPIO_IRQ_LEVEL_HIGH, false);
+        signal_cyw43_task();
+        CYW43_STAT_INC(IRQ_COUNT);
+    }
+}
+
+// Low priority interrupt handler to perform background processing
+static void cyw43_task(__unused void *param) {
+    do {
+        ulTaskNotifyTake(pdFALSE, portMAX_DELAY);
+        if (cyw43_task_should_exit) break;
+        cyw43_thread_enter();
+        if (cyw43_poll) cyw43_poll();
+        cyw43_thread_exit();
+        xSemaphoreGive(cyw43_worker_ran_sem);
+        __sev(); // it is possible regular code is waiting on a WFE on the other core
+    } while (true);
+}
+
+static void tcpip_init_done(void *param) {
+    xSemaphoreGive((SemaphoreHandle_t)param);
+}
+
+int cyw43_arch_init(void) {
+    cyw43_core_num = get_core_num();
+#if configUSE_CORE_AFFINITY && configNUM_CORES > 1
+    TaskHandle_t task_handle = xTaskGetCurrentTaskHandle();
+    UBaseType_t affinity = vTaskCoreAffinityGet(task_handle);
+    // we must bind the main task to one core during init
+    vTaskCoreAffinitySet(task_handle, 1 << portGET_CORE_ID());
+#endif
+#if !LWIP_TCPIP_CORE_LOCKING_INPUT
+    cyw43_mutex = xSemaphoreCreateRecursiveMutex();
+#endif
+    cyw43_init(&cyw43_state);
+    cyw43_worker_ran_sem = xSemaphoreCreateBinary();
+
+#if CYW43_LWIP
+    SemaphoreHandle_t init_sem = xSemaphoreCreateBinary();
+    tcpip_init(tcpip_init_done, init_sem);
+    xSemaphoreTake(init_sem, portMAX_DELAY);
+#endif
+
+    timer_handle = xTimerCreate(    "cyw43_sleep_timer",       // Just a text name, not used by the kernel.
+                                    pdMS_TO_TICKS(CYW43_SLEEP_CHECK_MS),
+                                    pdTRUE,        // The timers will auto-reload themselves when they expire.
+                                    NULL,
+                                    periodic_worker);
+
+    if (!timer_handle) {
+        return PICO_ERROR_GENERIC;
+    }
+
+    gpio_add_raw_irq_handler_with_order_priority(IO_IRQ_BANK0, gpio_irq_handler, CYW43_GPIO_IRQ_HANDLER_PRIORITY);
+    gpio_set_irq_enabled(CYW43_PIN_WL_HOST_WAKE, GPIO_IRQ_LEVEL_HIGH, true);
+    irq_set_enabled(IO_IRQ_BANK0, true);
+
+    cyw43_task_should_exit = false;
+    xTaskCreate(cyw43_task, "CYW43 Worker", configMINIMAL_STACK_SIZE, NULL, CYW43_TASK_PRIORITY, &cyw43_task_handle);
+#if configUSE_CORE_AFFINITY && configNUM_CORES > 1
+    // the cyw43 task mus tbe on the same core so it can restore IRQs
+    vTaskCoreAffinitySet(cyw43_task_handle, 1 << portGET_CORE_ID());
+#endif
+
+#if configUSE_CORE_AFFINITY && configNUM_CORES > 1
+    vTaskCoreAffinitySet(task_handle, affinity);
+#endif
+
+    return PICO_OK;
+}
+
+void cyw43_arch_deinit(void) {
+    assert(cyw43_core_num == get_core_num());
+    if (timer_handle) {
+        xTimerDelete(timer_handle, 0);
+        timer_handle = 0;
+    }
+    if (cyw43_task_handle) {
+        cyw43_task_should_exit = true;
+        signal_cyw43_task();
+    }
+    gpio_set_irq_enabled(CYW43_PIN_WL_HOST_WAKE, GPIO_IRQ_LEVEL_HIGH, false);
+    gpio_remove_raw_irq_handler(IO_IRQ_BANK0, gpio_irq_handler);
+}
+
+void cyw43_post_poll_hook(void) {
+    assert(cyw43_core_num == get_core_num());
+    gpio_set_irq_enabled(CYW43_PIN_WL_HOST_WAKE, GPIO_IRQ_LEVEL_HIGH, true);
+}
+
+// This is called in the gpio and low_prio_irq interrupts and on either core
+static void signal_cyw43_task(void) {
+    if (cyw43_task_handle) {
+        if (portCHECK_IF_IN_ISR()) {
+            vTaskNotifyGiveFromISR(cyw43_task_handle, NULL);
+        } else {
+            xTaskNotifyGive(cyw43_task_handle);
+        }
+    }
+}
+
+void cyw43_schedule_internal_poll_dispatch(void (*func)(void)) {
+    assert(func == cyw43_poll);
+    signal_cyw43_task();
+}
+
+static int nesting;
+// Prevent background processing in pensv and access by the other core
+// These methods are called in pensv context and on either core
+// They can be called recursively
+void cyw43_thread_enter(void) {
+    // Lock the other core and stop low_prio_irq running
+    assert(!portCHECK_IF_IN_ISR());
+#if LWIP_TCPIP_CORE_LOCKING_INPUT
+    // we must share their mutex otherwise we can get deadlocks with two different recursive mutexes
+    LOCK_TCPIP_CORE();
+#else
+    xSemaphoreTakeRecursive(cyw43_mutex, portMAX_DELAY);
+#endif
+    nesting++;
+}
+
+#ifndef NDEBUG
+void cyw43_thread_lock_check(void) {
+    // Lock the other core and stop low_prio_irq running
+#if LWIP_TCPIP_CORE_LOCKING_INPUT
+    assert(xSemaphoreGetMutexHolder(lock_tcpip_core.mut) == xTaskGetCurrentTaskHandle());
+#else
+    assert(xSemaphoreGetMutexHolder(cyw43_mutex) == xTaskGetCurrentTaskHandle());
+#endif
+}
+#endif
+
+// Re-enable background processing
+void cyw43_thread_exit(void) {
+    // Run low_prio_irq if needed
+    --nesting;
+#if LWIP_TCPIP_CORE_LOCKING_INPUT
+    // we must share their mutex otherwise we can get deadlocks with two different recursive mutexes
+    UNLOCK_TCPIP_CORE();
+#else
+    xSemaphoreGiveRecursive(cyw43_mutex);
+#endif
+
+    if (!nesting && cyw43_task_handle != xTaskGetCurrentTaskHandle())
+        signal_cyw43_task();
+}
+
+void cyw43_delay_ms(uint32_t ms) {
+    assert(!portCHECK_IF_IN_ISR());
+    vTaskDelay(pdMS_TO_TICKS(ms));
+}
+
+void cyw43_delay_us(uint32_t us) {
+    if (us >= 1000) {
+        cyw43_delay_ms(us / 1000);
+    } else {
+        vTaskDelay(1);
+    }
+}
+
+void cyw43_arch_poll() {
+}
+
+#endif
\ No newline at end of file
diff --git a/src/rp2_common/pico_cyw43_arch/cyw43_arch_poll.c b/src/rp2_common/pico_cyw43_arch/cyw43_arch_poll.c
new file mode 100644
index 000000000..e71f86ac5
--- /dev/null
+++ b/src/rp2_common/pico_cyw43_arch/cyw43_arch_poll.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+#include "hardware/gpio.h"
+#include "hardware/irq.h"
+#include "pico/sem.h"
+#include "pico/cyw43_arch.h"
+#include "cyw43_stats.h"
+
+#if PICO_CYW43_ARCH_POLL
+#include <lwip/init.h>
+#include "lwip/timeouts.h"
+
+#if CYW43_LWIP && !NO_SYS
+#error PICO_CYW43_ARCH_POLL requires lwIP NO_SYS=1
+#endif
+
+#define CYW43_GPIO_IRQ_HANDLER_PRIORITY 0x40
+
+#ifndef NDEBUG
+uint8_t cyw43_core_num;
+#endif
+
+bool cyw43_poll_required;
+
+// GPIO interrupt handler to tell us there's cyw43 has work to do
+static void gpio_irq_handler(void)
+{
+    uint32_t events = gpio_get_irq_event_mask(CYW43_PIN_WL_HOST_WAKE);
+    if (events & GPIO_IRQ_LEVEL_HIGH) {
+        // As we use a high level interrupt, it will go off forever until it's serviced
+        // So disable the interrupt until this is done. It's re-enabled again by CYW43_POST_POLL_HOOK
+        // which is called at the end of cyw43_poll_func
+        gpio_set_irq_enabled(CYW43_PIN_WL_HOST_WAKE, GPIO_IRQ_LEVEL_HIGH, false);
+        // also clear the force bit which we use to programmatically cause this handler to fire (on the right core)
+        io_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ?
+                                          &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl;
+        hw_clear_bits(&irq_ctrl_base->intf[CYW43_PIN_WL_HOST_WAKE/8], GPIO_IRQ_LEVEL_HIGH << (4 * (CYW43_PIN_WL_HOST_WAKE & 7)));
+        cyw43_schedule_internal_poll_dispatch(cyw43_poll);
+        CYW43_STAT_INC(IRQ_COUNT);
+    }
+}
+
+void cyw43_post_poll_hook(void) {
+    gpio_set_irq_enabled(CYW43_PIN_WL_HOST_WAKE, GPIO_IRQ_LEVEL_HIGH, true);
+}
+
+int cyw43_arch_init(void) {
+#ifndef NDEBUG
+    cyw43_core_num = (uint8_t)get_core_num();
+#endif
+    cyw43_init(&cyw43_state);
+    static bool done_lwip_init;
+    if (!done_lwip_init) {
+        lwip_init();
+        done_lwip_init = true;
+    }
+    gpio_add_raw_irq_handler_with_order_priority(IO_IRQ_BANK0, gpio_irq_handler, CYW43_GPIO_IRQ_HANDLER_PRIORITY);
+    gpio_set_irq_enabled(CYW43_PIN_WL_HOST_WAKE, GPIO_IRQ_LEVEL_HIGH, true);
+    irq_set_enabled(IO_IRQ_BANK0, true);
+    return 0;
+}
+
+void cyw43_arch_deinit(void) {
+    gpio_set_irq_enabled(CYW43_PIN_WL_HOST_WAKE, GPIO_IRQ_LEVEL_HIGH, false);
+    gpio_remove_raw_irq_handler(IO_IRQ_BANK0, gpio_irq_handler);
+    cyw43_deinit(&cyw43_state);
+}
+
+
+void cyw43_schedule_internal_poll_dispatch(__unused void (*func)(void)) {
+    cyw43_poll_required = true;
+}
+
+void cyw43_arch_poll(void)
+{
+    CYW43_STAT_INC(LWIP_RUN_COUNT);
+    sys_check_timeouts();
+    if (cyw43_poll) {
+        if (cyw43_sleep > 0) {
+            // todo check this; but we don't want to advance too quickly
+            static absolute_time_t last_poll_time;
+            absolute_time_t current = get_absolute_time();
+            if (absolute_time_diff_us(last_poll_time, current) > 1000) {
+                if (--cyw43_sleep == 0) {
+                    cyw43_poll_required = 1;
+                }
+                last_poll_time = current;
+            }
+        }
+        // todo graham i removed this because otherwise polling can do nothing during connect.
+        //  in the polling only case, the caller is responsible for throttling how often they call anyway.
+        //  The alternative would be to have the call to this function from the init set the poll_required flag first
+//        if (cyw43_poll_required) {
+            cyw43_poll();
+//            cyw43_poll_required = false;
+//        }
+    }
+}
+
+#ifndef NDEBUG
+void cyw43_thread_check() {
+    if (__get_current_exception() || get_core_num() != cyw43_core_num) {
+        panic("cyw43_thread_lock_check failed");
+    }
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/src/rp2_common/pico_cyw43_arch/cyw43_arch_threadsafe_background.c b/src/rp2_common/pico_cyw43_arch/cyw43_arch_threadsafe_background.c
new file mode 100644
index 000000000..a3dde74b7
--- /dev/null
+++ b/src/rp2_common/pico_cyw43_arch/cyw43_arch_threadsafe_background.c
@@ -0,0 +1,319 @@
+/*
+ * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+
+#include "pico/cyw43_arch.h"
+#include "pico/mutex.h"
+#include "pico/sem.h"
+
+#include "hardware/gpio.h"
+#include "hardware/irq.h"
+
+#include "cyw43_stats.h"
+
+#if CYW43_LWIP
+#include <lwip/init.h>
+#include "lwip/timeouts.h"
+#endif
+
+// note same code
+#if PICO_CYW43_ARCH_THREADSAFE_BACKGROUND
+
+#if PICO_CYW43_ARCH_THREADSAFE_BACKGROUND && CYW43_LWIP && !NO_SYS
+#error PICO_CYW43_ARCH_THREADSAFE_BACKGROUND requires lwIP NO_SYS=1
+#endif
+#if PICO_CYW43_ARCH_THREADSAFE_BACKGROUND && CYW43_LWIP && MEM_LIBC_MALLOC
+#error MEM_LIBC_MALLOC is incompatible with PICO_CYW43_ARCH_THREADSAFE_BACKGROUND
+#endif
+// todo right now we are now always doing a cyw43_dispatch along with a lwip one when hopping cores in low_prio_irq_schedule_dispatch
+
+#ifndef CYW43_SLEEP_CHECK_MS
+#define CYW43_SLEEP_CHECK_MS 50 // How often to run lwip callback
+#endif
+static alarm_id_t periodic_alarm = -1;
+
+static inline uint recursive_mutex_enter_count(recursive_mutex_t *mutex) {
+    return mutex->enter_count;
+}
+
+static inline lock_owner_id_t recursive_mutex_owner(recursive_mutex_t *mutex) {
+    return mutex->owner;
+}
+
+#define CYW43_GPIO_IRQ_HANDLER_PRIORITY 0x40
+
+enum {
+    CYW43_DISPATCH_SLOT_CYW43 = 0,
+    CYW43_DISPATCH_SLOT_ADAPTER,
+    CYW43_DISPATCH_SLOT_ENUM_COUNT
+};
+#ifndef CYW43_DISPATCH_SLOT_COUNT
+#define CYW43_DISPATCH_SLOT_COUNT CYW43_DISPATCH_SLOT_ENUM_COUNT
+#endif
+
+typedef void (*low_prio_irq_dispatch_t)(void);
+static void low_prio_irq_schedule_dispatch(size_t slot, low_prio_irq_dispatch_t f);
+
+static uint8_t cyw43_core_num;
+#ifndef NDEBUG
+static bool in_low_priority_irq;
+#endif
+static uint8_t low_priority_irq_num;
+static bool low_priority_irq_missed;
+static low_prio_irq_dispatch_t low_priority_irq_dispatch_slots[CYW43_DISPATCH_SLOT_COUNT];
+static recursive_mutex_t cyw43_mutex;
+semaphore_t cyw43_irq_sem;
+
+// Called in low priority pendsv interrupt only to do lwip processing and check cyw43 sleep
+static void periodic_worker(void)
+{
+#if CYW43_USE_STATS
+    static uint32_t counter;
+    if (counter++ % (30000 / LWIP_SYS_CHECK_MS) == 0) {
+        cyw43_dump_stats();
+    }
+#endif
+
+    CYW43_STAT_INC(LWIP_RUN_COUNT);
+#if CYW43_LWIP
+    sys_check_timeouts();
+#endif
+    if (cyw43_poll) {
+        if (cyw43_sleep > 0) {
+            if (--cyw43_sleep == 0) {
+                low_prio_irq_schedule_dispatch(CYW43_DISPATCH_SLOT_CYW43, cyw43_poll);
+            }
+        }
+    }
+}
+
+// Regular callback to get lwip to check for timeouts
+static int64_t periodic_alarm_handler(__unused alarm_id_t id, __unused void *user_data)
+{
+    // Do lwip processing in low priority pendsv interrupt
+    low_prio_irq_schedule_dispatch(CYW43_DISPATCH_SLOT_ADAPTER, periodic_worker);
+    return CYW43_SLEEP_CHECK_MS * 1000;
+}
+
+void cyw43_await_background_or_timeout_us(uint32_t timeout_us) {
+    // if we are called from within an IRQ, then don't wait (we are only ever called in a polling loop)
+    if (!__get_current_exception()) {
+        sem_acquire_timeout_us(&cyw43_irq_sem, timeout_us);
+    }
+}
+
+// GPIO interrupt handler to tell us there's cyw43 has work to do
+static void gpio_irq_handler(void)
+{
+    uint32_t events = gpio_get_irq_event_mask(CYW43_PIN_WL_HOST_WAKE);
+    if (events & GPIO_IRQ_LEVEL_HIGH) {
+        // As we use a high level interrupt, it will go off forever until it's serviced
+        // So disable the interrupt until this is done. It's re-enabled again by CYW43_POST_POLL_HOOK
+        // which is called at the end of cyw43_poll_func
+        gpio_set_irq_enabled(CYW43_PIN_WL_HOST_WAKE, GPIO_IRQ_LEVEL_HIGH, false);
+        // also clear the force bit which we use to progratically cause this handler to fire (on the right core)
+        io_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ?
+                                          &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl;
+        hw_clear_bits(&irq_ctrl_base->intf[CYW43_PIN_WL_HOST_WAKE/8], GPIO_IRQ_LEVEL_HIGH << (4 * (CYW43_PIN_WL_HOST_WAKE & 7)));
+        low_prio_irq_schedule_dispatch(CYW43_DISPATCH_SLOT_CYW43, cyw43_poll);
+        CYW43_STAT_INC(IRQ_COUNT);
+    }
+}
+
+// Low priority interrupt handler to perform background processing
+static void low_priority_irq_handler(void) {
+    assert(cyw43_core_num == get_core_num());
+    if (recursive_mutex_try_enter(&cyw43_mutex, NULL)) {
+        if (recursive_mutex_enter_count(&cyw43_mutex) != 1) {
+            low_priority_irq_missed = true;
+            CYW43_STAT_INC(PENDSV_DISABLED_COUNT);
+        } else {
+            CYW43_STAT_INC(PENDSV_RUN_COUNT);
+#ifndef NDEBUG
+            in_low_priority_irq = true;
+#endif
+            for (size_t i = 0; i < count_of(low_priority_irq_dispatch_slots); i++) {
+                if (low_priority_irq_dispatch_slots[i] != NULL) {
+                    low_prio_irq_dispatch_t f = low_priority_irq_dispatch_slots[i];
+                    low_priority_irq_dispatch_slots[i] = NULL;
+                    f();
+                }
+            }
+#ifndef NDEBUG
+            in_low_priority_irq = false;
+#endif
+        }
+        recursive_mutex_exit(&cyw43_mutex);
+    } else {
+        CYW43_STAT_INC(PENDSV_DISABLED_COUNT);
+        low_priority_irq_missed = true;
+    }
+    sem_release(&cyw43_irq_sem);
+}
+
+static bool low_prio_irq_init(uint8_t priority) {
+    assert(get_core_num() == cyw43_core_num);
+    int irq = user_irq_claim_unused(false);
+    if (irq < 0) return false;
+    low_priority_irq_num = (uint8_t) irq;
+    irq_set_exclusive_handler(low_priority_irq_num, low_priority_irq_handler);
+    irq_set_enabled(low_priority_irq_num, true);
+    irq_set_priority(low_priority_irq_num, priority);
+    return true;
+}
+
+static void low_prio_irq_deinit(void) {
+    if (low_priority_irq_num > 0) {
+        irq_set_enabled(low_priority_irq_num, false);
+        irq_remove_handler(low_priority_irq_num, low_priority_irq_handler);
+        user_irq_unclaim(low_priority_irq_num);
+        low_priority_irq_num = 0;
+    }
+}
+
+int cyw43_arch_init(void) {
+    cyw43_core_num = get_core_num();
+    recursive_mutex_init(&cyw43_mutex);
+    cyw43_init(&cyw43_state);
+    sem_init(&cyw43_irq_sem, 0, 1);
+
+    // Start regular lwip callback to handle timeouts
+    periodic_alarm = add_alarm_in_us(CYW43_SLEEP_CHECK_MS * 1000, periodic_alarm_handler, NULL, true);
+    if (periodic_alarm < 0) {
+        return PICO_ERROR_GENERIC;
+    }
+
+    gpio_add_raw_irq_handler_with_order_priority(IO_IRQ_BANK0, gpio_irq_handler, CYW43_GPIO_IRQ_HANDLER_PRIORITY);
+    gpio_set_irq_enabled(CYW43_PIN_WL_HOST_WAKE, GPIO_IRQ_LEVEL_HIGH, true);
+    irq_set_enabled(IO_IRQ_BANK0, true);
+
+#if CYW43_LWIP
+    lwip_init();
+#endif
+    // start low priority handler (no background work is done before this)
+    bool ok = low_prio_irq_init(PICO_LOWEST_IRQ_PRIORITY);
+    if (!ok) {
+        cyw43_arch_deinit();
+        return PICO_ERROR_GENERIC;
+    }
+    return PICO_OK;
+}
+
+void cyw43_arch_deinit(void) {
+    if (periodic_alarm >= 0) {
+        cancel_alarm(periodic_alarm);
+        periodic_alarm = -1;
+    }
+    gpio_set_irq_enabled(CYW43_PIN_WL_HOST_WAKE, GPIO_IRQ_LEVEL_HIGH, false);
+    gpio_remove_raw_irq_handler(IO_IRQ_BANK0, gpio_irq_handler);
+    low_prio_irq_deinit();
+}
+
+void cyw43_post_poll_hook(void) {
+    gpio_set_irq_enabled(CYW43_PIN_WL_HOST_WAKE, GPIO_IRQ_LEVEL_HIGH, true);
+}
+
+// This is called in the gpio and low_prio_irq interrupts and on either core
+static void low_prio_irq_schedule_dispatch(size_t slot, low_prio_irq_dispatch_t f) {
+    assert(slot < count_of(low_priority_irq_dispatch_slots));
+    low_priority_irq_dispatch_slots[slot] = f;
+    if (cyw43_core_num == get_core_num()) {
+        //on same core, can dispatch directly
+        irq_set_pending(low_priority_irq_num);
+    } else {
+        // on wrong core, so force via GPIO IRQ which itself calls this method for the CYW43 slot.
+        // since the CYW43 slot always uses the same function, this is fine with the addition of an
+        // extra (but harmless) CYW43 slot call when another SLOT is invoked.
+        // We could do better, but would have to track why the IRQ was called.
+        io_irq_ctrl_hw_t *irq_ctrl_base = cyw43_core_num ?
+                                          &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl;
+        hw_set_bits(&irq_ctrl_base->intf[CYW43_PIN_WL_HOST_WAKE/8], GPIO_IRQ_LEVEL_HIGH << (4 * (CYW43_PIN_WL_HOST_WAKE & 7)));
+    }
+}
+
+void cyw43_schedule_internal_poll_dispatch(void (*func)(void)) {
+    low_prio_irq_schedule_dispatch(CYW43_DISPATCH_SLOT_CYW43, func);
+}
+
+// Prevent background processing in pensv and access by the other core
+// These methods are called in pensv context and on either core
+// They can be called recursively
+void cyw43_thread_enter(void) {
+    // Lock the other core and stop low_prio_irq running
+    recursive_mutex_enter_blocking(&cyw43_mutex);
+}
+
+#ifndef NDEBUG
+void cyw43_thread_lock_check(void) {
+    // Lock the other core and stop low_prio_irq running
+    if (recursive_mutex_enter_count(&cyw43_mutex) < 1 || recursive_mutex_owner(&cyw43_mutex) != lock_get_caller_owner_id()) {
+        panic("cyw43_thread_lock_check failed");
+    }
+}
+#endif
+
+// Re-enable background processing
+void cyw43_thread_exit(void) {
+    // Run low_prio_irq if needed
+    if (1 == recursive_mutex_enter_count(&cyw43_mutex)) {
+        // note the outer release of the mutex is not via cyw43_exit in the low_priority_irq case (it is a direct mutex exit)
+        assert(!in_low_priority_irq);
+//        if (low_priority_irq_missed) {
+//            low_priority_irq_missed = false;
+            if (low_priority_irq_dispatch_slots[CYW43_DISPATCH_SLOT_CYW43]) {
+                low_prio_irq_schedule_dispatch(CYW43_DISPATCH_SLOT_CYW43, cyw43_poll);
+            }
+//        }
+    }
+    recursive_mutex_exit(&cyw43_mutex);
+}
+
+
+static void cyw43_delay_until(absolute_time_t until) {
+    // sleep can be called in IRQs, so there's not much we can do there
+    if (__get_current_exception()) {
+        busy_wait_until(until);
+    } else {
+        sleep_until(until);
+    }
+}
+
+void cyw43_delay_ms(uint32_t ms) {
+    cyw43_delay_until(make_timeout_time_ms(ms));
+}
+
+void cyw43_delay_us(uint32_t us) {
+    cyw43_delay_until(make_timeout_time_us(us));
+}
+
+void cyw43_arch_poll() {
+    // should not be necessary
+//    if (cyw43_poll) {
+//        low_prio_irq_schedule_dispatch(CYW43_DISPATCH_SLOT_CYW43, cyw43_poll);
+//    }
+}
+
+#if !CYW43_LWIP
+static void no_lwip_fail() {
+    panic("You cannot use IP with pico_cyw43_arch_none");
+}
+void cyw43_cb_tcpip_init(cyw43_t *self, int itf) {
+}
+void cyw43_cb_tcpip_deinit(cyw43_t *self, int itf) {
+}
+void cyw43_cb_tcpip_set_link_up(cyw43_t *self, int itf) {
+    no_lwip_fail();
+}
+void cyw43_cb_tcpip_set_link_down(cyw43_t *self, int itf) {
+    no_lwip_fail();
+}
+void cyw43_cb_process_ethernet(void *cb_data, int itf, size_t len, const uint8_t *buf) {
+    no_lwip_fail();
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/src/rp2_common/pico_cyw43_arch/include/cyw43_configport.h b/src/rp2_common/pico_cyw43_arch/include/cyw43_configport.h
new file mode 100644
index 000000000..7827c8115
--- /dev/null
+++ b/src/rp2_common/pico_cyw43_arch/include/cyw43_configport.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// This header is included by cyw43_driver to setup its environment
+
+#ifndef _CYW43_CONFIGPORT_H
+#define _CYW43_CONFIGPORT_H
+
+#include "pico.h"
+
+#ifdef PICO_CYW43_ARCH_HEADER
+#include __XSTRING(PICO_CYW43_ARCH_HEADER)
+#else
+#if PICO_CYW43_ARCH_POLL
+#include "pico/cyw43_arch/arch_poll.h"
+#elif PICO_CYW43_ARCH_THREADSAFE_BACKGROUND
+#include "pico/cyw43_arch/arch_threadsafe_background.h"
+#elif PICO_CYW43_ARCH_FREERTOS
+#include "pico/cyw43_arch/arch_freertos.h"
+#else
+#error must specify support pico_cyw43_arch architecture type or set PICO_CYW43_ARCH_HEADER
+#endif
+#endif
+
+#ifndef CYW43_HOST_NAME
+#define CYW43_HOST_NAME "PicoW"
+#endif
+
+#ifndef CYW43_GPIO
+#define CYW43_GPIO 1
+#endif
+
+#ifndef CYW43_LOGIC_DEBUG
+#define CYW43_LOGIC_DEBUG 0
+#endif
+
+#ifndef CYW43_USE_OTP_MAC
+#define CYW43_USE_OTP_MAC 1
+#endif
+
+#ifndef CYW43_NO_NETUTILS
+#define CYW43_NO_NETUTILS 1
+#endif
+
+#ifndef CYW43_IOCTL_TIMEOUT_US
+#define CYW43_IOCTL_TIMEOUT_US 1000000
+#endif
+
+#ifndef CYW43_USE_STATS
+#define CYW43_USE_STATS 0
+#endif
+
+// todo should this be user settable?
+#ifndef CYW43_HAL_MAC_WLAN0
+#define CYW43_HAL_MAC_WLAN0 0
+#endif
+
+#ifndef STATIC
+#define STATIC static
+#endif
+
+#ifndef CYW43_USE_SPI
+#define CYW43_USE_SPI 1
+#endif
+
+#ifndef CYW43_SPI_PIO
+#define CYW43_SPI_PIO 1
+#endif
+
+#endif
\ No newline at end of file
diff --git a/src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch.h b/src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch.h
new file mode 100644
index 000000000..8d6a628fc
--- /dev/null
+++ b/src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch.h
@@ -0,0 +1,328 @@
+/*
+ * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_CYW43_ARCH_H
+#define _PICO_CYW43_ARCH_H
+
+#include "pico.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "cyw43.h"
+#include "cyw43_country.h"
+
+/**
+ * \defgroup cyw43_driver cyw43_driver
+ * \ingroup pico_cyw43_arch
+ * \brief Driver used for Pico W wireless
+*/
+
+/**
+ * \defgroup cyw43_ll cyw43_ll
+ * \ingroup cyw43_driver
+ * \brief Low Level CYW43 driver interface
+*/
+
+/** \file pico/cyw43_arch.h
+ *  \defgroup pico_cyw43_arch pico_cyw43_arch
+ *
+ * Architecture for integrating the CYW43 driver (for the wireless on Pico W) and lwIP (for TCP/IP stack) into the SDK. It is also necessary for accessing the on-board LED on Pico W
+ *
+ * Both the low level \c cyw43_driver and the lwIP stack require periodic servicing, and have limitations
+ * on whether they can be called from multiple cores/threads.
+ *
+ * \c pico_cyw43_arch attempts to abstract these complications into several behavioral groups:
+ *
+ * * \em 'poll' - This not multi-core/IRQ safe, and requires the user to call \ref cyw43_arch_poll periodically from their main loop
+ * * \em 'thread_safe_background' - This is multi-core/thread/task safe, and maintenance of the driver and TCP/IP stack is handled automatically in the background
+ *
+ * As of right now, lwIP is the only supported TCP/IP stack, however the use of \c pico_cyw43_arch is intended to be independent of
+ * the particular TCP/IP stack used (and possibly Bluetooth stack used) in the future. For this reason, the integration of lwIP
+ * is handled in the base (\c pico_cyw43_arch) library based on the #define \ref CYW43_LWIP used by the \c cyw43_driver.
+ *
+ * Whilst you can use the \c pico_cyw43_arch library directly and  specify \ref CYW$#_LWIP (and other defines) yourself, several
+ * other libraries are made available to the build which aggregate the defines and other dependencies for you:
+ *
+ * * \b pico_cyw43_arch_lwip_poll - For using the RAW lwIP API (in `NO_SYS=1` mode) without any background processing or multi-core/thread safety.
+ *
+ *    The user must call \ref pico_cyw43_poll periodically from their main loop.
+ *
+ *    This wrapper library:
+ *    - Sets \c CYW43_LWIP=1 to enable lwIP support in \c pico_cyw43_arch and \c cyw43_driver.
+ *    - Sets \c PICO_CYW43_ARCH_POLL=1 to select the polling behavior.
+ *    - Adds the \c pico_lwip as a dependency to pull in lwIP.
+ *
+ * * \b pico_cyw43_arch_lwip_threadsafe_background - For using the RAW lwIP API (in `NO_SYS=1` mode) with multi-core/thread safety, and automatic servicing of the \c cyw43_driver and
+ * lwIP in background.
+ *
+ *    Calls into the \c cyw43_driver high level API (cyw43.h) may be made from either core or from lwIP callbacks, however calls into lwIP (which
+ * is not thread-safe) other than those made from lwIP callbacks, must be bracketed with \ref cyw43_arch_lwip_begin and \ref cyw43_arch_lwip_end. It is fine to bracket
+ * calls made from within lwIP callbacks too; you just don't have to.
+ *
+ *    \note lwIP callbacks happen in a (low priority) IRQ context (similar to an alarm callback), so care should be taken when interacting
+ *    with other code.
+ *
+ *    This wrapper library:
+ *    - Sets \c CYW43_LWIP=1 to enable lwIP support in \c pico_cyw43_arch and \c cyw43_driver
+ *    - Sets \c PICO_CYW43_ARCH_THREADSAFE_BACKGROUND=1 to select the thread-safe/non-polling behavior.
+ *    - Adds the pico_lwip as a dependency to pull in lwIP.
+ *
+ *
+ *    This library \em can also be used under the RP2040 port of FreeRTOS with lwIP in `NO_SYS=1` mode (allowing you to call \c cyw43_driver APIs
+ * from any task, and to call lwIP from lwIP callbacks, or from any task if you bracket the calls with \ref cyw43_arch_lwip_begin and \ref cyw43_arch_lwip_end. Again, you should be
+ * careful about what you do in lwIP callbacks, as you cannot call most FreeRTOS APIs from within an IRQ context. Unless you have good reason, you should probably
+ * use the full FreeRTOS integration (with `NO_SYS=0`) provided by \c pico_cyw43_arch_lwip_sys_freertos.
+ *
+ * * \b pico_cyw43_arch_lwip_sys_freertos - For using the full lwIP API including blocking sockets in OS (`NO_SYS=0`) mode, along with with multi-core/task/thread safety, and automatic servicing of the \c cyw43_driver and
+ * the lwIP stack.
+ *
+ *    This wrapper library:
+ *    - Sets \c CYW43_LWIP=1 to enable lwIP support in \c pico_cyw43_arch and \c cyw43_driver.
+ *    - Sets \c PICO_CYW43_ARCH_FREERTOS=1 to select the NO_SYS=0 lwip/FreeRTOS integration
+ *    - Sets \c LWIP_PROVIDE_ERRNO=1 to provide error numbers needed for compilation without an OS
+ *    - Adds the \c pico_lwip as a dependency to pull in lwIP.
+ *    - Adds the lwIP/FreeRTOS code from lwip-contrib (in the contrib directory of lwIP)
+ *
+ *    Calls into the \c cyw43_driver high level API (cyw43.h) may be made from any task or from lwIP callbacks, but not from IRQs. Calls into the lwIP RAW API (which is not thread safe)
+ *    must be bracketed with \ref cyw43_arch_lwip_begin and \ref cyw43_arch_lwip_end. It is fine to bracket calls made from within lwIP callbacks too; you just don't have to.
+ *
+ *    \note this wrapper library requires you to link FreeRTOS functionality with your application yourself.
+ *
+ * * \b pico_cyw43_arch_none - If you do not need the TCP/IP stack but wish to use the on-board LED.
+ *
+ *    This wrapper library:
+ *    - Sets \c CYW43_LWIP=0 to disable lwIP support in \c pico_cyw43_arch and \c cyw43_driver
+ */
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_CYW43_ARCH, Enable/disable assertions in the pico_cyw43_arch module, type=bool, default=0, group=pico_cyw43_arch
+#ifndef PARAM_ASSERTIONS_ENABLED_CYW43_ARCH
+#define PARAM_ASSERTIONS_ENABLED_CYW43_ARCH 0
+#endif
+
+// PICO_CONFIG: CYW43_ARCH_DEBUG_ENABLED, Enable/disable some debugging output in the pico_cyw43_arch module, type=bool, default=1 in debug builds, group=pico_cyw43_arch
+#ifndef CYW43_ARCH_DEBUG_ENABLED
+#ifndef NDEBUG
+#define CYW43_ARCH_DEBUG_ENABLED 1
+#else
+#define CYW43_ARCH_DEBUG_ENABLED 0
+#endif
+#endif
+
+// PICO_CONFIG: PICO_CYW43_ARCH_DEFAULT_COUNTRY_CODE, Default country code for the cyw43 wireless driver, default=CYW43_COUNTRY_WORLDWIDE, group=pico_cyw43_arch
+#ifndef PICO_CYW43_ARCH_DEFAULT_COUNTRY_CODE
+#define PICO_CYW43_ARCH_DEFAULT_COUNTRY_CODE CYW43_COUNTRY_WORLDWIDE
+#endif
+
+/*!
+ * \brief Initialize the CYW43 architecture
+ * \ingroup pico_cyw43_arch
+ *
+ * This method initializes the `cyw43_driver` code and initializes the lwIP stack (if it
+ * was enabled at build time). This method must be called prior to using any other \c pico_cyw43_arch,
+ * \cyw43_driver or lwIP functions.
+ *
+ * \note this method initializes wireless with a country code of \c PICO_CYW43_ARCH_DEFAULT_COUNTRY_CODE
+ * which defaults to \c CYW43_COUNTRY_WORLDWIDE. Worldwide settings may not give the best performance; consider
+ * setting PICO_CYW43_ARCH_DEFAULT_COUNTRY_CODE to a different value or calling \ref cyw43_arch_init_with_country
+ * \return 0 if the initialization is successful, an error code otherwise \see pico_error_codes
+ */
+int cyw43_arch_init(void);
+
+/*!
+ * \brief Initialize the CYW43 architecture for use in a specific country
+ * \ingroup pico_cyw43_arch
+ *
+ * This method initializes the `cyw43_driver` code and initializes the lwIP stack (if it
+ * was enabled at build time). This method must be called prior to using any other \c pico_cyw43_arch,
+ * \cyw43_driver or lwIP functions.
+ *
+ * \param country the country code to use (see \ref CYW43_COUNTRY_)
+ * \return 0 if the initialization is successful, an error code otherwise \see pico_error_codes
+ */
+int cyw43_arch_init_with_country(uint32_t country);
+
+/*!
+ * \brief Enables Wi-Fi STA (Station) mode.
+ * \ingroup pico_cyw43_arch
+ *
+ * This enables the Wi-Fi in \emStation mode such that connections can be made to other Wi-Fi Access Points
+ */
+void cyw43_arch_enable_sta_mode(void);
+
+/*!
+ * \brief Enables Wi-Fi AP (Access point) mode.
+ * \ingroup pico_cyw43_arch
+ *
+ * This enables the Wi-Fi in \em Access \em Point mode such that connections can be made to the device by  other Wi-Fi clients
+ * \param ssid the name for the access point
+ * \param password the password to use or NULL for no password.
+ * \param auth the authorization type to use when the password is enabled. Values are \ref CYW43_AUTH_WPA_TKIP_PSK,
+ *             \ref CYW43_AUTH_WPA2_AES_PSK, or \ref CYW43_AUTH_WPA2_MIXED_PSK (see \ref CYW43_AUTH_)
+ */
+void cyw43_arch_enable_ap_mode(const char *ssid, const char *password, uint32_t auth);
+
+/*!
+ * \brief De-initialize the CYW43 architecture
+ * \ingroup pico_cyw43_arch
+ *
+ * This method de-initializes the `cyw43_driver` code and de-initializes the lwIP stack (if it
+ * was enabled at build time). Note this method should always be called from the same core (or RTOS
+ * task, depending on the environment) as \ref cyw43_arch_init.
+ */
+void cyw43_arch_deinit(void);
+
+/*!
+ * \brief Attempt to connect to a wireless access point, blocking until the network is joined or a failure is detected.
+ * \ingroup pico_cyw43_arch
+ *
+ * \param ssid the network name to connect to
+ * \param password the network password or NULL if there is no password required
+ * \param auth the authorization type to use when the password is enabled. Values are \ref CYW43_AUTH_WPA_TKIP_PSK,
+ *             \ref CYW43_AUTH_WPA2_AES_PSK, or \ref CYW43_AUTH_WPA2_MIXED_PSK (see \ref CYW43_AUTH_)
+ *
+ * \return 0 if the initialization is successful, an error code otherwise \see pico_error_codes
+ */
+int cyw43_arch_wifi_connect_blocking(const char *ssid, const char *pw, uint32_t auth);
+
+/*!
+ * \brief Attempt to connect to a wireless access point, blocking until the network is joined, a failure is detected or a timeout occurs
+ * \ingroup pico_cyw43_arch
+ *
+ * \param ssid the network name to connect to
+ * \param password the network password or NULL if there is no password required
+ * \param auth the authorization type to use when the password is enabled. Values are \ref CYW43_AUTH_WPA_TKIP_PSK,
+ *             \ref CYW43_AUTH_WPA2_AES_PSK, or \ref CYW43_AUTH_WPA2_MIXED_PSK (see \ref CYW43_AUTH_)
+ *
+ * \return 0 if the initialization is successful, an error code otherwise \see pico_error_codes
+ */
+int cyw43_arch_wifi_connect_timeout_ms(const char *ssid, const char *pw, uint32_t auth, uint32_t timeout);
+
+/*!
+ * \brief Start attempting to connect to a wireless access point
+ * \ingroup pico_cyw43_arch
+ *
+ * This method tells the CYW43 driver to start connecting to an access point. You should subsequently check the
+ * status by calling \ref cyw43_wifi_link_status.
+ *
+ * \param ssid the network name to connect to
+ * \param password the network password or NULL if there is no password required
+ * \param auth the authorization type to use when the password is enabled. Values are \ref CYW43_AUTH_WPA_TKIP_PSK,
+ *             \ref CYW43_AUTH_WPA2_AES_PSK, or \ref CYW43_AUTH_WPA2_MIXED_PSK (see \ref CYW43_AUTH_)
+ *
+ * \return 0 if the scan was started successfully, an error code otherwise \see pico_error_codes
+ */
+int cyw43_arch_wifi_connect_async(const char *ssid, const char *pw, uint32_t auth);
+
+/*!
+ * \brief Return the country code used to initialize cyw43_arch
+ * \ingroup pico_cyw43_arch
+ *
+ * \return the country code (see \ref CYW43_COUNTRY_)
+ */
+uint32_t cyw43_arch_get_country_code(void);
+
+/*!
+ * \brief Set a GPIO pin on the wireless chip to a given value
+ * \ingroup pico_cyw43_arch
+ * \note this method does not check for errors setting the GPIO. You can use the lower level \ref cyw43_gpio_set instead if you wish
+ * to check for errors.
+ *
+ * \param wl_gpio the GPIO number on the wireless chip
+ * \param value true to set the GPIO, false to clear it.
+ */
+void cyw43_arch_gpio_put(uint wl_gpio, bool value);
+
+/*!
+ * \brief Read the value of a GPIO pin on the wireless chip
+ * \ingroup pico_cyw43_arch
+ * \note this method does not check for errors setting the GPIO. You can use the lower level \ref cyw43_gpio_get instead if you wish
+ * to check for errors.
+ *
+ * \param wl_gpio the GPIO number on the wireless chip
+ * \return true if the GPIO is high, false otherwise
+ */
+bool cyw43_arch_gpio_get(uint wl_gpio);
+
+/*!
+ * \brief Perform any processing required by the \c cyw43_driver or the TCP/IP stack
+ * \ingroup pico_cyw43_arch
+ *
+ * This method must be called periodically from the main loop when using a
+ * \em polling style \c pico_cyw43_arch (e.g. \c pico_cyw43_arch_lwip_poll ). It
+ * may be called in other styles, but it is unnecessary to do so.
+ */
+void cyw43_arch_poll(void);
+
+/*!
+ * \fn cyw43_arch_lwip_begin
+ * \brief Acquire any locks required to call into lwIP
+ * \ingroup pico_cyw43_arch
+ *
+ * The lwIP API is not thread safe. You should surround calls into the lwIP API
+ * with calls to this method and \ref cyw43_arch_lwip_end. Note these calls are not
+ * necessary (but harmless) when you are calling back into the lwIP API from an lwIP callback.
+ * If you are using single-core polling only (pico_cyw43_arch_poll) then these calls are no-ops
+ * anyway it is good practice to call them anyway where they are necessary.
+ *
+ * \sa cyw43_arch_lwip_end
+ * \sa cyw43_arch_lwip_protect
+ */
+
+/*!
+ * \fn void cyw43_arch_lwip_end(void)
+ * \brief Release any locks required for calling into lwIP
+ * \ingroup pico_cyw43_arch
+ *
+ * The lwIP API is not thread safe. You should surround calls into the lwIP API
+ * with calls to \ref cyw43_arch_lwip_begin and this method. Note these calls are not
+ * necessary (but harmless) when you are calling back into the lwIP API from an lwIP callback.
+ * If you are using single-core polling only (pico_cyw43_arch_poll) then these calls are no-ops
+ * anyway it is good practice to call them anyway where they are necessary.
+ *
+ * \sa cyw43_arch_lwip_begin
+ * \sa cyw43_arch_lwip_protect
+ */
+
+/*!
+ * \fn int cyw43_arch_lwip_protect(int (*func)(void *param), void *param)
+ * \brief sad Release any locks required for calling into lwIP
+ * \ingroup pico_cyw43_arch
+ *
+ * The lwIP API is not thread safe. You can use this method to wrap a function
+ * with any locking required to call into the lwIP API. If you are using
+ * single-core polling only (pico_cyw43_arch_poll) then there are no
+ * locks to required, but it is still good practice to use this function.
+ *
+ * \param func the function ta call with any required locks held
+ * \param param parameter to pass to \c func
+ * \return the return value from \c func
+ * \sa cyw43_arch_lwip_begin
+ * \sa cyw43_arch_lwip_end
+ */
+
+/*!
+ * \fn void cyw43_arch_lwip_check(void)
+ * \brief Checks the caller has any locks required for calling into lwIP
+ * \ingroup pico_cyw43_arch
+ *
+ * The lwIP API is not thread safe. You should surround calls into the lwIP API
+ * with calls to \ref cyw43_arch_lwip_begin and this method. Note these calls are not
+ * necessary (but harmless) when you are calling back into the lwIP API from an lwIP callback.
+ *
+ * This method will assert in debug mode, if the above conditions are not met (i.e. it is not safe to
+ * call into the lwIP API)
+ *
+ * \sa cyw43_arch_lwip_begin
+ * \sa cyw43_arch_lwip_protect
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_common.h b/src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_common.h
new file mode 100644
index 000000000..3cd5aa975
--- /dev/null
+++ b/src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_common.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_CYW43_ARCH_ARCH_COMMON_H
+#define _PICO_CYW43_ARCH_ARCH_COMMON_H
+
+#include "pico.h"
+#include "pico/time.h"
+#include "hardware/gpio.h"
+#include "pico/error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Note, these are negated, because cyw43_driver negates them before returning!
+#define CYW43_EPERM            (-PICO_ERROR_NOT_PERMITTED) // Operation not permitted
+#define CYW43_EIO              (-PICO_ERROR_IO) // I/O error
+#define CYW43_EINVAL           (-PICO_ERROR_INVALID_ARG) // Invalid argument
+#define CYW43_ETIMEDOUT        (-PICO_ERROR_TIMEOUT) // Connection timed out
+
+#define CYW43_NUM_GPIOS        CYW43_WL_GPIO_COUNT
+
+#define cyw43_hal_pin_obj_t uint
+
+// get the number of elements in a fixed-size array
+#define CYW43_ARRAY_SIZE(a) count_of(a)
+
+static inline uint32_t cyw43_hal_ticks_us(void) {
+    return time_us_32();
+}
+
+static inline uint32_t cyw43_hal_ticks_ms(void) {
+    return to_ms_since_boot(get_absolute_time());
+}
+
+static inline int cyw43_hal_pin_read(cyw43_hal_pin_obj_t pin) {
+    return gpio_get(pin);
+}
+
+static inline void cyw43_hal_pin_low(cyw43_hal_pin_obj_t pin) {
+    gpio_clr_mask(1 << pin);
+}
+
+static inline void cyw43_hal_pin_high(cyw43_hal_pin_obj_t pin) {
+    gpio_set_mask(1 << pin);
+}
+
+#define CYW43_HAL_PIN_MODE_INPUT           (GPIO_IN)
+#define CYW43_HAL_PIN_MODE_OUTPUT          (GPIO_OUT)
+
+#define CYW43_HAL_PIN_PULL_NONE            (0)
+#define CYW43_HAL_PIN_PULL_UP              (1)
+#define CYW43_HAL_PIN_PULL_DOWN            (2)
+
+static inline void cyw43_hal_pin_config(cyw43_hal_pin_obj_t pin, uint32_t mode, uint32_t pull, __unused uint32_t alt) {
+    assert((mode == CYW43_HAL_PIN_MODE_INPUT || mode == CYW43_HAL_PIN_MODE_OUTPUT) && alt == 0);
+    gpio_set_dir(pin, mode);
+    gpio_set_pulls(pin, pull == CYW43_HAL_PIN_PULL_UP, pull == CYW43_HAL_PIN_PULL_DOWN);
+}
+
+void cyw43_hal_get_mac(int idx, uint8_t buf[6]);
+
+void cyw43_hal_generate_laa_mac(int idx, uint8_t buf[6]);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_freertos.h b/src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_freertos.h
new file mode 100644
index 000000000..342a85caf
--- /dev/null
+++ b/src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_freertos.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _EXAMPLE_CYW43_ARCH_ARCH_FREERTOS_SYS_H
+#define _EXAMPLE_CYW43_ARCH_ARCH_FREERTOS_SYS_H
+
+#include "pico/cyw43_arch/arch_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void cyw43_thread_enter(void);
+void cyw43_thread_exit(void);
+
+#define CYW43_THREAD_ENTER cyw43_thread_enter();
+#define CYW43_THREAD_EXIT cyw43_thread_exit();
+#ifndef NDEBUG
+void cyw43_thread_lock_check(void);
+#define cyw43_arch_lwip_check() cyw43_thread_lock_check()
+#define CYW43_THREAD_LOCK_CHECK cyw43_arch_lwip_check();
+#else
+#define cyw43_arch_lwip_check() ((void)0)
+#define CYW43_THREAD_LOCK_CHECK
+#endif
+
+void cyw43_await_background_or_timeout_us(uint32_t timeout_us);
+// todo not 100% sure about the timeouts here; MP uses __WFI which will always wakeup periodically
+#define CYW43_SDPCM_SEND_COMMON_WAIT cyw43_await_background_or_timeout_us(1000);
+#define CYW43_DO_IOCTL_WAIT cyw43_await_background_or_timeout_us(1000);
+
+void cyw43_delay_ms(uint32_t ms);
+void cyw43_delay_us(uint32_t us);
+
+void cyw43_schedule_internal_poll_dispatch(void (*func)(void));
+
+void cyw43_post_poll_hook(void);
+#define CYW43_POST_POLL_HOOK cyw43_post_poll_hook();
+
+static inline void cyw43_arch_lwip_begin(void) {
+    cyw43_thread_enter();
+}
+static inline void cyw43_arch_lwip_end(void) {
+    cyw43_thread_exit();
+}
+
+static inline int cyw43_arch_lwip_protect(int (*func)(void *param), void *param) {
+    cyw43_arch_lwip_begin();
+    int rc = func(param);
+    cyw43_arch_lwip_end();
+    return rc;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_poll.h b/src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_poll.h
new file mode 100644
index 000000000..bfaea7f0e
--- /dev/null
+++ b/src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_poll.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_CYW43_ARCH_ARCH_POLL_H
+#define _PICO_CYW43_ARCH_ARCH_POLL_H
+
+#include "pico/cyw43_arch/arch_common.h"
+
+#include <assert.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CYW43_THREAD_ENTER
+#define CYW43_THREAD_EXIT
+#ifndef NDEBUG
+
+void cyw43_thread_check(void);
+
+#define cyw43_arch_lwip_check() cyw43_thread_check()
+#define CYW43_THREAD_LOCK_CHECK cyw43_arch_lwip_check();
+#else
+#define cyw43_arch_lwip_check() ((void)0)
+#define CYW43_THREAD_LOCK_CHECK
+#endif
+
+#define CYW43_SDPCM_SEND_COMMON_WAIT cyw43_poll_required = true;
+#define CYW43_DO_IOCTL_WAIT cyw43_poll_required = true;
+
+#define cyw43_delay_ms sleep_ms
+#define cyw43_delay_us sleep_us
+
+void cyw43_schedule_internal_poll_dispatch(void (*func)(void));
+
+void cyw43_post_poll_hook(void);
+
+extern bool cyw43_poll_required;
+
+#define CYW43_POST_POLL_HOOK cyw43_post_poll_hook();
+#endif
+
+#ifndef DOXYGEN_GENERATION // multiple definitions in separate headers seems to confused doxygen
+#define cyw43_arch_lwip_begin() ((void)0)
+#define cyw43_arch_lwip_end() ((void)0)
+
+static inline int cyw43_arch_lwip_protect(int (*func)(void *param), void *param) {
+    return func(param);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_threadsafe_background.h b/src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_threadsafe_background.h
new file mode 100644
index 000000000..713fcc1a8
--- /dev/null
+++ b/src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_threadsafe_background.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_CYW43_ARCH_ARCH_THREADSAFE_BACKGROUND_H
+#define _PICO_CYW43_ARCH_ARCH_THREADSAFE_BACKGROUND_H
+
+#include "pico/cyw43_arch/arch_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void cyw43_thread_enter(void);
+
+void cyw43_thread_exit(void);
+
+#define CYW43_THREAD_ENTER cyw43_thread_enter();
+#define CYW43_THREAD_EXIT cyw43_thread_exit();
+#ifndef NDEBUG
+
+void cyw43_thread_lock_check(void);
+
+#define cyw43_arch_lwip_check() cyw43_thread_lock_check()
+#define CYW43_THREAD_LOCK_CHECK cyw43_arch_lwip_check();
+#else
+#define cyw43_arch_lwip_check() ((void)0)
+#define CYW43_THREAD_LOCK_CHECK
+#endif
+
+void cyw43_await_background_or_timeout_us(uint32_t timeout_us);
+// todo not 100% sure about the timeouts here; MP uses __WFI which will always wakeup periodically
+#define CYW43_SDPCM_SEND_COMMON_WAIT cyw43_await_background_or_timeout_us(1000);
+#define CYW43_DO_IOCTL_WAIT cyw43_await_background_or_timeout_us(1000);
+
+void cyw43_delay_ms(uint32_t ms);
+
+void cyw43_delay_us(uint32_t us);
+
+void cyw43_schedule_internal_poll_dispatch(void (*func)(void));
+
+void cyw43_post_poll_hook(void);
+
+#define CYW43_POST_POLL_HOOK cyw43_post_poll_hook();
+
+static inline void cyw43_arch_lwip_begin(void) {
+    cyw43_thread_enter();
+}
+
+static inline void cyw43_arch_lwip_end(void) {
+    cyw43_thread_exit();
+}
+
+static inline int cyw43_arch_lwip_protect(int (*func)(void *param), void *param) {
+    cyw43_arch_lwip_begin();
+    int rc = func(param);
+    cyw43_arch_lwip_end();
+    return rc;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c b/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c
index ad9e82298..503cd12c4 100644
--- a/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c
+++ b/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c
@@ -17,12 +17,12 @@
 #define LS_K   0b10
 #define LS_SE1 0b11
 
+#if PICO_RP2040_B0_SUPPORTED || PICO_RP2040_B1_SUPPORTED
 static void hw_enumeration_fix_wait_se0(void);
 static void hw_enumeration_fix_force_ls_j(void);
 static void hw_enumeration_fix_finish(void);
 
 void rp2040_usb_device_enumeration_fix(void) {
-#if PICO_RP2040_B0_SUPPORTED || PICO_RP2040_B1_SUPPORTED
     // Actually check for B0/B1 h/w
     if (rp2040_chip_version() == 1) {
         // After coming out of reset, the hardware expects 800us of LS_J (linestate J) time
@@ -36,7 +36,6 @@ void rp2040_usb_device_enumeration_fix(void) {
         // Wait SE0 phase will call force ls_j phase which will call finish phase
         hw_enumeration_fix_wait_se0();
     }
-#endif
 }
 
 static inline uint8_t hw_line_state(void) {
@@ -146,3 +145,9 @@ static void hw_enumeration_fix_finish(void) {
     // Restore the pad ctrl value
     padsbank0_hw->io[dp] = pad_ctrl_prev;
 }
+
+#else
+void rp2040_usb_device_enumeration_fix(void) {
+    // nothing to do
+}
+#endif
\ No newline at end of file
diff --git a/src/rp2_common/pico_lwip/CMakeLists.txt b/src/rp2_common/pico_lwip/CMakeLists.txt
new file mode 100644
index 000000000..7b1a8a701
--- /dev/null
+++ b/src/rp2_common/pico_lwip/CMakeLists.txt
@@ -0,0 +1,278 @@
+if (DEFINED ENV{PICO_LWIP_PATH} AND (NOT PICO_LWIP_PATH))
+    set(PICO_LWIP_PATH $ENV{PICO_LWIP_PATH})
+    message("Using PICO_LWIP_PATH from environment ('${PICO_LWIP_PATH}')")
+endif ()
+
+set(LWIP_TEST_PATH "src/Filelists.cmake")
+if (NOT PICO_LWIP_PATH)
+    set(PICO_LWIP_PATH ${PROJECT_SOURCE_DIR}/lib/lwip)
+#    if (NOT EXISTS ${PICO_LWIP_PATH}/${LWIP_TEST_PATH})
+#        message(WARNING "LWIP submodule has not been initialized; Pico W wireless support will be unavailable
+#hint: try 'git submodule update --init' from your SDK directory (${PICO_SDK_PATH}).")
+#    endif()
+elseif (NOT EXISTS ${PICO_LWIP_PATH}/${LWIP_TEST_PATH})
+    message(WARNING "PICO_LWIP_PATH specified but content not present.")
+endif()
+
+if (EXISTS ${PICO_LWIP_PATH}/${LWIP_TEST_PATH})
+    message("lwIP available at ${PICO_LWIP_PATH}")
+
+    # argh... wanted to use this, but they dump stuff into the source tree, which breaks parallel builds
+    #set(LWIP_DIR ${PICO_LWIP_PATH})
+    #include(${PICO_LWIP_PATH}/src/Filelists.cmake)
+
+    pico_register_common_scope_var(PICO_LWIP_PATH)
+
+    # The minimum set of files needed for lwIP.
+    add_library(pico_lwip_core INTERFACE)
+    target_sources(pico_lwip_core INTERFACE
+            ${PICO_LWIP_PATH}/src/core/init.c
+            ${PICO_LWIP_PATH}/src/core/def.c
+            ${PICO_LWIP_PATH}/src/core/dns.c
+            ${PICO_LWIP_PATH}/src/core/inet_chksum.c
+            ${PICO_LWIP_PATH}/src/core/ip.c
+            ${PICO_LWIP_PATH}/src/core/mem.c
+            ${PICO_LWIP_PATH}/src/core/memp.c
+            ${PICO_LWIP_PATH}/src/core/netif.c
+            ${PICO_LWIP_PATH}/src/core/pbuf.c
+            ${PICO_LWIP_PATH}/src/core/raw.c
+            ${PICO_LWIP_PATH}/src/core/stats.c
+            ${PICO_LWIP_PATH}/src/core/sys.c
+            ${PICO_LWIP_PATH}/src/core/altcp.c
+            ${PICO_LWIP_PATH}/src/core/altcp_alloc.c
+            ${PICO_LWIP_PATH}/src/core/altcp_tcp.c
+            ${PICO_LWIP_PATH}/src/core/tcp.c
+            ${PICO_LWIP_PATH}/src/core/tcp_in.c
+            ${PICO_LWIP_PATH}/src/core/tcp_out.c
+            ${PICO_LWIP_PATH}/src/core/timeouts.c
+            ${PICO_LWIP_PATH}/src/core/udp.c
+            ${CMAKE_CURRENT_LIST_DIR}/random.c
+            )
+    target_include_directories(pico_lwip_core INTERFACE
+            ${PICO_LWIP_PATH}/src/include)
+
+    add_library(pico_lwip_core4 INTERFACE)
+    target_sources(pico_lwip_core4 INTERFACE
+            ${PICO_LWIP_PATH}/src/core/ipv4/acd.c
+            ${PICO_LWIP_PATH}/src/core/ipv4/autoip.c
+            ${PICO_LWIP_PATH}/src/core/ipv4/dhcp.c
+            ${PICO_LWIP_PATH}/src/core/ipv4/etharp.c
+            ${PICO_LWIP_PATH}/src/core/ipv4/icmp.c
+            ${PICO_LWIP_PATH}/src/core/ipv4/igmp.c
+            ${PICO_LWIP_PATH}/src/core/ipv4/ip4_frag.c
+            ${PICO_LWIP_PATH}/src/core/ipv4/ip4.c
+            ${PICO_LWIP_PATH}/src/core/ipv4/ip4_addr.c
+            )
+
+    add_library(pico_lwip_core6 INTERFACE)
+    target_sources(pico_lwip_core6 INTERFACE
+            ${PICO_LWIP_PATH}/src/core/ipv6/dhcp6.c
+            ${PICO_LWIP_PATH}/src/core/ipv6/ethip6.c
+            ${PICO_LWIP_PATH}/src/core/ipv6/icmp6.c
+            ${PICO_LWIP_PATH}/src/core/ipv6/inet6.c
+            ${PICO_LWIP_PATH}/src/core/ipv6/ip6.c
+            ${PICO_LWIP_PATH}/src/core/ipv6/ip6_addr.c
+            ${PICO_LWIP_PATH}/src/core/ipv6/ip6_frag.c
+            ${PICO_LWIP_PATH}/src/core/ipv6/mld6.c
+            ${PICO_LWIP_PATH}/src/core/ipv6/nd6.c
+            )
+
+    # APIFILES: The files which implement the sequential and socket APIs.
+    add_library(pico_lwip_api INTERFACE)
+    target_sources(pico_lwip_api INTERFACE
+            ${PICO_LWIP_PATH}/src/api/api_lib.c
+            ${PICO_LWIP_PATH}/src/api/api_msg.c
+            ${PICO_LWIP_PATH}/src/api/err.c
+            ${PICO_LWIP_PATH}/src/api/if_api.c
+            ${PICO_LWIP_PATH}/src/api/netbuf.c
+            ${PICO_LWIP_PATH}/src/api/netdb.c
+            ${PICO_LWIP_PATH}/src/api/netifapi.c
+            ${PICO_LWIP_PATH}/src/api/sockets.c
+            ${PICO_LWIP_PATH}/src/api/tcpip.c
+            )
+
+    # Files implementing various generic network interface functions
+    add_library(pico_lwip_netif INTERFACE)
+    target_sources(pico_lwip_netif INTERFACE
+            ${PICO_LWIP_PATH}/src/netif/ethernet.c
+            ${PICO_LWIP_PATH}/src/netif/bridgeif.c
+            ${PICO_LWIP_PATH}/src/netif/bridgeif_fdb.c
+            ${PICO_LWIP_PATH}/src/netif/slipif.c
+            )
+
+    # 6LoWPAN
+    add_library(pico_lwip_sixlowpan INTERFACE)
+    target_sources(pico_lwip_sixlowpan INTERFACE
+            ${PICO_LWIP_PATH}/src/netif/lowpan6_common.c
+            ${PICO_LWIP_PATH}/src/netif/lowpan6.c
+            ${PICO_LWIP_PATH}/src/netif/lowpan6_ble.c
+            ${PICO_LWIP_PATH}/src/netif/zepif.c
+            )
+
+    # PPP
+    add_library(pico_lwip_ppp INTERFACE)
+    target_sources(pico_lwip_ppp INTERFACE
+            ${PICO_LWIP_PATH}/src/netif/ppp/auth.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/ccp.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/chap-md5.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/chap_ms.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/chap-new.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/demand.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/eap.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/ecp.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/eui64.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/fsm.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/ipcp.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/ipv6cp.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/lcp.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/magic.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/mppe.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/multilink.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/ppp.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/pppapi.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/pppcrypt.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/pppoe.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/pppol2tp.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/pppos.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/upap.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/utils.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/vj.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/polarssl/arc4.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/polarssl/des.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/polarssl/md4.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/polarssl/md5.c
+            ${PICO_LWIP_PATH}/src/netif/ppp/polarssl/sha1.c
+            )
+
+    # SNMPv3 agent
+    add_library(pico_lwip_snmp INTERFACE)
+    target_sources(pico_lwip_snmp INTERFACE
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmp_asn1.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmp_core.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmp_mib2.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmp_mib2_icmp.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmp_mib2_interfaces.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmp_mib2_ip.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmp_mib2_snmp.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmp_mib2_system.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmp_mib2_tcp.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmp_mib2_udp.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmp_snmpv2_framework.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmp_snmpv2_usm.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmp_msg.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmpv3.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmp_netconn.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmp_pbuf_stream.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmp_raw.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmp_scalar.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmp_table.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmp_threadsync.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmp_traps.c
+            )
+
+    # HTTP server + client
+    add_library(pico_lwip_http INTERFACE)
+    target_sources(pico_lwip_http INTERFACE
+            ${PICO_LWIP_PATH}/src/apps/http/altcp_proxyconnect.c
+            ${PICO_LWIP_PATH}/src/apps/http/fs.c
+            ${PICO_LWIP_PATH}/src/apps/http/http_client.c
+            ${PICO_LWIP_PATH}/src/apps/http/httpd.c
+            )
+
+    # MAKEFSDATA HTTP server host utility
+    add_library(pico_lwip_makefsdata INTERFACE)
+    target_sources(pico_lwip_makefsdata INTERFACE
+            ${PICO_LWIP_PATH}/src/apps/http/makefsdata/makefsdata.c
+            )
+
+    # iperf
+    add_library(pico_lwip_iperf INTERFACE)
+    target_sources(pico_lwip_iperf INTERFACE
+            ${PICO_LWIP_PATH}/src/apps/lwiperf/lwiperf.c
+            )
+
+    # SMTP client
+    add_library(pico_lwip_smtp INTERFACE)
+    target_sources(pico_lwip_smtp INTERFACE
+            ${PICO_LWIP_PATH}/src/apps/smtp/smtp.c
+            )
+
+    # SNTP client
+    add_library(pico_lwip_sntp INTERFACE)
+    target_sources(pico_lwip_sntp INTERFACE
+            ${PICO_LWIP_PATH}/src/apps/sntp/sntp.c
+            )
+
+    # MDNS responder
+    add_library(pico_lwip_mdns INTERFACE)
+    target_sources(pico_lwip_mdns INTERFACE
+            ${PICO_LWIP_PATH}/src/apps/mdns/mdns.c
+            ${PICO_LWIP_PATH}/src/apps/mdns/mdns_out.c
+            ${PICO_LWIP_PATH}/src/apps/mdns/mdns_domain.c
+            )
+
+    # NetBIOS name server
+    add_library(pico_lwip_netbios INTERFACE)
+    target_sources(pico_lwip_netbios INTERFACE
+            ${PICO_LWIP_PATH}/src/apps/netbiosns/netbiosns.c
+            )
+
+    # TFTP server files
+    add_library(pico_lwip_tftp INTERFACE)
+    target_sources(pico_lwip_tftp INTERFACE
+            ${PICO_LWIP_PATH}/src/apps/tftp/tftp.c
+            )
+
+    # MQTT client files
+    add_library(pico_lwip_mbedtls INTERFACE)
+    target_sources(pico_lwip_mbedtls INTERFACE
+            ${PICO_LWIP_PATH}/src/apps/altcp_tls/altcp_tls_mbedtls.c
+            ${PICO_LWIP_PATH}/src/apps/altcp_tls/altcp_tls_mbedtls_mem.c
+            ${PICO_LWIP_PATH}/src/apps/snmp/snmpv3_mbedtls.c
+            )
+
+
+    # All LWIP files without apps
+    add_library(pico_lwip INTERFACE)
+    target_link_libraries(pico_lwip INTERFACE
+        pico_lwip_core
+        pico_lwip_core4
+        pico_lwip_core6
+        pico_lwip_api
+        pico_lwip_netif
+        pico_lwip_sixlowpan
+        pico_lwip_ppp
+    )
+
+    # our arch/cc.h
+    add_library(pico_lwip_arch INTERFACE)
+    target_include_directories(pico_lwip_arch INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/include)
+
+    # our nosys impl
+    add_library(pico_lwip_nosys INTERFACE)
+    target_sources(pico_lwip_nosys INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/nosys.c
+            )
+    target_link_libraries(pico_lwip_nosys INTERFACE
+            pico_lwip_arch)
+
+
+    if (NOT PICO_LWIP_CONTRIB_PATH)
+        set(PICO_LWIP_CONTRIB_PATH ${PICO_LWIP_PATH}/contrib)
+    endif()
+    pico_register_common_scope_var(PICO_LWIP_CONTRIB_PATH)
+
+    # Make lwip_contrib_freertos library, with the FreeRTOS/lwIP code from lwip-contrib
+    add_library(pico_lwip_contrib_freertos INTERFACE)
+    target_sources(pico_lwip_contrib_freertos INTERFACE
+            ${PICO_LWIP_CONTRIB_PATH}/ports/freertos/sys_arch.c
+            )
+    target_include_directories(pico_lwip_contrib_freertos INTERFACE
+            ${PICO_LWIP_CONTRIB_PATH}/ports/freertos/include
+            )
+    target_link_libraries(pico_lwip_contrib_freertos INTERFACE
+            pico_lwip_arch)
+
+    pico_promote_common_scope_vars()
+endif()
diff --git a/src/rp2_common/pico_lwip/doc.h b/src/rp2_common/pico_lwip/doc.h
new file mode 100644
index 000000000..ede60b69c
--- /dev/null
+++ b/src/rp2_common/pico_lwip/doc.h
@@ -0,0 +1,44 @@
+/**
+ * \defgroup pico_lwip pico_lwip
+ * \brief Wrapper libraries for <a href="https://savannah.nongnu.org/projects/lwip/lwIP">lwIP</a>
+ *
+ * The following libraries are provided that contain the equivalent lwIP functionality groups:
+ *
+ * * \c \b pico_lwip_core - 
+ * * \c \b pico_lwip_core4 - 
+ * * \c \b pico_lwip_core6 - 
+ * * \c \b pico_lwip_netif -
+ * * \c \b pico_lwip_sixlowpan - 
+ * * \c \b pico_lwip_ppp -
+ * * \c \b pico_lwip_api -
+ *
+ * The following libraries are provided that contain the equivalent lwIP application support:
+ *
+ * * \c \b pico_lwip_snmp -
+ * * \c \b pico_lwip_http -
+ * * \c \b pico_lwip_makefsdata - 
+ * * \c \b pico_lwip_iperf - 
+ * * \c \b pico_lwip_smtp - 
+ * * \c \b pico_lwip_sntp - 
+ * * \c \b pico_lwip_mdns - 
+ * * \c \b pico_lwip_netbios - 
+ * * \c \b pico_lwip_tftp - 
+ * * \c \b pico_lwip_mbedtls -
+ *
+ * The SDK Provides a common set of functionality in \c \p pico_lwip which aggregates:
+ *
+ * * \c \b pico_lwip_core -
+ * * \c \b pico_lwip_core4 -
+ * * \c \b pico_lwip_core6 -
+ * * \c \b pico_lwip_netif -
+ * * \c \b pico_lwip_sixlowpan -
+ * * \c \b pico_lwip_ppp -
+ *
+ * The following additional libraries are provided:
+ *
+ * * \c \b pico_lwip - Aggregates the lwIP RAW API: \c \b pico_lwip_core, \c \b pico_lwip_core4, \c \b pico_lwip_core6, \c \b pico_lwip_api, \c \b pico_lwip_netif, \c \b pico_lwip_sixlowpan and \c \b pico_lwip_ppp. It does
+ * not include \c \b pico_lwip_api, which requires NO_SYS=0. You should include the latter separately if you want it.
+ *
+ * * \c \b pico_lwip_arch - lwIP required compiler adapters. This is not included in \c \b pico_lwip in case you wish to replace them.
+ * * \c \b pico_lwip_nosys - basic stub functions for NO_SYS mode.
+ */
diff --git a/src/rp2_common/pico_lwip/include/arch/cc.h b/src/rp2_common/pico_lwip/include/arch/cc.h
new file mode 100644
index 000000000..447e4d24e
--- /dev/null
+++ b/src/rp2_common/pico_lwip/include/arch/cc.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __CC_H__
+#define __CC_H__
+
+#if NO_SYS
+// todo really we should just not allow SYS_LIGHTWEIGHT_PROT for nosys mode (it doesn't do anything anyway)
+typedef int sys_prot_t;
+#endif
+
+/* define compiler specific symbols */
+#if defined (__ICCARM__)
+
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_STRUCT
+#define PACK_STRUCT_END
+#define PACK_STRUCT_FIELD(x) x
+#define PACK_STRUCT_USE_INCLUDES
+
+#elif defined (__CC_ARM)
+
+#define PACK_STRUCT_BEGIN __packed
+#define PACK_STRUCT_STRUCT
+#define PACK_STRUCT_END
+#define PACK_STRUCT_FIELD(x) x
+
+#elif defined (__GNUC__)
+
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_STRUCT __attribute__ ((__packed__))
+#define PACK_STRUCT_END
+#define PACK_STRUCT_FIELD(x) x
+
+#elif defined (__TASKING__)
+
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_STRUCT
+#define PACK_STRUCT_END
+#define PACK_STRUCT_FIELD(x) x
+
+#endif
+
+#define LWIP_PLATFORM_ASSERT(x) do { if(!(x)) while(1); } while(0)
+
+unsigned int pico_lwip_rand(void);
+#ifndef LWIP_RAND
+// Use ROSC based random number generation, more for the fact that rand() may not be seeded, than anything else
+#define LWIP_RAND pico_lwip_rand
+#endif
+#endif /* __CC_H__ */
diff --git a/src/rp2_common/pico_lwip/nosys.c b/src/rp2_common/pico_lwip/nosys.c
new file mode 100644
index 000000000..4e7605db7
--- /dev/null
+++ b/src/rp2_common/pico_lwip/nosys.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "lwip/init.h"
+#include "pico/time.h"
+
+#if NO_SYS
+/* lwip has provision for using a mutex, when applicable */
+sys_prot_t sys_arch_protect(void) {
+    return 0;
+}
+
+void sys_arch_unprotect(sys_prot_t pval) {
+    (void) pval;
+}
+
+/* lwip needs a millisecond time source, and the TinyUSB board support code has one available */
+uint32_t sys_now(void) {
+    return to_ms_since_boot(get_absolute_time());
+}
+
+#endif
+
diff --git a/src/rp2_common/pico_lwip/random.c b/src/rp2_common/pico_lwip/random.c
new file mode 100644
index 000000000..2c4cdf878
--- /dev/null
+++ b/src/rp2_common/pico_lwip/random.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico.h"
+#include "hardware/structs/rosc.h"
+
+static uint8_t pico_lwip_random_byte(int cycles) {
+    static uint8_t byte;
+    assert(cycles >= 8);
+    assert(rosc_hw->status & ROSC_STATUS_ENABLED_BITS);
+    for(int i=0;i<cycles;i++) {
+        // picked a fairly arbitrary polynomial of 0x35u - this doesn't have to be crazily uniform.
+        byte = ((byte << 1) | rosc_hw->randombit) ^ (byte & 0x80u ? 0x35u : 0);
+        // delay a little because the random bit is a little slow
+        busy_wait_at_least_cycles(30);
+    }
+    return byte;
+}
+
+unsigned int pico_lwip_rand(void) {
+    uint32_t value = 0;
+    for (int i = 0; i < 4; i++) {
+        value = (value << 8u) | pico_lwip_random_byte(32);
+    }
+    return value;
+}
\ No newline at end of file
diff --git a/src/rp2_common/tinyusb/CMakeLists.txt b/src/rp2_common/tinyusb/CMakeLists.txt
index ea919cd64..897878855 100644
--- a/src/rp2_common/tinyusb/CMakeLists.txt
+++ b/src/rp2_common/tinyusb/CMakeLists.txt
@@ -53,5 +53,6 @@ if (EXISTS ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH})
                 PROPERTIES
                 COMPILE_FLAGS "-Wno-stringop-overflow -Wno-array-bounds")
     endfunction()
+
     pico_promote_common_scope_vars()
 endif()
diff --git a/test/kitchen_sink/CMakeLists.txt b/test/kitchen_sink/CMakeLists.txt
index 3487fbb31..a2019919c 100644
--- a/test/kitchen_sink/CMakeLists.txt
+++ b/test/kitchen_sink/CMakeLists.txt
@@ -41,11 +41,6 @@ target_link_libraries(kitchen_sink_libs INTERFACE
     pico_unique_id
     pico_util
 )
-# todo this is full of warnings atm
-#if (TARGET tinyusb_device)
-#    target_include_directories(kitchen_sink_libs INTERFACE ${CMAKE_CURRENT_LIST_DIR})
-#    target_link_libraries(kitchen_sink_libs INTERFACE tinyusb_device)
-#endif()
 
 add_library(kitchen_sink_options INTERFACE)
 
@@ -63,7 +58,7 @@ target_compile_options(kitchen_sink_options INTERFACE
         -Wcast-qual
         -Wfloat-equal
         -Wmissing-format-attribute
-        -Wconversion
+        #-Wconversion
         -Wsign-compare
         $<$<COMPILE_LANGUAGE:C>:-Wstrict-prototypes>
 
@@ -100,6 +95,13 @@ if (COMMAND suppress_tinyusb_warnings)
     # TinyUSB itself, so we have to guard against TinyUSB not being present with the above if
     suppress_tinyusb_warnings()
 endif()
+if (TARGET pico_lwip)
+    set_source_files_properties(
+            ${PICO_LWIP_PATH}/src/core/ipv4/ip4_frag.c
+            PROPERTIES
+            COMPILE_FLAGS "-Wno-null-dereference")
+
+endif()
 target_link_libraries(kitchen_sink_extra_stdio kitchen_sink_libs kitchen_sink_options)
 pico_add_extra_outputs(kitchen_sink_extra_stdio)
 pico_enable_stdio_usb(kitchen_sink_extra_stdio 1)
@@ -119,3 +121,25 @@ add_executable(kitchen_sink_cpp ${CMAKE_CURRENT_LIST_DIR}/kitchen_sink_cpp.cpp)
 target_link_libraries(kitchen_sink_cpp kitchen_sink_libs kitchen_sink_options)
 pico_set_program_name(kitchen_sink_cpp "Wombat tentacles CPP")
 pico_add_extra_outputs(kitchen_sink_cpp)
+
+if (TARGET pico_cyw43_arch)
+    # for lwipopts.h
+    add_executable(kitchen_sink_lwip_poll ${CMAKE_CURRENT_LIST_DIR}/kitchen_sink.c)
+    target_link_libraries(kitchen_sink_lwip_poll kitchen_sink_libs kitchen_sink_options)
+    pico_add_extra_outputs(kitchen_sink_lwip_poll)
+    target_link_libraries(kitchen_sink_lwip_poll
+            pico_cyw43_arch_lwip_poll)
+    # for lwipopts.h
+    target_include_directories(kitchen_sink_lwip_poll PRIVATE
+            ${CMAKE_CURRENT_LIST_DIR})
+
+    add_executable(kitchen_sink_lwip_background ${CMAKE_CURRENT_LIST_DIR}/kitchen_sink.c)
+    target_link_libraries(kitchen_sink_lwip_background kitchen_sink_libs kitchen_sink_options)
+    pico_add_extra_outputs(kitchen_sink_lwip_background)
+    target_link_libraries(kitchen_sink_lwip_background
+            pico_cyw43_arch_lwip_threadsafe_background)
+    # for lwipopts.h
+    target_include_directories(kitchen_sink_lwip_background PRIVATE
+            ${CMAKE_CURRENT_LIST_DIR})
+
+endif()
diff --git a/test/kitchen_sink/kitchen_sink.c b/test/kitchen_sink/kitchen_sink.c
index 62fe03a07..a49654d1b 100644
--- a/test/kitchen_sink/kitchen_sink.c
+++ b/test/kitchen_sink/kitchen_sink.c
@@ -47,6 +47,9 @@
 #include "pico/sync.h"
 #include "pico/time.h"
 #include "pico/unique_id.h"
+#if LIB_PICO_CYW43_ARCH
+#include "pico/cyw43_arch.h"
+#endif
 
 #include "hardware/structs/adc.h"
 #include "hardware/structs/bus_ctrl.h"
diff --git a/test/kitchen_sink/lwipopts.h b/test/kitchen_sink/lwipopts.h
new file mode 100644
index 000000000..58b704a1c
--- /dev/null
+++ b/test/kitchen_sink/lwipopts.h
@@ -0,0 +1,14 @@
+#ifndef _LWIPOPTS_H
+#define _LWIPOPTS_H
+
+// dummy lwip opts to allow compilation
+
+#define NO_SYS                      1
+#define LWIP_DHCP                   1
+#define LWIP_RAW                    1
+#define LWIP_NETIF_HOSTNAME         1
+#define LWIP_NETIF_STATUS_CALLBACK  1
+#define LWIP_DNS                    1
+#define LWIP_SOCKET                 0
+#define LWIP_NETCONN                0
+#endif
\ No newline at end of file

From 2e6142b15b8a75c1227dd3edbe839193b2bf9041 Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Wed, 29 Jun 2022 22:56:27 -0500
Subject: [PATCH 31/51] SDK 1.4.0 release

---
 pico_sdk_version.cmake | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/pico_sdk_version.cmake b/pico_sdk_version.cmake
index bd6fdbf12..f00759ae4 100644
--- a/pico_sdk_version.cmake
+++ b/pico_sdk_version.cmake
@@ -3,13 +3,13 @@
 set(PICO_SDK_VERSION_MAJOR 1)
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, group=pico_base
 # PICO_CONFIG: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, group=pico_base
-set(PICO_SDK_VERSION_MINOR 3)
+set(PICO_SDK_VERSION_MINOR 4)
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, group=pico_base
 # PICO_CONFIG: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, group=pico_base
-set(PICO_SDK_VERSION_REVISION 2)
+set(PICO_SDK_VERSION_REVISION 0)
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base
 # PICO_CONFIG: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base
-set(PICO_SDK_VERSION_PRE_RELEASE_ID develop)
+#set(PICO_SDK_VERSION_PRE_RELEASE_ID develop)
 
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base
 # PICO_CONFIG: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base

From d1e7294dab75939a14224f90fcdd78b67ce55640 Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Thu, 30 Jun 2022 01:20:10 -0500
Subject: [PATCH 32/51] Start SDK 1.4.1 development

---
 pico_sdk_version.cmake | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/pico_sdk_version.cmake b/pico_sdk_version.cmake
index f00759ae4..8a4827f2b 100644
--- a/pico_sdk_version.cmake
+++ b/pico_sdk_version.cmake
@@ -6,10 +6,10 @@ set(PICO_SDK_VERSION_MAJOR 1)
 set(PICO_SDK_VERSION_MINOR 4)
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, group=pico_base
 # PICO_CONFIG: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, group=pico_base
-set(PICO_SDK_VERSION_REVISION 0)
+set(PICO_SDK_VERSION_REVISION 1)
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base
 # PICO_CONFIG: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base
-#set(PICO_SDK_VERSION_PRE_RELEASE_ID develop)
+set(PICO_SDK_VERSION_PRE_RELEASE_ID develop)
 
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base
 # PICO_CONFIG: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base

From 0fa3e7247dd9897e380f3a6756887cedb3939482 Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Wed, 27 Jul 2022 08:24:42 -0500
Subject: [PATCH 33/51] Some PIO setup was using SM 0 rather than the allocated
 SM (#940)

---
 src/rp2_common/cyw43_driver/cyw43_bus_pio_spi.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/rp2_common/cyw43_driver/cyw43_bus_pio_spi.c b/src/rp2_common/cyw43_driver/cyw43_bus_pio_spi.c
index 0fd17f489..12b633a7e 100644
--- a/src/rp2_common/cyw43_driver/cyw43_bus_pio_spi.c
+++ b/src/rp2_common/cyw43_driver/cyw43_bus_pio_spi.c
@@ -258,13 +258,13 @@ int cyw43_spi_transfer(cyw43_int_t *self, const uint8_t *tx, size_t tx_length, u
 
         dma_channel_config out_config = dma_channel_get_default_config(bus_data->dma_out);
         channel_config_set_bswap(&out_config, true);
-        channel_config_set_dreq(&out_config, pio_get_dreq(bus_data->pio, 0, true));
+        channel_config_set_dreq(&out_config, pio_get_dreq(bus_data->pio, bus_data->pio_sm, true));
 
         dma_channel_configure(bus_data->dma_out, &out_config, &bus_data->pio->txf[0], tx, tx_length / 4, true);
 
         dma_channel_config in_config = dma_channel_get_default_config(bus_data->dma_in);
         channel_config_set_bswap(&in_config, true);
-        channel_config_set_dreq(&in_config, pio_get_dreq(bus_data->pio, 0, false));
+        channel_config_set_dreq(&in_config, pio_get_dreq(bus_data->pio, bus_data->pio_sm, false));
         channel_config_set_write_increment(&in_config, true);
         channel_config_set_read_increment(&in_config, false);
         dma_channel_configure(bus_data->dma_in, &in_config, rx + tx_length, &bus_data->pio->rxf[0], rx_length / 4 - tx_length / 4, true);
@@ -299,12 +299,12 @@ int cyw43_spi_transfer(cyw43_int_t *self, const uint8_t *tx, size_t tx_length, u
 
         dma_channel_config out_config = dma_channel_get_default_config(bus_data->dma_out);
         channel_config_set_bswap(&out_config, true);
-        channel_config_set_dreq(&out_config, pio_get_dreq(bus_data->pio, 0, true));
+        channel_config_set_dreq(&out_config, pio_get_dreq(bus_data->pio, bus_data->pio_sm, true));
 
         dma_channel_configure(bus_data->dma_out, &out_config, &bus_data->pio->txf[0], tx, tx_length / 4, true);
 
         bus_data->pio->fdebug = 1u << PIO_FDEBUG_TXSTALL_LSB;
-        pio_sm_set_enabled(bus_data->pio, 0, true);
+        pio_sm_set_enabled(bus_data->pio, bus_data->pio_sm, true);
         while (!(bus_data->pio->fdebug & (1u << PIO_FDEBUG_TXSTALL_LSB))) {
             tight_loop_contents(); // todo timeout
         }

From de8f857de4b970fe3afc923d166e7176a5e4bd1c Mon Sep 17 00:00:00 2001
From: "Mr. Green's Workshop"
 <76992231+MrGreensWorkshop@users.noreply.github.com>
Date: Tue, 2 Aug 2022 21:26:04 +0900
Subject: [PATCH 34/51] fix typo datsheet -> datasheet (#942)

fix typo datsheet -> datasheet
---
 src/rp2_common/hardware_gpio/include/hardware/gpio.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/rp2_common/hardware_gpio/include/hardware/gpio.h b/src/rp2_common/hardware_gpio/include/hardware/gpio.h
index 09a9b96a6..1dff2587f 100644
--- a/src/rp2_common/hardware_gpio/include/hardware/gpio.h
+++ b/src/rp2_common/hardware_gpio/include/hardware/gpio.h
@@ -85,7 +85,7 @@ extern "C" {
  * selected on one GPIO at a time. If the same peripheral input is connected to multiple GPIOs, the peripheral sees the logical
  * OR of these GPIO inputs.
  *
- * Please refer to the datsheet for more information on GPIO function selection.
+ * Please refer to the datasheet for more information on GPIO function selection.
  */
 enum gpio_function {
     GPIO_FUNC_XIP = 0,

From 17c759b6e9f24e8f52158d85b3680d7a1255f3c9 Mon Sep 17 00:00:00 2001
From: Andrew Scheller <andrew.scheller@raspberrypi.com>
Date: Tue, 2 Aug 2022 13:28:37 +0100
Subject: [PATCH 35/51] Fix various typos in CMake CONFIG lines. Also add a
 script that found some of these errors. (#907)

---
 cmake/pico_pre_load_platform.cmake                |  2 +-
 pico_sdk_version.cmake                            | 10 +++++-----
 src/common/pico_base/generate_config_header.cmake |  6 +++---
 src/rp2_common.cmake                              |  8 ++++----
 src/rp2_common/pico_standard_link/CMakeLists.txt  |  4 ++--
 src/rp2_common/pico_stdlib/CMakeLists.txt         |  4 ++--
 tools/CMakeLists.txt                              |  2 +-
 tools/check_configs.sh                            |  9 +++++++++
 8 files changed, 27 insertions(+), 18 deletions(-)
 create mode 100755 tools/check_configs.sh

diff --git a/cmake/pico_pre_load_platform.cmake b/cmake/pico_pre_load_platform.cmake
index 51ee39a00..479eedf3b 100644
--- a/cmake/pico_pre_load_platform.cmake
+++ b/cmake/pico_pre_load_platform.cmake
@@ -13,7 +13,7 @@ endif ()
 
 set(PICO_PLATFORM ${PICO_PLATFORM} CACHE STRING "PICO Build platform (e.g. rp2040, host)")
 
-# PICO_CMAKE_CONFIG: PICO_CMAKE_RELOAD_PLATFORM_FILE, custom CMake file to use to set up the platform environment, default=none, group=build
+# PICO_CMAKE_CONFIG: PICO_CMAKE_PRELOAD_PLATFORM_FILE, custom CMake file to use to set up the platform environment, default=none, group=build
 set(PICO_CMAKE_PRELOAD_PLATFORM_FILE "" CACHE INTERNAL "")
 set(PICO_CMAKE_PRELOAD_PLATFORM_DIR "${CMAKE_CURRENT_LIST_DIR}/preload/platforms" CACHE INTERNAL "")
 
diff --git a/pico_sdk_version.cmake b/pico_sdk_version.cmake
index 8a4827f2b..63b30025d 100644
--- a/pico_sdk_version.cmake
+++ b/pico_sdk_version.cmake
@@ -1,18 +1,18 @@
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_MAJOR, SDK major version number, type=int, group=pico_base
-# PICO_CONFIG: PICO_SDK_VERSION_MAJOR, SDK major version number, type=int, group=pico_base
+# PICO_CMAKE_CONFIG: PICO_SDK_VERSION_MAJOR, SDK major version number, type=int, group=pico_base
 set(PICO_SDK_VERSION_MAJOR 1)
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, group=pico_base
-# PICO_CONFIG: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, group=pico_base
+# PICO_CMAKE_CONFIG: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, group=pico_base
 set(PICO_SDK_VERSION_MINOR 4)
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, group=pico_base
-# PICO_CONFIG: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, group=pico_base
+# PICO_CMAKE_CONFIG: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, group=pico_base
 set(PICO_SDK_VERSION_REVISION 1)
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base
-# PICO_CONFIG: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base
+# PICO_CMAKE_CONFIG: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base
 set(PICO_SDK_VERSION_PRE_RELEASE_ID develop)
 
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base
-# PICO_CONFIG: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base
+# PICO_CMAKE_CONFIG: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base
 set(PICO_SDK_VERSION_STRING "${PICO_SDK_VERSION_MAJOR}.${PICO_SDK_VERSION_MINOR}.${PICO_SDK_VERSION_REVISION}")
 
 if (PICO_SDK_VERSION_PRE_RELEASE_ID)
diff --git a/src/common/pico_base/generate_config_header.cmake b/src/common/pico_base/generate_config_header.cmake
index 333dfa750..98401057c 100644
--- a/src/common/pico_base/generate_config_header.cmake
+++ b/src/common/pico_base/generate_config_header.cmake
@@ -13,8 +13,8 @@ endmacro()
 # PICO_CMAKE_CONFIG: PICO_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for all platforms, type=list, default="", group=pico_base
 add_header_content_from_var(PICO_CONFIG_HEADER_FILES)
 
-# PICO_CMAKE_CONFIG: PICO_CONFIG_RP2040_HEADER_FILES, List of extra header files to include from pico/config.h for rp2040 platform, type=list, default="", group=pico_base
-# PICO_CMAKE_CONFIG: PICO_CONFIG_HOST_HEADER_FILES, List of extra header files to include from pico/config.h for host platform, type=list, default="", group=pico_base
+# PICO_CMAKE_CONFIG: PICO_RP2040_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for rp2040 platform, type=list, default="", group=pico_base
+# PICO_CMAKE_CONFIG: PICO_HOST_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for host platform, type=list, default="", group=pico_base
 add_header_content_from_var(PICO_${PICO_PLATFORM_UPPER}_CONFIG_HEADER_FILES)
 
 file(GENERATE
@@ -26,4 +26,4 @@ configure_file( ${CMAKE_CURRENT_LIST_DIR}/include/pico/version.h.in ${CMAKE_BINA
 
 foreach(DIR IN LISTS PICO_INCLUDE_DIRS)
     target_include_directories(pico_base_headers INTERFACE ${DIR})
-endforeach()
\ No newline at end of file
+endforeach()
diff --git a/src/rp2_common.cmake b/src/rp2_common.cmake
index c04e55144..63e230802 100644
--- a/src/rp2_common.cmake
+++ b/src/rp2_common.cmake
@@ -49,11 +49,11 @@ endfunction()
 add_subdirectory(common)
 add_subdirectory(rp2_common)
 
-# PICO_CMAKE_CONFIG: PICO_NO_HARDWARE, OPTION: Whether the build is not targeting an RP2040 device,  type=bool, default=1 for PICO_PLATFORM=host 0 otherwise, group=build
-# PICO_BUILD_DEFINE: PICO_NO_HARDWARE, Whether the build is not targeting an RP2040 device,  type=bool, default=1 for PICO_PLATFORM=host 0 otherwise, group=build
+# PICO_CMAKE_CONFIG: PICO_NO_HARDWARE, OPTION: Whether the build is not targeting an RP2040 device, type=bool, default=1 when PICO_PLATFORM is host, 0 otherwise, group=build
+# PICO_BUILD_DEFINE: PICO_NO_HARDWARE, Whether the build is not targeting an RP2040 device, type=bool, default=1 when PICO_PLATFORM is host, 0 otherwise, group=build
 set(PICO_NO_HARDWARE "0" CACHE INTERNAL "")
-# PICO_CMAKE_CONFIG: PICO_ON_DEVICE, OPTION: Whether the build is targeting an RP2040 device,  type=bool, default=0 for PICO_PLATFORM=host 1 otherwise, group=build
-# PICO_BUILD_DEFIN: PICO_ON_DEVICE, Whether the build is targeting an RP2040 device,  type=bool, default=0 for PICO_PLATFORM=host 1 otherwise, group=build
+# PICO_CMAKE_CONFIG: PICO_ON_DEVICE, OPTION: Whether the build is targeting an RP2040 device, type=bool, default=0 when PICO_PLATFORM is host, 1 otherwise, group=build
+# PICO_BUILD_DEFINE: PICO_ON_DEVICE, Whether the build is targeting an RP2040 device, type=bool, default=0 when PICO_PLATFORM is host, 1 otherwise, group=build
 set(PICO_ON_DEVICE "1" CACHE INTERNAL "")
 
 set(CMAKE_EXECUTABLE_SUFFIX .elf PARENT_SCOPE)
diff --git a/src/rp2_common/pico_standard_link/CMakeLists.txt b/src/rp2_common/pico_standard_link/CMakeLists.txt
index a7305403c..2efc287c9 100644
--- a/src/rp2_common/pico_standard_link/CMakeLists.txt
+++ b/src/rp2_common/pico_standard_link/CMakeLists.txt
@@ -62,7 +62,7 @@ if (NOT TARGET pico_standard_link)
     # PICO_BUILD_DEFINE: PICO_NO_FLASH, whether this is a 'no_flash' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link
     target_compile_definitions(pico_standard_link INTERFACE PICO_NO_FLASH=$<IF:$<STREQUAL:$<TARGET_PROPERTY:PICO_TARGET_BINARY_TYPE>,no_flash>,1,$<AND:$<BOOL:${PICO_NO_FLASH}>,$<STREQUAL:,$<TARGET_PROPERTY:PICO_TARGET_BINARY_TYPE>>>>)
     # PICO_USE_BLOCKED_RAM will be set based on PICO_TARGET_BUILD_TYPE target property being equal to use_blocked_ram if set, otherwise to the value of the PICO_USE_BLOCKED_RAM cmake variable unless PICO_TARGET_TYPE is set to something else
-    # PICO_BUILD_DEFINE: PICO_USE_BLOCKS_RAM, whether this is a 'blocked_ram' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link
+    # PICO_BUILD_DEFINE: PICO_USE_BLOCKED_RAM, whether this is a 'blocked_ram' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link
     target_compile_definitions(pico_standard_link INTERFACE PICO_USE_BLOCKED_RAM=$<IF:$<STREQUAL:$<TARGET_PROPERTY:PICO_TARGET_BINARY_TYPE>,use_blocked_ram>,1,$<AND:$<BOOL:${PICO_USE_BLOCKED_RAM}>,$<STREQUAL:,$<TARGET_PROPERTY:PICO_TARGET_BINARY_TYPE>>>>)
     # PICO_COPY_TO_RAM will be set based on PICO_TARGET_BUILD_TYPE target property being equal to copy_to_ram if set, otherwise to the value of the PICO_COPY_TO_RAM cmake variable unless PICO_TARGET_TYPE is set to something else
     # PICO_BUILD_DEFINE: PICO_COPY_TO_RAM, whether this is a 'copy_to_ram' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link
@@ -89,7 +89,7 @@ if (NOT TARGET pico_standard_link)
     # this line occasionally useful for debugging ... todo maybe make a PICO_ var
     # target_compile_options(pico_standard_link INTERFACE --save-temps) #debugging only
 
-    # PICO_CMAKE_CONFIG: PICO_NO_GC_SECTIONS, Disable -ffunction-sections -fdata-sections, and --gc-sections, type=bool, default=0, advanced=true, group=pico_standard_link
+    # PICO_CMAKE_CONFIG: PICO_NO_GC_SECTIONS, Disable -ffunction-sections -fdata-sections and --gc-sections, type=bool, default=0, advanced=true, group=pico_standard_link
     if (NOT PICO_NO_GC_SECTIONS)
         target_compile_options(pico_standard_link INTERFACE -ffunction-sections -fdata-sections)
         target_link_options(pico_standard_link INTERFACE "LINKER:--gc-sections")
diff --git a/src/rp2_common/pico_stdlib/CMakeLists.txt b/src/rp2_common/pico_stdlib/CMakeLists.txt
index b54639b44..cc48743ae 100644
--- a/src/rp2_common/pico_stdlib/CMakeLists.txt
+++ b/src/rp2_common/pico_stdlib/CMakeLists.txt
@@ -2,8 +2,8 @@
 option(PICO_STDIO_UART "Globablly enable stdio UART" 1)
 # PICO_CMAKE_CONFIG: PICO_STDIO_USB, OPTION: Globally enable stdio USB, default=0, group=pico_stdlib
 option(PICO_STDIO_USB "Globablly enable stdio USB" 0)
-# PICO_CMAKE_CONFIG: PICO_STDIO_USB, OPTIONS: Globally enable stdio semihosting, default=0, group=pico_stdlib
-option(PICO_STDIO_USB "Globablly enable stdio semihosting " 0)
+# PICO_CMAKE_CONFIG: PICO_STDIO_SEMIHOSTING, OPTION: Globally enable stdio semihosting, default=0, group=pico_stdlib
+option(PICO_STDIO_SEMIHOSTING "Globablly enable stdio semihosting" 0)
 
 if (NOT TARGET pico_stdlib)
     pico_add_impl_library(pico_stdlib)
diff --git a/tools/CMakeLists.txt b/tools/CMakeLists.txt
index 59bf09f9e..bc49c9852 100644
--- a/tools/CMakeLists.txt
+++ b/tools/CMakeLists.txt
@@ -4,7 +4,7 @@ function(_pico_init_pioasm)
     find_package(Pioasm REQUIRED)
 endfunction()
 
-# PICO_DEFAULT_PIOASM_OUTPUT_FORMAT, default output format used by pioasm when using pico_generate_pio_header, default=c-sdk, group=build
+# PICO_CMAKE_CONFIG: PICO_DEFAULT_PIOASM_OUTPUT_FORMAT, default output format used by pioasm when using pico_generate_pio_header, default=c-sdk, group=build
 function(pico_generate_pio_header TARGET PIO)
     _pico_init_pioasm()
     cmake_parse_arguments(pico_generate_pio_header "" "OUTPUT_FORMAT;OUTPUT_DIR" "" ${ARGN} )
diff --git a/tools/check_configs.sh b/tools/check_configs.sh
new file mode 100755
index 000000000..95e0a4c1b
--- /dev/null
+++ b/tools/check_configs.sh
@@ -0,0 +1,9 @@
+#!/bin/bash
+# Little script to find possibly-misnamed CONFIG lines
+for CONF in PICO_CONFIG PICO_CMAKE_CONFIG PICO_BUILD_DEFINE; do
+  for DEF in $(git grep "$CONF:" | sed -n "s/.*$CONF: \+\(\w\+\).*/\1/p"); do
+    if [ $(git grep "$DEF" | wc -l) -lt 2 ]; then
+        echo "$CONF: $DEF only appears once"
+    fi
+  done
+done

From 49d7d9edfbe775a70b83b650df7829567307a7c7 Mon Sep 17 00:00:00 2001
From: Andrew Scheller <andrew.scheller@raspberrypi.com>
Date: Tue, 2 Aug 2022 13:29:08 +0100
Subject: [PATCH 36/51] typo (#905)

---
 src/rp2_common.cmake | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/rp2_common.cmake b/src/rp2_common.cmake
index 63e230802..bc82e7cb0 100644
--- a/src/rp2_common.cmake
+++ b/src/rp2_common.cmake
@@ -22,7 +22,7 @@ function(pico_add_extra_outputs TARGET)
     pico_add_bin_output(${TARGET})
     pico_add_dis_output(${TARGET})
 
-    # PICO_CMAKE_CONFIG: PICO_NO_TARGET_NAME, Don't defined PICO_TARGET_NAME, type=bool, default=0, group=build
+    # PICO_CMAKE_CONFIG: PICO_NO_TARGET_NAME, Don't define PICO_TARGET_NAME, type=bool, default=0, group=build
     # PICO_BUILD_DEFINE: PICO_TARGET_NAME, The name of the build target being compiled (unless PICO_NO_TARGET_NAME set in build), type=string, default=target name, group=build
     if (NOT PICO_NO_TARGET_NAME)
         target_compile_definitions(${TARGET} PRIVATE

From fe7849d645f8c2f05ea8a1264d79b4e1240f5be7 Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Mon, 8 Aug 2022 07:42:52 -0500
Subject: [PATCH 37/51] fix delayed_by_us and delayed_by_ms to not return times
 > at_the_end_of_time (#936)

---
 src/common/pico_time/include/pico/time.h | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/common/pico_time/include/pico/time.h b/src/common/pico_time/include/pico/time.h
index 0fde00feb..d1cc02d30 100644
--- a/src/common/pico_time/include/pico/time.h
+++ b/src/common/pico_time/include/pico/time.h
@@ -95,8 +95,9 @@ static inline absolute_time_t delayed_by_us(const absolute_time_t t, uint64_t us
     absolute_time_t t2;
     uint64_t base = to_us_since_boot(t);
     uint64_t delayed = base + us;
-    if (delayed < base) {
-        delayed = (uint64_t)-1;
+    if ((int64_t)delayed < 0) {
+        // absolute_time_t (to allow for signed time deltas) is never greater than INT64_MAX which == at_the_end_of_time
+        delayed = INT64_MAX;
     }
     update_us_since_boot(&t2, delayed);
     return t2;
@@ -113,8 +114,9 @@ static inline absolute_time_t delayed_by_ms(const absolute_time_t t, uint32_t ms
     absolute_time_t t2;
     uint64_t base = to_us_since_boot(t);
     uint64_t delayed = base + ms * 1000ull;
-    if (delayed < base) {
-        delayed = (uint64_t)-1;
+    if ((int64_t)delayed < 0) {
+        // absolute_time_t (to allow for signed time deltas) is never greater than INT64_MAX which == at_the_end_of_time
+        delayed = INT64_MAX;
     }
     update_us_since_boot(&t2, delayed);
     return t2;

From 2ebba462ac1676a4b2429ed8f6ea7764f0f34f02 Mon Sep 17 00:00:00 2001
From: Attila Wagner <attila.wagner.89@gmail.com>
Date: Mon, 8 Aug 2022 13:48:29 +0100
Subject: [PATCH 38/51] Properly terminate cyw43 task when
 `cyw43_arch_deinit()` is called (#962)

---
 src/rp2_common/pico_cyw43_arch/cyw43_arch_freertos.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/rp2_common/pico_cyw43_arch/cyw43_arch_freertos.c b/src/rp2_common/pico_cyw43_arch/cyw43_arch_freertos.c
index 88dde6ece..2bfb39eaa 100644
--- a/src/rp2_common/pico_cyw43_arch/cyw43_arch_freertos.c
+++ b/src/rp2_common/pico_cyw43_arch/cyw43_arch_freertos.c
@@ -101,6 +101,7 @@ static void cyw43_task(__unused void *param) {
         xSemaphoreGive(cyw43_worker_ran_sem);
         __sev(); // it is possible regular code is waiting on a WFE on the other core
     } while (true);
+    vTaskDelete(NULL);
 }
 
 static void tcpip_init_done(void *param) {

From 150be75aa426490a9bf615162d4a61e7e4ae83e9 Mon Sep 17 00:00:00 2001
From: Thomas Roberts <tom.p.roberts@gmail.com>
Date: Mon, 8 Aug 2022 15:14:01 +0100
Subject: [PATCH 39/51] Add pico_lwip_mqtt library (#948)

---
 src/rp2_common/pico_lwip/CMakeLists.txt | 7 ++++++-
 src/rp2_common/pico_lwip/doc.h          | 1 +
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/rp2_common/pico_lwip/CMakeLists.txt b/src/rp2_common/pico_lwip/CMakeLists.txt
index 7b1a8a701..643e26258 100644
--- a/src/rp2_common/pico_lwip/CMakeLists.txt
+++ b/src/rp2_common/pico_lwip/CMakeLists.txt
@@ -223,7 +223,7 @@ if (EXISTS ${PICO_LWIP_PATH}/${LWIP_TEST_PATH})
             ${PICO_LWIP_PATH}/src/apps/tftp/tftp.c
             )
 
-    # MQTT client files
+    # Mbed TLS files
     add_library(pico_lwip_mbedtls INTERFACE)
     target_sources(pico_lwip_mbedtls INTERFACE
             ${PICO_LWIP_PATH}/src/apps/altcp_tls/altcp_tls_mbedtls.c
@@ -231,6 +231,11 @@ if (EXISTS ${PICO_LWIP_PATH}/${LWIP_TEST_PATH})
             ${PICO_LWIP_PATH}/src/apps/snmp/snmpv3_mbedtls.c
             )
 
+    # MQTT client files
+    add_library(pico_lwip_mqtt INTERFACE)
+    target_sources(pico_lwip_mqtt INTERFACE
+            ${PICO_LWIP_PATH}/src/apps/mqtt/mqtt.c
+            )
 
     # All LWIP files without apps
     add_library(pico_lwip INTERFACE)
diff --git a/src/rp2_common/pico_lwip/doc.h b/src/rp2_common/pico_lwip/doc.h
index ede60b69c..33b15c14c 100644
--- a/src/rp2_common/pico_lwip/doc.h
+++ b/src/rp2_common/pico_lwip/doc.h
@@ -24,6 +24,7 @@
  * * \c \b pico_lwip_netbios - 
  * * \c \b pico_lwip_tftp - 
  * * \c \b pico_lwip_mbedtls -
+ * * \c \b pico_lwip_mqtt -
  *
  * The SDK Provides a common set of functionality in \c \p pico_lwip which aggregates:
  *

From 2dfaa1ab4c1b53d0fa966118ace2d542a488719e Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Mon, 8 Aug 2022 10:12:54 -0500
Subject: [PATCH 40/51] Fix various stdio_usb issues, add stdio_init_all return
 code, and add alarm_pool_core_num() API (#918)

This issue addresses possible starvation issues when using `getchar()` with `stdio_usb` and also fixes possible missing of IRQs as a result of #871
---
 src/common/pico_sync/critical_section.c       |  4 +-
 .../pico_sync/include/pico/critical_section.h | 10 +++
 src/common/pico_time/include/pico/time.h      | 10 ++-
 src/common/pico_time/time.c                   |  6 ++
 .../pico_stdio/include/pico/stdio.h           |  3 +-
 src/rp2_common/pico_stdio/stdio.c             |  9 ++-
 src/rp2_common/pico_stdio_usb/stdio_usb.c     | 62 ++++++++++++++++---
 7 files changed, 88 insertions(+), 16 deletions(-)

diff --git a/src/common/pico_sync/critical_section.c b/src/common/pico_sync/critical_section.c
index f28732b7f..7cbb6227d 100644
--- a/src/common/pico_sync/critical_section.c
+++ b/src/common/pico_sync/critical_section.c
@@ -21,7 +21,5 @@ void critical_section_init_with_lock_num(critical_section_t *crit_sec, uint lock
 
 void critical_section_deinit(critical_section_t *crit_sec) {
     spin_lock_unclaim(spin_lock_get_num(crit_sec->spin_lock));
-#ifndef NDEBUG
-    crit_sec->spin_lock = (spin_lock_t *)-1;
-#endif
+    crit_sec->spin_lock = NULL;
 }
\ No newline at end of file
diff --git a/src/common/pico_sync/include/pico/critical_section.h b/src/common/pico_sync/include/pico/critical_section.h
index 2f9449475..9d61150a8 100644
--- a/src/common/pico_sync/include/pico/critical_section.h
+++ b/src/common/pico_sync/include/pico/critical_section.h
@@ -82,6 +82,16 @@ static inline void critical_section_exit(critical_section_t *crit_sec) {
  */
 void critical_section_deinit(critical_section_t *crit_sec);
 
+/*! \brief Test whether a critical_section has been initialized
+ *  \ingroup mutex
+ *
+ * \param crit_sec Pointer to critical_section structure
+ * \return true if the critical section is initialized, false otherwise
+ */
+static inline bool critical_section_is_initialized(critical_section_t *crit_sec) {
+    return crit_sec->spin_lock != 0;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/common/pico_time/include/pico/time.h b/src/common/pico_time/include/pico/time.h
index d1cc02d30..206c24c53 100644
--- a/src/common/pico_time/include/pico/time.h
+++ b/src/common/pico_time/include/pico/time.h
@@ -200,7 +200,7 @@ static inline bool is_nil_time(absolute_time_t t) {
  * \note  These functions should not be called from an IRQ handler.
  *
  * \note  Lower powered sleep requires use of the \link alarm_pool_get_default default alarm pool\endlink which may
- * be disabled by the #PICO_TIME_DEFAULT_ALARM_POOL_DISABLED define or currently full in which case these functions
+ * be disabled by the PICO_TIME_DEFAULT_ALARM_POOL_DISABLED #define or currently full in which case these functions
  * become busy waits instead.
  *
  * \note  Whilst \a sleep_ functions are preferable to \a busy_wait functions from a power perspective, the \a busy_wait equivalent function
@@ -405,6 +405,14 @@ alarm_pool_t *alarm_pool_create(uint hardware_alarm_num, uint max_timers);
  */
 uint alarm_pool_hardware_alarm_num(alarm_pool_t *pool);
 
+/**
+ * \brief Return the core number the alarm pool was initialized on (and hence callbacks are called on)
+ * \ingroup alarm
+ * \param pool the pool
+ * \return the core used by the pool
+ */
+uint alarm_pool_core_num(alarm_pool_t *pool);
+
 /**
  * \brief Destroy the alarm pool, cancelling all alarms and freeing up the underlying hardware alarm
  * \ingroup alarm
diff --git a/src/common/pico_time/time.c b/src/common/pico_time/time.c
index 3a585f652..2618e8e47 100644
--- a/src/common/pico_time/time.c
+++ b/src/common/pico_time/time.c
@@ -31,6 +31,7 @@ typedef struct alarm_pool {
     uint8_t *entry_ids_high;
     alarm_id_t alarm_in_progress; // this is set during a callback from the IRQ handler... it can be cleared by alarm_cancel to prevent repeats
     uint8_t hardware_alarm_num;
+    uint8_t core_num;
 } alarm_pool_t;
 
 #if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
@@ -190,6 +191,7 @@ void alarm_pool_post_alloc_init(alarm_pool_t *pool, uint hardware_alarm_num) {
     hardware_alarm_set_callback(hardware_alarm_num, alarm_pool_alarm_callback);
     pool->lock = spin_lock_instance(next_striped_spin_lock_num());
     pool->hardware_alarm_num = (uint8_t) hardware_alarm_num;
+    pool->core_num = get_core_num();
     pools[hardware_alarm_num] = pool;
 }
 
@@ -286,6 +288,10 @@ uint alarm_pool_hardware_alarm_num(alarm_pool_t *pool) {
     return pool->hardware_alarm_num;
 }
 
+uint alarm_pool_core_num(alarm_pool_t *pool) {
+    return pool->core_num;
+}
+
 static void alarm_pool_dump_key(pheap_node_id_t id, void *user_data) {
     alarm_pool_t *pool = (alarm_pool_t *)user_data;
 #if PICO_ON_DEVICE
diff --git a/src/rp2_common/pico_stdio/include/pico/stdio.h b/src/rp2_common/pico_stdio/include/pico/stdio.h
index e44c01d05..87c245afe 100644
--- a/src/rp2_common/pico_stdio/include/pico/stdio.h
+++ b/src/rp2_common/pico_stdio/include/pico/stdio.h
@@ -52,9 +52,10 @@ typedef struct stdio_driver stdio_driver_t;
  * When stdio_usb is configured, this method can be optionally made to block, waiting for a connection
  * via the variables specified in \ref stdio_usb_init (i.e. \ref PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS)
  *
+ * \return true if at least one output was successfully initialized, false otherwise.
  * \see stdio_uart, stdio_usb, stdio_semihosting
  */
-void stdio_init_all(void);
+bool stdio_init_all(void);
 
 /*! \brief Initialize all of the present standard stdio types that are linked into the binary.
  * \ingroup pico_stdio
diff --git a/src/rp2_common/pico_stdio/stdio.c b/src/rp2_common/pico_stdio/stdio.c
index 52a1c0cc0..75e906298 100644
--- a/src/rp2_common/pico_stdio/stdio.c
+++ b/src/rp2_common/pico_stdio/stdio.c
@@ -267,20 +267,25 @@ int __printflike(1, 0) WRAPPER_FUNC(printf)(const char* format, ...)
     return ret;
 }
 
-void stdio_init_all(void) {
+bool stdio_init_all(void) {
     // todo add explicit custom, or registered although you can call stdio_enable_driver explicitly anyway
     // These are well known ones
+
+    bool rc = false;
 #if LIB_PICO_STDIO_UART
     stdio_uart_init();
+    rc = true;
 #endif
 
 #if LIB_PICO_STDIO_SEMIHOSTING
     stdio_semihosting_init();
+    rc = true;
 #endif
 
 #if LIB_PICO_STDIO_USB
-    stdio_usb_init();
+    rc |= stdio_usb_init();
 #endif
+    return rc;
 }
 
 int WRAPPER_FUNC(getchar)(void) {
diff --git a/src/rp2_common/pico_stdio_usb/stdio_usb.c b/src/rp2_common/pico_stdio_usb/stdio_usb.c
index cd2e2c93f..576626c31 100644
--- a/src/rp2_common/pico_stdio_usb/stdio_usb.c
+++ b/src/rp2_common/pico_stdio_usb/stdio_usb.c
@@ -25,6 +25,11 @@ static uint8_t stdio_usb_core_num;
 
 // when tinyusb_device is explicitly linked we do no background tud processing
 #if !LIB_TINYUSB_DEVICE
+// if this crit_sec is initialized, we are not in periodic timer mode, and must make sure
+// we don't either create multiple one shot timers, or miss creating one. this crit_sec
+// is used to protect the one_shot_timer_pending flag
+static critical_section_t one_shot_timer_crit_sec;
+static volatile bool one_shot_timer_pending;
 #ifdef PICO_STDIO_USB_LOW_PRIORITY_IRQ
 static_assert(PICO_STDIO_USB_LOW_PRIORITY_IRQ >= NUM_IRQS - NUM_USER_IRQS, "");
 #define low_priority_irq_num PICO_STDIO_USB_LOW_PRIORITY_IRQ
@@ -32,13 +37,45 @@ static_assert(PICO_STDIO_USB_LOW_PRIORITY_IRQ >= NUM_IRQS - NUM_USER_IRQS, "");
 static uint8_t low_priority_irq_num;
 #endif
 
+static int64_t timer_task(__unused alarm_id_t id, __unused void *user_data) {
+    int64_t repeat_time;
+    if (critical_section_is_initialized(&one_shot_timer_crit_sec)) {
+        critical_section_enter_blocking(&one_shot_timer_crit_sec);
+        one_shot_timer_pending = false;
+        critical_section_exit(&one_shot_timer_crit_sec);
+        repeat_time = 0; // don't repeat
+    } else {
+        repeat_time = PICO_STDIO_USB_TASK_INTERVAL_US;
+    }
+    irq_set_pending(low_priority_irq_num);
+    return repeat_time;
+}
+
 static void low_priority_worker_irq(void) {
-    // if the mutex is already owned, then we are in user code
-    // in this file which will do a tud_task itself, so we'll just do nothing
-    // until the next tick; we won't starve
     if (mutex_try_enter(&stdio_usb_mutex, NULL)) {
         tud_task();
         mutex_exit(&stdio_usb_mutex);
+    } else {
+        // if the mutex is already owned, then we are in non IRQ code in this file.
+        //
+        // it would seem simplest to just let that code call tud_task() at the end, however this
+        // code might run during the call to tud_task() and we might miss a necessary tud_task() call
+        //
+        // if we are using a periodic timer (crit_sec is not initialized in this case),
+        // then we are happy just to wait until the next tick, however when we are not using a periodic timer,
+        // we must kick off a one-shot timer to make sure the tud_task() DOES run (this method
+        // will be called again as a result, and will try the mutex_try_enter again, and if that fails
+        // create another one shot timer again, and so on).
+        if (critical_section_is_initialized(&one_shot_timer_crit_sec)) {
+            bool need_timer;
+            critical_section_enter_blocking(&one_shot_timer_crit_sec);
+            need_timer = !one_shot_timer_pending;
+            one_shot_timer_pending = true;
+            critical_section_exit(&one_shot_timer_crit_sec);
+            if (need_timer) {
+                add_alarm_in_us(PICO_STDIO_USB_TASK_INTERVAL_US, timer_task, NULL, true);
+            }
+        }
     }
 }
 
@@ -46,11 +83,6 @@ static void usb_irq(void) {
     irq_set_pending(low_priority_irq_num);
 }
 
-static int64_t timer_task(__unused alarm_id_t id, __unused void *user_data) {
-    assert(stdio_usb_core_num == get_core_num()); // if this fails, you have initialized stdio_usb on the wrong core
-    irq_set_pending(low_priority_irq_num);
-    return PICO_STDIO_USB_TASK_INTERVAL_US;
-}
 #endif
 
 static void stdio_usb_out_chars(const char *buf, int length) {
@@ -97,6 +129,9 @@ int stdio_usb_in_chars(char *buf, int length) {
     if (tud_cdc_connected() && tud_cdc_available()) {
         int count = (int) tud_cdc_read(buf, (uint32_t) length);
         rc =  count ? count : PICO_ERROR_NO_DATA;
+    } else {
+        // because our mutex use may starve out the background task, run tud_task here (we own the mutex)
+        tud_task();
     }
     mutex_exit(&stdio_usb_mutex);
     return rc;
@@ -111,6 +146,12 @@ stdio_driver_t stdio_usb = {
 };
 
 bool stdio_usb_init(void) {
+    if (get_core_num() != alarm_pool_core_num(alarm_pool_get_default())) {
+        // included an assertion here rather than just returning false, as this is likely
+        // a coding bug, rather than anything else.
+        assert(false);
+        return false;
+    }
 #ifndef NDEBUG
     stdio_usb_core_num = (uint8_t)get_core_num();
 #endif
@@ -139,8 +180,11 @@ bool stdio_usb_init(void) {
     if (irq_has_shared_handler(USBCTRL_IRQ)) {
         // we can use a shared handler to notice when there may be work to do
         irq_add_shared_handler(USBCTRL_IRQ, usb_irq, PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY);
+        critical_section_init_with_lock_num(&one_shot_timer_crit_sec, next_striped_spin_lock_num());
     } else {
-        rc = add_alarm_in_us(PICO_STDIO_USB_TASK_INTERVAL_US, timer_task, NULL, true);
+        rc = add_alarm_in_us(PICO_STDIO_USB_TASK_INTERVAL_US, timer_task, NULL, true) >= 0;
+        // we use initialization state of the one_shot_timer_critsec as a flag
+        memset(&one_shot_timer_crit_sec, 0, sizeof(one_shot_timer_crit_sec));
     }
 #endif
     if (rc) {

From a33a11ea1695f0ff8ee890140be629a763a0b218 Mon Sep 17 00:00:00 2001
From: Attila Wagner <attila.wagner.89@gmail.com>
Date: Wed, 10 Aug 2022 13:55:54 +0100
Subject: [PATCH 41/51] Call `cyw43_deinit()` from `cyw43_arch_deinit()` to
 release the DMA channels and power off the WLAN chip (#965)

---
 src/rp2_common/pico_cyw43_arch/cyw43_arch_freertos.c             | 1 +
 .../pico_cyw43_arch/cyw43_arch_threadsafe_background.c           | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/rp2_common/pico_cyw43_arch/cyw43_arch_freertos.c b/src/rp2_common/pico_cyw43_arch/cyw43_arch_freertos.c
index 2bfb39eaa..01d9baa0e 100644
--- a/src/rp2_common/pico_cyw43_arch/cyw43_arch_freertos.c
+++ b/src/rp2_common/pico_cyw43_arch/cyw43_arch_freertos.c
@@ -168,6 +168,7 @@ void cyw43_arch_deinit(void) {
     }
     gpio_set_irq_enabled(CYW43_PIN_WL_HOST_WAKE, GPIO_IRQ_LEVEL_HIGH, false);
     gpio_remove_raw_irq_handler(IO_IRQ_BANK0, gpio_irq_handler);
+    cyw43_deinit(&cyw43_state);
 }
 
 void cyw43_post_poll_hook(void) {
diff --git a/src/rp2_common/pico_cyw43_arch/cyw43_arch_threadsafe_background.c b/src/rp2_common/pico_cyw43_arch/cyw43_arch_threadsafe_background.c
index a3dde74b7..79ccfd701 100644
--- a/src/rp2_common/pico_cyw43_arch/cyw43_arch_threadsafe_background.c
+++ b/src/rp2_common/pico_cyw43_arch/cyw43_arch_threadsafe_background.c
@@ -211,6 +211,7 @@ void cyw43_arch_deinit(void) {
     gpio_set_irq_enabled(CYW43_PIN_WL_HOST_WAKE, GPIO_IRQ_LEVEL_HIGH, false);
     gpio_remove_raw_irq_handler(IO_IRQ_BANK0, gpio_irq_handler);
     low_prio_irq_deinit();
+    cyw43_deinit(&cyw43_state);
 }
 
 void cyw43_post_poll_hook(void) {

From 80cde7276d238feb6396381a1845166d30041402 Mon Sep 17 00:00:00 2001
From: "Mr. Green's Workshop"
 <76992231+MrGreensWorkshop@users.noreply.github.com>
Date: Wed, 10 Aug 2022 23:16:44 +0900
Subject: [PATCH 42/51] Enable/disable connection check made with DTR (#932)

* Enable/disable connection check made with DTR
this gives users the option to disable DTR check.

Co-authored-by: Graham Sanderson <graham.sanderson@gmail.com>
---
 .../pico_stdio_usb/include/pico/stdio_usb.h          |  5 +++++
 src/rp2_common/pico_stdio_usb/stdio_usb.c            | 12 +++++++++---
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb.h b/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb.h
index 8ac824447..565b6c328 100644
--- a/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb.h
+++ b/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb.h
@@ -97,6 +97,11 @@
 #define PICO_STDIO_USB_RESET_RESET_TO_FLASH_DELAY_MS 100
 #endif
 
+// PICO_CONFIG: PICO_STDIO_USB_CONNECTION_WITHOUT_DTR, Disable use of DTR for connection checking meaning connection is assumed to be valid, type=bool, default=0, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_CONNECTION_WITHOUT_DTR
+#define PICO_STDIO_USB_CONNECTION_WITHOUT_DTR 0
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/src/rp2_common/pico_stdio_usb/stdio_usb.c b/src/rp2_common/pico_stdio_usb/stdio_usb.c
index 576626c31..d7a649c32 100644
--- a/src/rp2_common/pico_stdio_usb/stdio_usb.c
+++ b/src/rp2_common/pico_stdio_usb/stdio_usb.c
@@ -92,7 +92,7 @@ static void stdio_usb_out_chars(const char *buf, int length) {
         if (owner == get_core_num()) return; // would deadlock otherwise
         mutex_enter_blocking(&stdio_usb_mutex);
     }
-    if (tud_cdc_connected()) {
+    if (stdio_usb_connected()) {
         for (int i = 0; i < length;) {
             int n = length - i;
             int avail = (int) tud_cdc_write_available();
@@ -106,7 +106,7 @@ static void stdio_usb_out_chars(const char *buf, int length) {
             } else {
                 tud_task();
                 tud_cdc_write_flush();
-                if (!tud_cdc_connected() ||
+                if (!stdio_usb_connected() ||
                     (!tud_cdc_write_available() && time_us_64() > last_avail_time + PICO_STDIO_USB_STDOUT_TIMEOUT_US)) {
                     break;
                 }
@@ -126,7 +126,7 @@ int stdio_usb_in_chars(char *buf, int length) {
         mutex_enter_blocking(&stdio_usb_mutex);
     }
     int rc = PICO_ERROR_NO_DATA;
-    if (tud_cdc_connected() && tud_cdc_available()) {
+    if (stdio_usb_connected() && tud_cdc_available()) {
         int count = (int) tud_cdc_read(buf, (uint32_t) length);
         rc =  count ? count : PICO_ERROR_NO_DATA;
     } else {
@@ -210,8 +210,14 @@ bool stdio_usb_init(void) {
 }
 
 bool stdio_usb_connected(void) {
+#if PICO_STDIO_USB_CONNECTION_WITHOUT_DTR
+    return tud_ready();
+#else
+    // this actually checks DTR
     return tud_cdc_connected();
+#endif
 }
+
 #else
 #warning stdio USB was configured along with user use of TinyUSB device mode, but CDC is not enabled
 bool stdio_usb_init(void) {

From 00780f0de92ae6e75c1a249f002ead9bdc329680 Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Wed, 17 Aug 2022 10:25:23 -0500
Subject: [PATCH 43/51] Make sure stack is 8 byte aligned in shared IRQ
 handlers (#971)

---
 src/rp2_common/hardware_irq/irq.c               | 10 +++++-----
 src/rp2_common/hardware_irq/irq_handler_chain.S |  6 ++++--
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/src/rp2_common/hardware_irq/irq.c b/src/rp2_common/hardware_irq/irq.c
index 251cdf7b7..40af5fea7 100644
--- a/src/rp2_common/hardware_irq/irq.c
+++ b/src/rp2_common/hardware_irq/irq.c
@@ -213,7 +213,7 @@ void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_prior
         struct irq_handler_chain_slot slot_data = {
                 .inst1 = 0xa100,                                                    // add r1, pc, #0
                 .inst2 = make_branch(&slot->inst2, irq_handler_chain_first_slot),   // b irq_handler_chain_first_slot
-                .inst3 = 0xbd00,                                                    // pop {pc}
+                .inst3 = 0xbd01,                                                    // pop {r0, pc}
                 .link = -1,
                 .priority = order_priority,
                 .handler = handler
@@ -237,7 +237,7 @@ void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_prior
                     .inst2 = 0x4780,                                                        // blx r0
                     .inst3 = prev_slot->link >= 0 ?
                             make_branch(&slot->inst3, resolve_branch(&prev_slot->inst3)) : // b next_slot
-                            0xbd00,                                                        // pop {pc}
+                            0xbd01,                                                        // pop {r0, pc}
                     .link = prev_slot->link,
                     .priority = order_priority,
                     .handler = handler
@@ -319,7 +319,7 @@ void irq_remove_handler(uint num, irq_handler_t handler) {
                     to_free_slot->link = next_slot->link;
                     to_free_slot->inst3 = next_slot->link >= 0 ?
                             make_branch(&to_free_slot->inst3, resolve_branch(&next_slot->inst3)) : // b mext_>slot->next_slot
-                            0xbd00;                                                                // pop {pc}
+                            0xbd01;                                                                // pop {r0, pc}
 
                     // add old next slot back to free list
                     next_slot->link = irq_hander_chain_free_slot_head;
@@ -331,7 +331,7 @@ void irq_remove_handler(uint num, irq_handler_t handler) {
                         if (prev_slot) {
                             // chain is not empty
                             prev_slot->link = -1;
-                            prev_slot->inst3 = 0xbd00; // pop {pc}
+                            prev_slot->inst3 = 0xbd01; // pop {r0, pc}
                         } else {
                             // chain is not empty
                             vtable_handler = __unhandled_user_irq;
@@ -400,7 +400,7 @@ void irq_add_tail_to_free_list(struct irq_handler_chain_slot *slot) {
         for(uint i=0;i<count_of(irq_handler_chain_slots);i++) {
             if (irq_handler_chain_slots[i].link == slot_index) {
                 irq_handler_chain_slots[i].link = -1;
-                irq_handler_chain_slots[i].inst3 = 0xbd00; // pop {pc}
+                irq_handler_chain_slots[i].inst3 = 0xbd01; // pop {r0, pc}
                 found = true;
                 break;
             }
diff --git a/src/rp2_common/hardware_irq/irq_handler_chain.S b/src/rp2_common/hardware_irq/irq_handler_chain.S
index ca1529287..bb65fb160 100644
--- a/src/rp2_common/hardware_irq/irq_handler_chain.S
+++ b/src/rp2_common/hardware_irq/irq_handler_chain.S
@@ -54,7 +54,9 @@ irq_handler_chain_slots:
 .endr
 
 irq_handler_chain_first_slot:
-    push {lr}         // Save EXC_RETURN token, so `pop {pc}` will return from interrupt
+    push {r0, lr}     // Save EXC_RETURN token, so `pop {r0, pc}` will return from interrupt
+                      // Note that r0 does not NEED to be saved, however we must maintain
+                      // an 8 byte stack alignment, and this is the cheapest way to do so
     ldr  r0, [r1, #4] // Get `handler` field of irq_handler_chain_slot
     adds r1, #1       // r1 points to `inst3` field of slot struct. Set Thumb bit on r1,
     mov  lr, r1       // and copy to lr, so `inst3` is executed on return from handler
@@ -65,7 +67,7 @@ irq_handler_chain_remove_tail:
     subs r0, #9       // so lr points to offset +8. Note also lr has its Thumb bit set!
     ldr  r1, =irq_add_tail_to_free_list
     blx  r1
-    pop  {pc}         // Top of stack is EXC_RETURN
+    pop  {r0, pc}     // Top of stack is EXC_RETURN
 
 
 #endif

From 830e867211c76044adfcafd3dfe6702d2eddbb00 Mon Sep 17 00:00:00 2001
From: NomiChirps <70026509+NomiChirps@users.noreply.github.com>
Date: Wed, 17 Aug 2022 12:37:50 -0700
Subject: [PATCH 44/51] Fix dma_irqn_acknowledge_channel (#977)

Also dma_channel_acknowledge_irq0 and dma_channel_acknowledge_irq1.
Using hw_set_bits acked every channel because INTS0/1 are WC registers.

Fixes #974.
---
 src/rp2_common/hardware_dma/include/hardware/dma.h | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/rp2_common/hardware_dma/include/hardware/dma.h b/src/rp2_common/hardware_dma/include/hardware/dma.h
index ec735640a..b1e956fc3 100644
--- a/src/rp2_common/hardware_dma/include/hardware/dma.h
+++ b/src/rp2_common/hardware_dma/include/hardware/dma.h
@@ -665,7 +665,7 @@ static inline bool dma_irqn_get_channel_status(uint irq_index, uint channel) {
  */
 static inline void dma_channel_acknowledge_irq0(uint channel) {
     check_dma_channel_param(channel);
-    hw_set_bits(&dma_hw->ints0, (1u << channel));
+    dma_hw->ints0 = 1u << channel;
 }
 
 /*! \brief  Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_1
@@ -675,7 +675,7 @@ static inline void dma_channel_acknowledge_irq0(uint channel) {
  */
 static inline void dma_channel_acknowledge_irq1(uint channel) {
     check_dma_channel_param(channel);
-    hw_set_bits(&dma_hw->ints1, (1u << channel));
+    dma_hw->ints1 = 1u << channel;
 }
 
 /*! \brief  Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_N
@@ -687,7 +687,10 @@ static inline void dma_channel_acknowledge_irq1(uint channel) {
 static inline void dma_irqn_acknowledge_channel(uint irq_index, uint channel) {
     invalid_params_if(DMA, irq_index > 1);
     check_dma_channel_param(channel);
-    hw_set_bits(irq_index ? &dma_hw->ints1 : &dma_hw->ints0, (1u << channel));
+    if (irq_index)
+        dma_hw->ints1 = 1u << channel;
+    else
+        dma_hw->ints0 = 1u << channel;
 }
 
 /*! \brief  Check if DMA channel is busy

From 0d872ea40933877ddf5820349ce155ef7fb7bfe6 Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Thu, 18 Aug 2022 07:51:38 -0500
Subject: [PATCH 45/51] Move to TinyUSB 0.14.0 (#937)

---
 lib/tinyusb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/tinyusb b/lib/tinyusb
index 4bfab30c0..b0b155c94 160000
--- a/lib/tinyusb
+++ b/lib/tinyusb
@@ -1 +1 @@
-Subproject commit 4bfab30c02279a0530e1a56f4a7c539f2d35a293
+Subproject commit b0b155c9491d9e8cfc3d40366f77accfd3302cec

From 89bce613aeb43a156de78a35daf3773a7b0a6007 Mon Sep 17 00:00:00 2001
From: David Thacher <davidethacher@gmail.com>
Date: Thu, 18 Aug 2022 09:14:40 -0400
Subject: [PATCH 46/51] Remove hw_set_bits from pio->irq (#978)

It is not known if this is required. This is done for consistency purposes. Related to #974
---
 src/rp2_common/hardware_pio/include/hardware/pio.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/rp2_common/hardware_pio/include/hardware/pio.h b/src/rp2_common/hardware_pio/include/hardware/pio.h
index e42c60fc2..87f27790c 100644
--- a/src/rp2_common/hardware_pio/include/hardware/pio.h
+++ b/src/rp2_common/hardware_pio/include/hardware/pio.h
@@ -818,7 +818,7 @@ static inline bool pio_interrupt_get(PIO pio, uint pio_interrupt_num) {
 static inline void pio_interrupt_clear(PIO pio, uint pio_interrupt_num) {
     check_pio_param(pio);
     invalid_params_if(PIO, pio_interrupt_num >= 8);
-    hw_set_bits(&pio->irq, (1u << pio_interrupt_num));
+    pio->irq = (1u << pio_interrupt_num);
 }
 
 /*! \brief Return the current program counter for a state machine

From 0041f4b7fd3d6d7c92594d866db6fee2360c776f Mon Sep 17 00:00:00 2001
From: Peter Harper <77111776+peterharperuk@users.noreply.github.com>
Date: Thu, 1 Sep 2022 20:10:06 +0100
Subject: [PATCH 47/51] set CYW43_WIFI_NVRAM_INCLUDE_FILE allowing user
 override

---
 src/rp2_common/pico_cyw43_arch/include/cyw43_configport.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/rp2_common/pico_cyw43_arch/include/cyw43_configport.h b/src/rp2_common/pico_cyw43_arch/include/cyw43_configport.h
index 7827c8115..68cc4b8c5 100644
--- a/src/rp2_common/pico_cyw43_arch/include/cyw43_configport.h
+++ b/src/rp2_common/pico_cyw43_arch/include/cyw43_configport.h
@@ -70,4 +70,8 @@
 #define CYW43_SPI_PIO 1
 #endif
 
+#ifndef CYW43_WIFI_NVRAM_INCLUDE_FILE
+#define CYW43_WIFI_NVRAM_INCLUDE_FILE "wifi_nvram_43439.h"
+#endif
+
 #endif
\ No newline at end of file

From 07e5caf341bdd79610290a21a6cdc153542d1781 Mon Sep 17 00:00:00 2001
From: Zachary Kohnen <me@dusterthefirst.com>
Date: Tue, 6 Sep 2022 17:59:48 +0200
Subject: [PATCH 48/51] Supress -Wunused-parameter when
 PICO_STDIO_ENABLE_CRLF_SUPPORT is unset (#998)

---
 src/rp2_common/pico_stdio/stdio.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/rp2_common/pico_stdio/stdio.c b/src/rp2_common/pico_stdio/stdio.c
index 75e906298..6f9405ea1 100644
--- a/src/rp2_common/pico_stdio/stdio.c
+++ b/src/rp2_common/pico_stdio/stdio.c
@@ -315,6 +315,10 @@ void stdio_set_translate_crlf(stdio_driver_t *driver, bool enabled) {
     }
     driver->crlf_enabled = enabled;
 #else
+    // Suppress -Wunused-parameter
+    (void)driver;
+    (void)enabled;
+    
     panic_unsupported();
 #endif
-}
+}
\ No newline at end of file

From 189d377be24988a2f5381506732d7e627196c4dd Mon Sep 17 00:00:00 2001
From: bruelltuete <jo@bruelltuete.com>
Date: Tue, 6 Sep 2022 17:00:51 +0100
Subject: [PATCH 49/51] Only include mutex header if necessary (#991)

---
 src/rp2_common/pico_stdio/stdio.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/rp2_common/pico_stdio/stdio.c b/src/rp2_common/pico_stdio/stdio.c
index 6f9405ea1..cce9de8db 100644
--- a/src/rp2_common/pico_stdio/stdio.c
+++ b/src/rp2_common/pico_stdio/stdio.c
@@ -9,13 +9,15 @@
 #include <stdarg.h>
 
 #include "pico.h"
-#include "pico/mutex.h"
 #if LIB_PICO_PRINTF_PICO
 #include "pico/printf.h"
 #endif
 #include "pico/stdio.h"
 #include "pico/stdio/driver.h"
 #include "pico/time.h"
+#if PICO_STDOUT_MUTEX
+#include "pico/mutex.h"
+#endif
 
 #if LIB_PICO_STDIO_UART
 #include "pico/stdio_uart.h"

From a4ec3c4848b1ab55958e29b8612329b2139ea71e Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Tue, 6 Sep 2022 23:02:45 +0700
Subject: [PATCH 50/51] fix wconversion warning (#981)

---
 src/common/pico_time/time.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/common/pico_time/time.c b/src/common/pico_time/time.c
index 2618e8e47..5ce704584 100644
--- a/src/common/pico_time/time.c
+++ b/src/common/pico_time/time.c
@@ -191,7 +191,7 @@ void alarm_pool_post_alloc_init(alarm_pool_t *pool, uint hardware_alarm_num) {
     hardware_alarm_set_callback(hardware_alarm_num, alarm_pool_alarm_callback);
     pool->lock = spin_lock_instance(next_striped_spin_lock_num());
     pool->hardware_alarm_num = (uint8_t) hardware_alarm_num;
-    pool->core_num = get_core_num();
+    pool->core_num = (uint8_t) get_core_num();
     pools[hardware_alarm_num] = pool;
 }
 

From 4e828980131e9af8049da3c585a8201a7f967cf3 Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Mon, 19 Sep 2022 18:00:49 +0200
Subject: [PATCH 51/51] Remove cyw43-driver and lwip submodules

---
 README.md        | 2 +-
 lib/cyw43-driver | 1 -
 lib/lwip         | 1 -
 3 files changed, 1 insertion(+), 3 deletions(-)
 delete mode 160000 lib/cyw43-driver
 delete mode 160000 lib/lwip

diff --git a/README.md b/README.md
index 22829739f..eeb6aff66 100644
--- a/README.md
+++ b/README.md
@@ -1 +1 @@
-# ATTENTION! THIS IS THE QMK FORK OF PICO SDK WHICH REMOVES TINYUSB AS A SUBMODULE. ALL USB FUNCTIONALITY IS HANDLED BY THE CHIBIOS USB STACK!
+# ATTENTION! THIS IS THE QMK FORK OF PICO SDK WHICH REMOVES TINYUSB, CYW43-DRIVER and LWIP SUBMODULES. ALL USB FUNCTIONALITY IS HANDLED BY THE CHIBIOS USB STACK!
diff --git a/lib/cyw43-driver b/lib/cyw43-driver
deleted file mode 160000
index 195dfcc10..000000000
--- a/lib/cyw43-driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 195dfcc10bb6f379e3dea45147590db2203d3c7b
diff --git a/lib/lwip b/lib/lwip
deleted file mode 160000
index 239918ccc..000000000
--- a/lib/lwip
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 239918ccc173cb2c2a62f41a40fd893f57faf1d6