From a1c42e6614bbec0921341f919f629d192f19870a Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Sun, 6 Nov 2016 17:56:48 +0000 Subject: [PATCH] [Hexagon] Round 2 of selection pattern simplifications Add pat frags for any-, sign-, and zero-extensions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286076 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonPatterns.td | 56 ++++++++++++++------------- 1 file changed, 29 insertions(+), 27 deletions(-) diff --git a/lib/Target/Hexagon/HexagonPatterns.td b/lib/Target/Hexagon/HexagonPatterns.td index b242c55316e2..232bb2bf15bd 100644 --- a/lib/Target/Hexagon/HexagonPatterns.td +++ b/lib/Target/Hexagon/HexagonPatterns.td @@ -359,6 +359,10 @@ def: T_MType_acc_pat3 ; def: T_MType_acc_pat3 ; def: T_MType_acc_pat3 ; +def Aext64: PatFrag<(ops node:$Rs), (i64 (anyext node:$Rs))>; +def Sext64: PatFrag<(ops node:$Rs), (i64 (sext node:$Rs))>; +def Zext64: PatFrag<(ops node:$Rs), (i64 (zext node:$Rs))>; + // Return true if for a 32 to 64-bit sign-extended load. def Sext64Ld : PatLeaf<(i64 DoubleRegs:$src1), [{ LoadSDNode *LD = dyn_cast(N); @@ -368,12 +372,10 @@ def Sext64Ld : PatLeaf<(i64 DoubleRegs:$src1), [{ LD->getMemoryVT().getScalarType() == MVT::i32; }]>; -def: Pat<(i64 (mul (i64 (anyext I32:$src1)), - (i64 (anyext I32:$src2)))), +def: Pat<(i64 (mul (Aext64 I32:$src1), (Aext64 I32:$src2))), (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>; -def: Pat<(i64 (mul (i64 (sext I32:$src1)), - (i64 (sext I32:$src2)))), +def: Pat<(i64 (mul (Sext64 I32:$src1), (Sext64 I32:$src2))), (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>; def: Pat<(i64 (mul Sext64Ld:$src1, Sext64Ld:$src2)), @@ -382,34 +384,34 @@ def: Pat<(i64 (mul Sext64Ld:$src1, Sext64Ld:$src2)), // Multiply and accumulate, use full result. // Rxx[+-]=mpy(Rs,Rt) -def: Pat<(i64 (add (i64 DoubleRegs:$src1), - (mul (i64 (sext (i32 IntRegs:$src2))), - (i64 (sext (i32 IntRegs:$src3)))))), +def: Pat<(i64 (add I64:$src1, + (mul (Sext64 I32:$src2), + (Sext64 I32:$src3)))), (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; -def: Pat<(i64 (sub (i64 DoubleRegs:$src1), - (mul (i64 (sext (i32 IntRegs:$src2))), - (i64 (sext (i32 IntRegs:$src3)))))), +def: Pat<(i64 (sub I64:$src1, + (mul (Sext64 I32:$src2), + (Sext64 I32:$src3)))), (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; -def: Pat<(i64 (add (i64 DoubleRegs:$src1), - (mul (i64 (anyext (i32 IntRegs:$src2))), - (i64 (anyext (i32 IntRegs:$src3)))))), +def: Pat<(i64 (add I64:$src1, + (mul (Aext64 I32:$src2), + (Aext64 I32:$src3)))), (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; -def: Pat<(i64 (add (i64 DoubleRegs:$src1), - (mul (i64 (zext (i32 IntRegs:$src2))), - (i64 (zext (i32 IntRegs:$src3)))))), +def: Pat<(i64 (add I64:$src1, + (mul (Zext64 I32:$src2), + (Zext64 I32:$src3)))), (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; -def: Pat<(i64 (sub (i64 DoubleRegs:$src1), - (mul (i64 (anyext (i32 IntRegs:$src2))), - (i64 (anyext (i32 IntRegs:$src3)))))), +def: Pat<(i64 (sub I64:$src1, + (mul (Aext64 I32:$src2), + (Aext64 I32:$src3)))), (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; -def: Pat<(i64 (sub (i64 DoubleRegs:$src1), - (mul (i64 (zext (i32 IntRegs:$src2))), - (i64 (zext (i32 IntRegs:$src3)))))), +def: Pat<(i64 (sub I64:$src1, + (mul (Zext64 I32:$src2), + (Zext64 I32:$src3)))), (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; class Storepi_pat; def: Storexm_simple_pat; def: Storexm_simple_pat; -def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>; +def: Pat <(Sext64 I32:$src), (A2_sxtw I32:$src)>; def: Pat<(i32 (select (i1 (setlt I32:$src, 0)), (i32 (sub 0, I32:$src)), @@ -1100,7 +1102,7 @@ multiclass MinMax_pats_p { defm: T_MinMax_pats; } -def: Pat<(add (i64 (sext I32:$Rs)), I64:$Rt), +def: Pat<(add (Sext64 I32:$Rs), I64:$Rt), (A2_addsp IntRegs:$Rs, DoubleRegs:$Rt)>; let AddedComplexity = 200 in { @@ -1244,7 +1246,7 @@ defm: Loadxm_pat; defm: Loadxm_pat; // Map Rdd = anyext(Rs) -> Rdd = combine(#0, Rs). -def: Pat<(i64 (anyext I32:$src1)), (ToZext64 IntRegs:$src1)>; +def: Pat<(Aext64 I32:$src1), (ToZext64 IntRegs:$src1)>; multiclass T_LoadAbsReg_Pat { def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2_0ImmPred:$src2), @@ -1323,7 +1325,7 @@ def: Pat<(i64 (zext I1:$src1)), (ToZext64 (C2_muxii PredRegs:$src1, 1, 0))>; // zext i32->i64 -def: Pat<(i64 (zext I32:$src1)), +def: Pat<(Zext64 I32:$src1), (ToZext64 IntRegs:$src1)>; let AddedComplexity = 40 in @@ -2183,7 +2185,7 @@ def: Pat<(or (or (or (shl (i64 (zext (i32 (and I32:$b, (i32 65535))))), (i64 (zext (i32 (and I32:$a, (i32 65535)))))), (shl (i64 (anyext (i32 (and I32:$c, (i32 65535))))), (i32 32))), - (shl (i64 (anyext I32:$d)), (i32 48))), + (shl (Aext64 I32:$d), (i32 48))), (Insert4 IntRegs:$a, IntRegs:$b, IntRegs:$c, IntRegs:$d)>; // We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH