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Commits on Jan 20, 2022

• Substitute llvm_asm!(deprecated) with asm! (#5)

  wyfcyx

  authored
  11d43cf

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Commits on May 24, 2021

• Fix several page number bugs. (#4)

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  gjz010

  authored
  b6c469f

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Commits on May 22, 2021

• remove recursive page table

  wangrunji0408

  committed
  94a7329

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• remove 'hypervisor' feature and enable by default

  wangrunji0408

  committed
  d1f968e

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• Merge pull request #3 from rcore-riscv-hypervisor-dev/hypervisorext

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  wangrunji0408

  authored
  4e58457

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Commits on May 10, 2021

• bugfix in asm

  gjz010

  committed
  3f5efb1

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Commits on May 4, 2021

• Registers fixup.

  gjz010

  committed
  180c1f4

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Commits on Apr 25, 2021

• rustfmt

  gjz010

  committed
  74ee9c1

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• Removed more platform-dependent parts.

  gjz010

  committed
  d8acfbc

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• Merge branch 'master' of https://github.com/rcore-os/riscv into hypervisorext

  gjz010

  committed
  803700f

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• Refactor crate so that it looks more like official riscv crate.

  gjz010

  committed
  ed1109d

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Commits on Apr 2, 2021

• fix page table update flags

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  wangrunji0408

  committed
  0074cbc

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Commits on Mar 8, 2021

• Run cargo fmt.

  gjz010

  committed
  50b5fb4

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• Merge branch 'master' of https://github.com/rcore-os/riscv into hypervisorext

  gjz010

  committed
  89475d5

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• Run cargo fmt.

  gjz010

  committed
  922f448

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• Unifying build process.

  gjz010

  committed
  2fd5f1b

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• Merge branch 'merge_ext' into hypervisorext

  gjz010

  committed
  684ef1d

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• Moving H-extension into main riscv repository.

  gjz010

  committed
  6cb0df3

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• More flushing methods.

  gjz010

  committed
  7860e6d

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• More generic.

  gjz010

  committed
  ec41f2d

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• asm.S using global_asm inline assembly.

  gjz010

  committed
  681aef8

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• PhysAddrs and VirtAddrs redefined, with PhysAddr and VirtAddr as fallbacks.

  gjz010

  committed
  828a54e

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Commits on Mar 7, 2021

• CSR registers.

  gjz010

  committed
  eee747f

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Commits on Mar 6, 2021

• initial commit

  gjz010

  committed
  88f03d4

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Commits on Mar 4, 2021

• Migrating PhysAddr to u64 to support Sv32. PageTableX4 added for GPA support.

  gjz010

  committed
  5b88df3

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Commits on Jun 26, 2020

• Merge remote-tracking branch 'upstream/staging'

  jiegec

  committed
  21e32ee

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Commits on Jun 25, 2020

• Merge rust-embedded#52

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  bors[bot]

  and

  luojia65

  authored
  6392fa9

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• Use cargo fmt

  luojia65

  committed
  7309236

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• Uppercase doc comments for medeleg

  luojia65

  committed
  b144dd1

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• medeleg; small doc fix

  luojia65

  committed
  db4a22c

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Commits on Jun 20, 2020

• Merge rust-embedded#51

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  bors[bot]

  and

  Disasm

  authored
  4d16f14

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• Fix {S,U}tvec::trap_mode() functions to match Mtvec::trap_mode()

  Disasm

  committed
  f844c17

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• Merge rust-embedded#50

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  bors[bot]

  and

  Disasm

  authored
  3b8b0ad

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• Fix CI

  Disasm

  committed
  01148aa

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• Release v0.6.0

  Disasm

  committed
  b395169

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