The purpose of this changelog is to give a good overview of the changes in xpcc. It is an editorialized version of the git history, with features, PRs and fixes chosen for their importance to xpcc users as judged by the maintainer. This means that not every small commit makes it in here.
Changelog format
The release summaries are formatted as:
Breaking changes: [list]
Major features: [list]
Fixes: [list]
Known bugs: [list]
New development board targets: [list]
New device drivers: [list]
Contributors: [list]PR #[GitHub] -> [release tag].
With a more detailed changelog below with this format:
[detailed summary]
PR #[GitHub] -> [sha1] (with [level] impact (on [scope])).
Tested in hardware by [contributor].
Note that -> [sha1]
means "all changes up to and including this commit" which
needs to be interpreted in the context of the git history.
This usually corresponds to the changes in the Pull Request on GitHub though.
This changelog also labels the changes with an impact and usually also scopes them to the relevant subset of xpcc code or targets. This describes the anticipated impact of these changes on users of xpcc and has four levels:
- No impact mentioned: No influence. Adds new features and does not touch existing code.
- Low impact: No expected influence. Modifies xpcc in a backwards compatible way.
- Medium impact: Likely influence. Modifies xpcc in a non-backwards compatible way.
- High impact: Definite influence. Breaks the API within the scope.
High impact changes are explicitly called out in the release notes for you to pay attention to. Medium impact changes are also worth looking at.
This release covers everything from the 2018q1 release on 2018-04-05 and has been tested with avr-gcc v7.3.0 and arm-none-eabi-gcc 2018q2 from Arm.
With this release xpcc is marked as deprecated. Please port your application to its successor library modm using this guide. xpcc's repository will be archived after the 2018q4 release.
Breaking changes:
- No breaking changes.
Major features:
- Shared USART IRQ implementation for STM32F0/L0, fixes #88.
- Generic constexpr CAN bit timing calculations
Major fixes:
- Force UTF-8 encoding on Jinja templates, fixes #345.
- Fix missing ASCR register for STM32L4 GPIO.
- Correct formatting of float NaN and +-Inf values.
- Fix
SoftwareSpiMaster::acquire()
function.
Known bugs:
- GPIO
connect
on STM32F1 is still broken. See #178 for discussion. The API from MODM will not be backported to xpcc however. - STM32F107 does not compile due to the HAL trying to remap USB. See #268.
- SCons build system emits multiple non-critical warnings. See #286.
- avr-gcc 7 complains about dynamic initialization put into program memory area. See #314.
New development board targets:
- Nucleo-L432KC board as
nucleo_l432kc
. - Black Pill board as
stm32f103c8t6_black_pill
.
New device drivers:
- No new device drivers.
Many thanks to all our contributors: A special shoutout to first timers (🎉🎊):
- Christopher Durand (@chris-durand)
- Lucas Mösch (@lmoesch) 🎉🎊
- Nick Sarten (@genbattle)
- Niklas Hauser (@salkinium)
- Raphael Lehmann (@rleh)
- Sascha Schade (@strongly-typed)
Detailed changelog
PR #360 -> a1b5a1b.
Tested in hardware by @rleh.
PR #359 -> f22ba4e.
Tested in hardware by @rleh.
PR #358 -> ef2badd.
Tested in hardware by @strongly-typed.
PR #356 -> 871d2c0.
Tested in hardware by @rleh.
PR #353 -> 7a1e75a.
Tested in hardware by @chris-durand.
PR #355 -> 32dd08d.
Tested in hardware by @genbattle.
PR #351 -> 9fd0155 with medium impact on STM32F0/L0 targets.
Tested in hardware by @lmoesch.
PR #352 -> 6dff64d with low impact on STM32L4 targets.
Tested by @chris-durand.
PR #349 -> f83de4f with low impact on Windows targets.
Tested by @lmoesch.
This release covers everything from the 2017q4 release on 2018-01-07 and has been tested with avr-gcc v7.2.0 and arm-none-eabi-gcc 2017q4 from Arm.
Breaking changes:
- No breaking changes.
Major features:
- ADC implementation for STM32F0
- Block device interface and implementations
- CMake wrapper generator
- STM32L4 PLL configuration
Major fixes:
- Better Python 2/3 compatibility
- Fix HD44780 timing
- Fix AMSYS5915 sensor readings computation
Known bugs:
- xpcc may generate separate IRQ handlers for shared interrupts. See #88.
- GPIO
connect
on STM32F1 is still broken. See #178 for discussion. The API from MODM will not be backported to xpcc however. - STM32F107 does not compile due to the HAL trying to remap USB. See #268.
- SCons build system emits multiple non-critical warnings. See #286.
- avr-gcc 7 complains about dynamic initialization put into program memory area. See #314.
- Template encoding issues on Windows. See #345.
New development board targets:
- STM32F030F4P6 demo board as
stm32f030f4p6_demo_board
New device drivers:
- SPI Flash SST block device
- Memory block device
- File block device (hosted)
- Mirrored block device
Many thanks to all our contributors:
- Álan Crístoffer (@acristoffers)
- Antal Szabó (@Sh4rK)
- Christopher Durand (@chris-durand)
- Niklas Hauser (@salkinium)
- Raphael Lehmann (@rleh)
Detailed changelog
PR #346 -> 270d578 with medium-impact on STM32L4 targets.
Tested in hardware by @chris-durand.
Basic support for generating CMake projects files.
PR #341 -> 00ad2da.
Tested in hardware by @rleh.
PR #340 -> 95233ba with low-impact on STM32 targets.
Tested in hardware by @chris-durand.
PR #339 -> 4656fd4 with low-impact on AMSYS5915 driver.
Tested in hardware by @chris-durand.
PR #336 -> 0cedee1.
Tested in hardware by @Sh4rK.
Drivers to store data in a SPI SST flash xpcc::BdSpiFlash
, to store data in a
file (on hosted) xpcc::BdFile
and to store data in RAM (for testing purposes)
xpcc::BdHeap
are included.
Additionally, xpcc::BdMirror
is a virtual block device that behaves like
RAID1 devices.
PR #328 -> a945513.
Tested in hardware by @rleh.
PR #327 -> aad8d40 with low impact on STM32F0 targets.
Tested in hardware by @acristoffers.
This release covers everything from the 2017q3 release on 2017-10-01 and has been tested with avr-gcc v5.4.0 from Atmel and arm-none-eabi-gcc 2017q4 from Arm.
Breaking changes:
- No breaking changes.
Major features:
- SCons 3 and Python 3 support for built tools
- All targets build with C++14 by default
- Rosserial support
- LPC support (revival)
Major fixes:
- Fix the I2C driver on STM32L0/L4 for writes/reads > 255 bytes.
- Fix matrix multiplication and LU decomposition
- Fix
GpioPort
setOutput()/setInput()/configure() on STM32 - Fix Hd44780 initialization for 4-bit bus
- Fix GCC7-specific compile errors and warnings
Known bugs:
- xpcc may generate separate IRQ handlers for shared interrupts. See #88.
- GPIO
connect
on STM32F1 is still broken. See #178 for discussion. The API from MODM will not be backported to xpcc however. - STM32F107 does not compile due to the HAL trying to remap USB. See #268.
- SCons build system emits multiple non-critical warnings. See #286.
- avr-gcc 7 complains about dynamic initialization put into program memory area. See #314.
New development board targets:
- No new development board targets
New device drivers:
- No new device drivers
Many thanks to all our contributors. A special shoutout to first timers (🎉🎊):
- Álan Crístoffer (@acristoffers) 🎉🎊
- Andre Gilerson (@AndreGilerson) 🎉🎊
- Carl Treudler (@cajt)
- Christopher Durand (@chris-durand)
- Marten Junga (@Maju-Ketchup)
- Michael Thies (@mhthies)
- Niklas Hauser (@salkinium)
- Raphael Lehmann (@rleh)
- Sascha Schade (@strongly-typed)
Detailed changelog
Adds missing bitshift to write the correct nibble to enable 4-bit mode.
PR #326 -> 42837c7 with low impact on HD44780 driver.
Tested in hardware by @acristoffers.
Fixes wrong offset of a port mask used to configure output, input and pullups.
PR ? -> 6328b4a with low impact on STM32 targets.
Tested in hardware by @salkinium.
PR #324 -> 857e514 with medium impact on STM32 targets.
Tested in hardware by @salkinium.
Replaces the hosted implementation of our RTOS interface with the C++ stdlib to reduce our dependence on boost for threading.
PR #322 -> 5ef8009 with low impact on hosted targets.
SCons 3.0 features support for both Python 3.5+ and Python 2.7. These changes make all build and tool scripts compatible with both versions and adapt the CI systems too.
PR #297 -> 3b47fa5 with low impact on all build tools.
This is possible since Atmel's offical avr-gcc is now >= v5.4.0.
PR #320 -> 68e73b3 with low impact on all targets.
Matrix height and width parameters were switched.
PR #318 -> c4ed672 with medium impact on matrix math.
Tested in hardware by @Maju-Ketchup.
Only the lower 32 bits of an uint64_t were shown in iostream.
PR #315 -> 2c898ae with medium impact on printing 64-bit numbers.
Tested in hardware by @Maju-Ketchup.
Allows using xpcc for embedded sensor aquisition and interacting with a ROS robot across a serial link via ROS messages.
PR #306 -> 78c3ae2.
Tested in hardware by @strongly-typed.
"out of curiosity"
PR #305 -> 48d60e2 with medium impact on LPC targets.
Tested in hardware by @strongly-typed.
PR #301 -> 6aee411 with medium impact on negative LTC298x data.
Tested in hardware by @rleh.
Correctly generates restart condition on writes > 255 bytes.
PR #299 -> 3d9d80f with low impact on STM32L0/L4 targets.
Tested in hardware by @strongly-typed.
This release covers everything from the 2017q2 release on 2017-07-02 and has been tested with avr-gcc v5.4.0 from Atmel and arm-none-eabi-gcc 2017q2 from Arm. Note, that Arm did not release 6-2017-q3-update for their toolchain this quarter.
Breaking changes:
- MCP2515 revival adds new
initialize
API
Major features:
- No major features
Major fixes:
- Fix pin remap access (MAPR2 register) for STM32F1 XL Density series
- Fix moving average for negative averages
- Fix printf format string type violations
Known bugs:
- xpcc may generate separate IRQ handlers for shared interrupts. See #88.
- GPIO
connect
on STM32F1 is still broken. See #178 for discussion. The API from MODM will not be backported to xpcc however. - STM32L0/L4 hardware I2C driver has limitations on restart behaviors. See #255.
- STM32F107 does not compile due to the HAL trying to remap USB. See #268.
- SCons build system emits multiple non-critical warnings. See #286.
- SCons 3.0 was released, however, our build system is not fully compatible. See #293.
New development board targets:
- OLIMEXINO-STM32 as
olimexino_stm32
- STM32F051R-DISCO as
stm32f0_discovery
New device drivers:
- AD79x8
- LTC298x
- AMSYS5915
- MCP2515 (revived)
Many thanks to all our contributors. A special shoutout to first timers (🎉🎊):
- Carl Treudler (@cajt) 🎉🎊
- Christopher Durand (@chris-durand)
- Daniel Krebs (@daniel-k)
- Marten Junga (@Maju-Ketchup) 🎉🎊
- Michael Thies (@mhthies)
- Niklas Hauser (@salkinium)
- Raphael Lehmann (@rleh)
- Sascha Schade (@strongly-typed)
Detailed changelog
PR #295 -> e1f056a with medium impact on STM32 targets.
Tested in hardware by @salkinium.
PR #288 -> 9d6620d.
Tested in hardware by @cajt.
PR #284 -> 51491ad.
Tested in hardware by @strongly-typed.
Tested in hardware with 8 MHz external crystal for 10, 20, 50, 100, 125, 250, 500 and 1000 kBps with STM32 bxCAN and oscilloscope with protocol decoder.
PR #278 -> b77294e with high impact on MCP2515 driver users.
Tested in hardware by @strongly-typed.
Since template parameter N is defined as std::size_t
which is unsigned,
the result of the average calculation will be implicitly casted and
therefore negative averages gave wrong results.
PR #272 -> e14ba68 with medium impact on filter algorithms.
PR #275 -> fc59fc0.
Tested in hardware by @rleh.
PR #273 -> a27ca5d.
Tested in hardware by @rleh.
PR #274 -> 680c92a.
Tested in hardware by @chris-durand.
PR #270 -> 8cc5c78 with low impact.
Fix pin remap access (MAPR2 register) for STM32F1 XL Density series
PR #269 -> 06b5af9 with medium impact on STM32F1 targets.
Tested in hardware by @strongly-typed.
The XPCC (the protocol) tools now work with both Python2 and Python3.
PR #261 -> fc2f33b with low impact.
Now the compiler checks the format string for any type violations.
This release covers everything from the 2017q1 release on 2017-04-05 and has been tested with avr-gcc v5.4.0 from Atmel and arm-none-eabi-gcc 2017q2 from ARM.
Breaking changes:
- No breaking changes
Major features:
- STM32L4 target support and drivers
- Improve assert implementation and make use of them
Major fixes:
- Fix issues and warnings in release tests
- Fix wrong
ns_per_loop
rounding in board definitions
Known bugs:
- xpcc may generate separate IRQ handlers for shared interrupts. See #88.
- GPIO
connect
on STM32F1 is still broken. See #178 for discussion. The API from MODM will not be backported to xpcc however. - STM32L0/L4 hardware I2C driver has limitations on restart behaviors. See #255.
New development board targets:
- NUCLEO-L476RG as
nucleo_l476rg
- STM32L476G-DISCO as
stm32l476_discovery
New device drivers:
- DS1302
- TCS3472X
Many thanks to all our contributors. A special shoutout to first timers (🎉🎊):
- Arjun Sarin 🎉🎊
- Michael Thies (@mhthies)
- Niklas Hauser (@salkinium)
- Sascha Schade (@strongly-typed)
Detailed changelog
PR #254 -> f2ac1a0.
Tested in hardware by @strongly-typed.
PR #249 -> 29c8905.
Tested in hardware by @strongly-typed.
PR #248 -> 51159ff.
Tested in hardware by @strongly-typed.
PR #251 -> 40da657.
Tested in hardware by @strongly-typed.
- Make header C-compatible so asserts can be called from C.
- Specialize
assert_fail
function for context value. - Return condition from
xpcc_assert
for error handling. - Remove
exit()
calls from implementation. - Add assertions to core.
- Update F469-DISCO assert example.
PR #247 -> 3992534 with low impact.
Tested in hardware by @salkinium.
- Updates the DFG and SCons for STM32L4 family.
- Fixes AF issues with TimerN BreakIn signal.
- Adds ports of drivers for STM32L4 family.
- Adds BSPs for STM32L476 Nucleo and Discovery.
- Adds examples for STM32L476 Nucleo and Discovery.
PR #240 -> e9591d5 with medium impact on STM32 targets.
Tested in hardware by @strongly-typed.
UART does not have LIN or Smartcard mode.
As this is our first official release it covers the last 12 months of development since 2016-04-01.
Breaking changes:
- Fix implicit conversion of Flags
- Refactor
buffer
todisplay_buffer
inBufferedGraphicDisplay
- Fix spelling of
SpiMaster::acquire
- Namespace architecture/util.hpp macros
stm32f7_discovery
renamed tostm32f746g_discovery
Major features:
- Runtime error model using assertion handlers
- Memory traits to heap regions and allocators
- TLSF allocator
- Link against newlib-nosys and newlib-nano
- Unified interrupt declaration conventions
- Black Magic Probe programming support
- ARM Cortex-M7 with double precision FPU
- ZeroMQ as transport layer for XPCC
- Update STM32 header and device files
- Namespace architecture/util.hpp macros
- Coding conventions
- Porting guide
Major fixes:
- Fix implicit conversion of Flags
- Fix I2C master reception of 2B transfers
- Fix spelling of
SpiMaster::acquire
Known bugs:
- xpcc may generate separate IRQ handlers for shared interrupts. See #88.
- GPIO
connect
on STM32F1 is broken. They can be remapped only in groups, however, the API allows invalid remapping. This cannot be fixed without introducing a new API for that. See #178 for discussion. A solution has been tested for modm, but isn't ready for xpcc.
New development board targets:
- NUCLEO-F031K6 as
nucleo_f031k6
- NUCLEO-F303K8 as
nucleo_f303k8
- NUCLEO-F401RE as
nucleo_f401re
- NUCLEO-F411RE as
nucleo_f411re
- NUCLEO-F429ZI as
nucleo_f429zi
- STM32F769I-DISCO as
stm32f769i_discovery
- STM32F469I-DISCO as
stm32f469_discovery
- STM32F103 board "Blue Pill" as
stm32f103c8t6_blue_pill
New device drivers:
- VL53L0X
- BME280
- ADNS9800
- FT6x06
Many thanks to all our contributors. A special shoutout to first timers (🎉🎊):
- Antal Szabó (@Sh4rK)
- Christopher Durand (@chris-durand) 🎉🎊
- Daniel Krebs (@daniel-k)
- Fabian Greif (@dergraaf)
- Georgi Grinshpun (@georgi-g)
- Julia Gutheil 🎉🎊
- Kevin Läufer (@ekiwi)
- Michael Thies (@mhthies) 🎉🎊
- Nick Sarten (@genbattle) 🎉🎊
- Niklas Hauser (@salkinium)
- Raphael Lehmann (@rleh) 🎉🎊
- Sascha Schade (@strongly-typed)
- Tarik TIRE (@7Kronos) 🎉🎊
- Tomasz Chyrowicz (@tomchy) 🎉🎊
Detailed changelog
Adds get()
, rget()
, []
operator and appendOverwrite()
,
prependOverwrite()
to BoundedDeque
to access elements by id, e.g.
to do a binary search on ordered elements in the deque and to use the
BoundedDeque as a ring buffer.
Adds --specs=nosys.specs
to linker flags.
PR #235 -> 0e7e57f with low impact on ARM Cortex-M targets.
Tested in hardware by @salkinium.
This is some beautiful driver code.
PR #234 -> 553dceb.
Tested in hardware by @chris-durand.
PR #231 -> f472f7f.
Tested in hardware by @strongly-typed.
Conversion of Flags to an associated FlagsGroup
will now work
correctly even when multiple enum constants or flag variables are
combined with logical operators.
The bool conversion of flags classes is implemented in terms of
explicit operator bool()
to fix issues with function overloading
on Flags parameters.
The explicit operator will only allow implicit casts where contextual conversion takes place, which is more restrictive than the previous implementation. It will occur in the following contexts:
- conditions of if, while, for, do-while statements
- logical operators (&&, ||)
- negation (operator !)
- static_assert
This may break user code that requires implicit bool conversions on other occasions, for instance in return statements.
PR #230 -> fcf27a1 with high impact due to breaking API change.
This prevents confusion over which buffer
to use when also inheriting from an
I2cTransaction
class.
PR #194 -> e1efaf4 with high impact on display drivers due to breaking API change.
They've temporarily been lost.
PR #221 -> f780c2a.
Tested in hardware by @genbattle.
This replaces the STM32 device headers in ext/st/ with a git subtree of modm-io/cmsis-header-stm32 and updates the DFG to work for STM32L devices and adds all available device files.
PR #226 -> da784bd with medium impact on STM32 targets.
Tested in hardware by @salkinium.
This fixes several issues in the ZeroMQ backend.
PR #194 -> a8a2322 with low impact.
In the progress of adding raw Ethernet frames as a backend for XPCC communication, each container requires a unique id.
When using CAN as a backend filtering is done by component id. Normally, each CAN controller has enough filters to accommodate up to ten components per container. E.g. STM32F4 has 14 CAN filters.
When moving to Ethernet, the Ethernet MAC controller only has two or six filters which may be not enough. The filters are more difficult to configure.
The fifth byte of the MAC address will be used for the container Id and the sixth byte for the component Id. MAC filtering then can be easily implemented by filtering for the first five bytes of the MAC address.
There is no overhead for CAN communication as container Id is omitted.
PR #204 -> 5f5934a with low impact.
PR #202 -> dd3639b with low impact.
Tested in hardware by @7Kronos.
Adds macros for a unified interrupt declaration across all platforms and regardless of being declared in C or C++ source code. This allows us to change the interrupt invocation mechanism in the future without modifying the source code.
In total four macros are added:
XPCC_ISR(vector, attributes...)
for declaring a static ISR with attributes (e.g.xpcc_fastcode
).XPCC_ISR_NAME(vector)
for getting the platform specific ISR name.XPCC_ISR_DECL(vector)
for forward declarations of ISRs.XPCC_ISR_CALL(vector)
for calling ISRs manually from code.
XPCC_ISR_NAME(vector)
is backwards compatible, mapping to
{vector}_vect
on AVR and {vector}_IRQHandler
on ARM Cortex-M.
Consequently, the vector name is now used without _vect
or
_IRQHandler
suffixes and all occurrences have been renamed.
PR #185 -> 13904f8 with low impact.
This adds a mechanism for asserting runtime conditions on all platforms. The application can specify failure handlers that get called on assertion failure and can specify abandonment behavior depending on the failure. The abandonment handler can also be overwritten to provide application specific behavior, like blinking an LED or logging the failure.
For details see: http://blog.salkinium.com/xpccs-error-model
PR #185 -> 13904f8 with low impact.
Tested in hardware by @salkinium.
The optimization level can be set in project.cfg
as
build.optimization=level
and overwritten using the command line
argument optimization=level
.
PR #195 -> 5e547ab.
Tested in hardware by @strongly-typed.
This feature adds a ZeroMQ implementation of the XPCC backend as a replacement for TIPC on hosted targets and examples to show this new functionality.
PR #176 -> a00d3cc.
Tested in hardware by @strongly-typed.
PR #194 -> b21f502.
Tested in hardware by @strongly-typed.
Adds a 'naming-schema' and 'invalid-device' tag to the device files to allow to enumerate all valid device names from the device files alone. Removes the size_id attribute for AVRs because it is redundant with the name and not used by the AVR DFG merger. Uses local imports in the Python code and therefore removes the need to update the python path in every file.
PR #189 -> d949fee with low impact.
Deduplication by using Jinja2 macros to deduplicate the linker script formatting followed by clean up of unused linker sections.
PR #188 -> a379e61 with low impact on ARM Cortex-M targets.
Tested in hardware by @salkinium.
Adds --specs=nano.specs
to linker flags.
This saves up to 2kB of static data and ~1.5kB of code.
PR #187 -> cb0a11e with medium impact on ARM Cortex-M targets.
Tested in hardware by @salkinium.
This change updates the device file generator (DFG) to generate the patches we added to the device files manually now automatically. Any drivers that needed minor changes due to this were updated.
PR #183 -> 08784cd with low impact.
The xpcc/architecture/util.hpp
macros have been renamed and
properly documented.
A new header xpcc/architecture/legacy_macros.hpp
contains backwards
compatible mappings for application code. All occurrences of the non-
namespaced macros in xpcc have been replaced. The backwards-compatible
mapping can be disabled by declaring the XPCC_DISABLE_LEGACY_MACROS
macro to the compiler.
- ALWAYS_INLINE -> xpcc_always_inline
- ATTRIBUTE_UNUSED -> xpcc_unused
- ATTRIBUTE_WEAK -> xpcc_weak
- ATTRIBUTE_ALIGNED(n) -> xpcc_aligned(n)
- ATTRIBUTE_PACKED -> xpcc_packed
- ATTRIBUTE_FASTCODE -> xpcc_fastcode
- ATTRIBUTE_FASTDATA -> xpcc_fastdata
- ATTRIBUTE_MAY_ALIAS -> xpcc_may_alias
- CONCAT(a,b) -> XPCC_CONCAT(a,b)
- STRINGIFY(a) -> XPCC_STRINGIFY(a)
- XPCC__ARRAY_SIZE(x) -> XPCC_ARRAY_SIZE(x)
- likely(x) -> xpcc_likely(x)
- unlikely(x) -> xpcc_unlikely(x)
Note that the ENUM_CLASS_FLAG
was replaced with xpcc::Flags32
and
is not completely backwards compatible (Interrupt
vs Interrupt_t
).
PR #182 -> 9940a65 with high impact due to breaking API change.
Includes better handling of platform specific startup code, a better location for linkerscripts and minor code cleanup.
PR #180 -> 0dbf73c with low impact on ARM Cortex-M targets.
Tested in hardware by @salkinium.
PR #175 -> 26471ab.
Tested in hardware by @strongly-typed.
PR #173 -> 3c7cd31.
Tested in hardware by @strongly-typed.
Adds build system and startup script support for ARM Cortex-M7 with double precision FPU as well as CI tests.
PR #173 -> c605416 with low impact on STM32 devices.
Tested in hardware by @strongly-typed.
Update to the latest CMSIS device headers for STM32 and adds a few new device files.
PR #168 -> 84d5bd0 with medium impact on STM32 devices.
Tested in hardware by @salkinium.
Apparently acquire
is spelled with a c
. This fix breaks the API, sorry!
PR #167 -> fd1b109 with high impact on drivers due to breaking API change.
There are more than one STM32F7 Discovery board available, this renames
the stm32f7_discovery
board target to stm32f746g_discovery
PR #165 -> 637e074 with high impact on STM32F7 targets.
Add board support for STM32F103C8T6 Minimum System Development, aka. "Blue Pill", and examples.
PR #154 -> 7ab0132.
Tested in hardware by @strongly-typed.
PR #155 -> 63ad1d3.
Tested in hardware by @salkinium.
Adds initialization code and examples for the DSI and display found on the board.
PR #155 -> 0118a13.
Tested in hardware by @salkinium.
A heap table in the linkerscript describes the memory regions with their traits. The allocator implementation reads this table to initialize the heaps. To allocate memory, the heap that fits the requested traits best is chosen.
Three heap algorithms can be chosen from using the xpcc parameters:
- newlib's dlmalloc (default): Chooses largest continuous heap from page table.
- xpcc's block allocator: Chooses largest heap from page table.
- TLSF: Uses all heaps in the table.
Overloading of the new operator in C++ is provided:
Foo *foo = new (xpcc::MemoryFastData) Foo(args);
Finally, linkerscripts can be extended to include additional memory regions that include static data and bss as well as heap sections.
PR #147 -> e2f9b4a with low impact on ARM Cortex-M targets with TLSF allocator.
Tested in hardware by @salkinium.
PR #145 -> 6c1a111.
Tested in hardware by @salkinium.
PR ? -> 2504682.
Tested in hardware by @salkinium.
This replaces the very dynamic xpcc::stm32::SystemClock
with a fake
SystemClock class that is hardcoded to a specific clock speed.
This makes porting to new boards easier.
PR #144 -> 170f53a with medium impact on STM32 board targets.
Tested in hardware by @salkinium.
This introduces the FlagsOperators class which contains nothing else but the bitwise operators overloads and comparison functions. This class in then inherited from for the Flags, Configurations and Value classes, enabling transparent use of these operator overloads between the classes.
PR #143 -> a6519c3 with low impact.
PR #138 -> e346020.
Tested in hardware by @salkinium.
Overwriting the weak functions in newlib regarding malloc does not work correctly.
This bug was discovered on the F103 platform, where the first byte of 2B receive transfers was not acknowledged by the master. This resulted in the slave device never placing the data for the 2nd byte on the bus, effectively "sending" 0xff as the second byte.
PR #129 -> 408c309.
Tested in hardware by @strongly-typed.
These changes fix the embedded test runners for AVR and STM32 targets, and fixes bugs in the unit test source code that come from using the cross compilers (float vs. double tolerances, type promotions, etc).
These changes add the TLSF implementation from http://tlsf.baisoku.org and enable it by default, completely replacing the newlib allocator.
Up to three arenas are constructed:
- SRAM: with
.heap1
,.heap2
if available and.heap3
if available - CCM or DTCM: with
.heap0
if available - ITCM: with
.heap4
if available
These three functions are provided:
malloc
: Uses SRAM by default, falls back to CCM if SRAM is fullrealloc
: determines source arena by pointer addressfree
: determines source arena by pointer address
PR #115 -> ffa4e1b with medium impact on ARM Cortex-M targets.
Tested in hardware by @salkinium.
Please interpret the git history for older changes.