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Copy pathADuCM355_typedefs.h
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ADuCM355_typedefs.h
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/******************************************************************************
Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved.
This software is proprietary to Analog Devices, Inc. and its licensors.
By using this software you agree to the terms of the associated
Analog Devices Software License Agreement.
*****************************************************************************/
#ifndef _ADUCM355_TYPEDEFS_H
#define _ADUCM355_TYPEDEFS_H
/* pickup integer types */
#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__))
#include <stdint.h>
#endif /* _LANGUAGE_C */
#if defined ( __CC_ARM )
#pragma push
#pragma anon_unions
#endif
#if defined (_MISRA_RULES)
/*
anonymous unions violate ISO 9899:1990 and therefore MISRA Rule 1.1.
Use of unions violates MISRA Rule 18.4.
Anonymous unions are required for this implementation.
Re-use of identifiers violates MISRA Rule 5.7.
Field names are repeated for the ADuCM355 register map.
*/
#pragma diag(push)
#pragma diag(suppress:misra_rule_1_1:"Allow anonymous unions")
#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit")
#pragma diag(suppress:misra_rule_5_3:"Header will re-use typedef identifiers")
#pragma diag(suppress:misra_rule_5_6:"Header will re-use identifiers in the same scope")
#pragma diag(suppress:misra_rule_5_7:"Header will re-use identifiers")
#pragma diag(suppress:misra_rule_18_4:"Allow the use of a union")
#endif /* _MISRA_RULES */
/** @defgroup LOAD 16-bit load value (LOAD) Register
* 16-bit load value (LOAD) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_TMR_LOAD_Struct
*! \brief 16-bit load value Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_LOAD_t__
typedef struct _ADI_TMR_LOAD_t {
union {
struct {
int16_t VALUE : 16; /**< Load value */
};
int16_t VALUE16;
};
} ADI_TMR_LOAD_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_LOAD_t__ */
/*@}*/
/** @defgroup CURCNT 16-bit timer value (CURCNT) Register
* 16-bit timer value (CURCNT) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_TMR_CURCNT_Struct
*! \brief 16-bit timer value Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CURCNT_t__
typedef struct _ADI_TMR_CURCNT_t {
union {
struct {
int16_t VALUE : 16; /**< Current count */
};
int16_t VALUE16;
};
} ADI_TMR_CURCNT_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CURCNT_t__ */
/*@}*/
/** @defgroup CTL Control (CTL) Register
* Control (CTL) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_TMR_CTL_Struct
*! \brief Control Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CTL_t__
typedef struct _ADI_TMR_CTL_t {
union {
struct {
uint16_t PRE : 2; /**< Prescaler */
uint16_t UP : 1; /**< Count up */
uint16_t MODE : 1; /**< Timer mode */
uint16_t EN : 1; /**< Timer enable */
uint16_t CLK : 2; /**< Clock select */
uint16_t RLD : 1; /**< Reload control */
uint16_t EVTRANGE : 5; /**< Event select range */
uint16_t EVTEN : 1; /**< Event select */
uint16_t RSTEN : 1; /**< Counter and prescale reset enable */
uint16_t SYNCBYP : 1; /**< Synchronization bypass */
};
uint16_t VALUE16;
};
} ADI_TMR_CTL_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CTL_t__ */
/*@}*/
/** @defgroup CLRINT Clear Interrupt (CLRINT) Register
* Clear Interrupt (CLRINT) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_TMR_CLRINT_Struct
*! \brief Clear Interrupt Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CLRINT_t__
typedef struct _ADI_TMR_CLRINT_t {
union {
struct {
uint16_t TIMEOUT : 1; /**< Clear timeout interrupt */
uint16_t EVTCAPT : 1; /**< Clear captured event interrupt */
uint16_t reserved2 : 14;
};
uint16_t VALUE16;
};
} ADI_TMR_CLRINT_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CLRINT_t__ */
/*@}*/
/** @defgroup CAPTURE Capture (CAPTURE) Register
* Capture (CAPTURE) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_TMR_CAPTURE_Struct
*! \brief Capture Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CAPTURE_t__
typedef struct _ADI_TMR_CAPTURE_t {
union {
struct {
int16_t VALUE : 16; /**< 16-bit captured value */
};
int16_t VALUE16;
};
} ADI_TMR_CAPTURE_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CAPTURE_t__ */
/*@}*/
/** @defgroup ALOAD 16-bit load value, asynchronous (ALOAD) Register
* 16-bit load value, asynchronous (ALOAD) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_TMR_ALOAD_Struct
*! \brief 16-bit load value, asynchronous Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_ALOAD_t__
typedef struct _ADI_TMR_ALOAD_t {
union {
struct {
int16_t VALUE : 16; /**< Load value, asynchronous */
};
int16_t VALUE16;
};
} ADI_TMR_ALOAD_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_ALOAD_t__ */
/*@}*/
/** @defgroup ACURCNT 16-bit timer value, asynchronous (ACURCNT) Register
* 16-bit timer value, asynchronous (ACURCNT) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_TMR_ACURCNT_Struct
*! \brief 16-bit timer value, asynchronous Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_ACURCNT_t__
typedef struct _ADI_TMR_ACURCNT_t {
union {
struct {
int16_t VALUE : 16; /**< Counter value */
};
int16_t VALUE16;
};
} ADI_TMR_ACURCNT_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_ACURCNT_t__ */
/*@}*/
/** @defgroup STAT Status (STAT) Register
* Status (STAT) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_TMR_STAT_Struct
*! \brief Status Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_STAT_t__
typedef struct _ADI_TMR_STAT_t {
union {
struct {
uint16_t TIMEOUT : 1; /**< Timeout event occurred */
uint16_t CAPTURE : 1; /**< Capture event pending */
uint16_t reserved2 : 4;
uint16_t BUSY : 1; /**< Timer Busy */
uint16_t PDOK : 1; /**< Clear Interrupt Register synchronization */
uint16_t CNTRST : 1; /**< Counter reset occurring */
uint16_t reserved9 : 7;
};
uint16_t VALUE16;
};
} ADI_TMR_STAT_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_STAT_t__ */
/*@}*/
/** @defgroup PWMCTL PWM Control Register (PWMCTL) Register
* PWM Control Register (PWMCTL) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_TMR_PWMCTL_Struct
*! \brief PWM Control Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_PWMCTL_t__
typedef struct _ADI_TMR_PWMCTL_t {
union {
struct {
uint16_t MATCH : 1; /**< PWM Match enabled */
uint16_t IDLESTATE : 1; /**< PWM Idle State */
uint16_t reserved2 : 14;
};
uint16_t VALUE16;
};
} ADI_TMR_PWMCTL_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_PWMCTL_t__ */
/*@}*/
/** @defgroup PWMMATCH PWM Match Value (PWMMATCH) Register
* PWM Match Value (PWMMATCH) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_TMR_PWMMATCH_Struct
*! \brief PWM Match Value Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_PWMMATCH_t__
typedef struct _ADI_TMR_PWMMATCH_t {
union {
struct {
int16_t VALUE : 16; /**< PWM Match Value */
};
int16_t VALUE16;
};
} ADI_TMR_PWMMATCH_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_PWMMATCH_t__ */
/*@}*/
/** @defgroup CR0 RTC Control 0 (CR0) Register
* RTC Control 0 (CR0) Register.
* @{
*/
/* =========================================================================
*! \enum ADI_RTC_CR0_MOD60ALM
*! \brief Periodic, modulo-60 alarm time in prescaled RTC time units beyond a modulo-60 boundary (MOD60ALM) Enumerations
* ========================================================================= */
typedef enum
{
RTC_CR0_EXAMPLE_1_THIRTY_TIME_UNITS_DECIMAL = 30, /**< Example of setting a modulo-60 periodic interrupt from the RTC to be issued to the CPU at 30 time units past a modulo-60 boundary. */
RTC_CR0_EXAMPLE_2_FIFTYFIVE_TIME_UNITS_DECIMAL = 55 /**< Example of setting a modulo-60 periodic interrupt from the RTC to be issued to the CPU at 55 time units past a modulo-60 boundary. */
} ADI_RTC_CR0_MOD60ALM;
/* ==========================================================================
*! \struct ADI_RTC_CR0_Struct
*! \brief RTC Control 0 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR0_t__
typedef struct _ADI_RTC_CR0_t {
union {
struct {
uint16_t CNTEN : 1; /**< Global enable for the RTC */
uint16_t ALMEN : 1; /**< Enable the RTC alarm (absolute) operation */
uint16_t ALMINTEN : 1; /**< Enable sourced alarm interrupts to the CPU */
uint16_t TRMEN : 1; /**< Enable RTC digital trimming */
uint16_t MOD60ALMEN : 1; /**< Enable RTC modulo-60 counting of time past a modulo-60 boundary */
uint16_t MOD60ALM : 6; /**< Periodic, modulo-60 alarm time in prescaled RTC time units beyond a modulo-60 boundary */
uint16_t MOD60ALMINTEN : 1; /**< Enable periodic Modulo-60 RTC alarm sourced interrupts to the CPU */
uint16_t ISOINTEN : 1; /**< Enable RTC power-domain isolation sourced interrupts to the CPU when isolation of the RTC power domain is activated and subsequently de-activated */
uint16_t WPNDERRINTEN : 1; /**< Enable Write pending error sourced interrupts to the CPU when an RTC register-write pending error occurs */
uint16_t WSYNCINTEN : 1; /**< Enable Write synchronization sourced interrupts to the CPU */
uint16_t WPNDINTEN : 1; /**< Enable Write Pending sourced interrupts to the CPU */
};
uint16_t VALUE16;
};
} ADI_RTC_CR0_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR0_t__ */
/*@}*/
/** @defgroup SR0 RTC Status 0 (SR0) Register
* RTC Status 0 (SR0) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_SR0_Struct
*! \brief RTC Status 0 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR0_t__
typedef struct _ADI_RTC_SR0_t {
union {
struct {
uint16_t reserved0 : 1;
uint16_t ALMINT : 1; /**< Alarm interrupt source */
uint16_t MOD60ALMINT : 1; /**< Modulo-60 RTC alarm interrupt source */
uint16_t ISOINT : 1; /**< RTC power-domain isolation interrupt source */
uint16_t WPNDERRINT : 1; /**< Write pending error interrupt source */
uint16_t WSYNCINT : 1; /**< Write synchronization interrupt */
uint16_t WPNDINT : 1; /**< Write pending interrupt */
uint16_t WSYNCCR0 : 1; /**< Synchronization status of posted writes to RTC Control 0 Register */
uint16_t WSYNCSR0 : 1; /**< Synchronization status of posted clearances to interrupt sources in RTC Status 0 Register */
uint16_t WSYNCCNT0 : 1; /**< Synchronization status of posted writes to RTC Count 0 Register */
uint16_t WSYNCCNT1 : 1; /**< Synchronization status of posted writes to RTC Count 1 Register */
uint16_t WSYNCALM0 : 1; /**< Synchronization status of posted writes to RTC Alarm 0 Register */
uint16_t WSYNCALM1 : 1; /**< Synchronization status of posted writes to RTC Alarm 1 Register */
uint16_t WSYNCTRM : 1; /**< Synchronization status of posted writes to RTC Trim Register */
uint16_t ISOENB : 1; /**< Visibility status of 32 kHz sourced registers, taking account of power-domain isolation */
uint16_t reserved15 : 1;
};
uint16_t VALUE16;
};
} ADI_RTC_SR0_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR0_t__ */
/*@}*/
/** @defgroup SR1 RTC Status 1 (SR1) Register
* RTC Status 1 (SR1) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_SR1_Struct
*! \brief RTC Status 1 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR1_t__
typedef struct _ADI_RTC_SR1_t {
union {
struct {
uint16_t reserved0 : 7;
uint16_t WPNDCR0 : 1; /**< Pending status of posted writes to RTC Control 0 Register */
uint16_t WPNDSR0 : 1; /**< Pending status of posted clearances of interrupt sources in RTC Status 0 Register */
uint16_t WPNDCNT0 : 1; /**< Pending status of posted writes to RTC Count 0 Register */
uint16_t WPNDCNT1 : 1; /**< Pending status of posted writes to RTC Count 1 Register */
uint16_t WPNDALM0 : 1; /**< Pending status of posted writes to RTC ALARM 0 Register */
uint16_t WPNDALM1 : 1; /**< Pending status of posted writes to RTC ALARM 1 Register */
uint16_t WPNDTRM : 1; /**< Pending status of posted writes to RTC Trim Register */
uint16_t reserved14 : 2;
};
uint16_t VALUE16;
};
} ADI_RTC_SR1_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR1_t__ */
/*@}*/
/** @defgroup CNT0 RTC Count 0 (CNT0) Register
* RTC Count 0 (CNT0) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_CNT0_Struct
*! \brief RTC Count 0 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CNT0_t__
typedef struct _ADI_RTC_CNT0_t {
union {
struct {
uint16_t VALUE : 16; /**< Lower 16 prescaled (non-fractional) bits of the RTC real-time count */
};
uint16_t VALUE16;
};
} ADI_RTC_CNT0_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CNT0_t__ */
/*@}*/
/** @defgroup CNT1 RTC Count 1 (CNT1) Register
* RTC Count 1 (CNT1) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_CNT1_Struct
*! \brief RTC Count 1 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CNT1_t__
typedef struct _ADI_RTC_CNT1_t {
union {
struct {
uint16_t VALUE : 16; /**< Upper 16 prescaled (non-fractional) bits of the RTC real-time count */
};
uint16_t VALUE16;
};
} ADI_RTC_CNT1_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CNT1_t__ */
/*@}*/
/** @defgroup ALM0 RTC Alarm 0 (ALM0) Register
* RTC Alarm 0 (ALM0) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_ALM0_Struct
*! \brief RTC Alarm 0 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_ALM0_t__
typedef struct _ADI_RTC_ALM0_t {
union {
struct {
uint16_t VALUE : 16; /**< Lower 16 prescaled (that is, non-fractional) bits of the RTC alarm target time */
};
uint16_t VALUE16;
};
} ADI_RTC_ALM0_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_ALM0_t__ */
/*@}*/
/** @defgroup ALM1 RTC Alarm 1 (ALM1) Register
* RTC Alarm 1 (ALM1) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_ALM1_Struct
*! \brief RTC Alarm 1 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_ALM1_t__
typedef struct _ADI_RTC_ALM1_t {
union {
struct {
uint16_t VALUE : 16; /**< Upper 16 prescaled (non-fractional) bits of the RTC alarm target time */
};
uint16_t VALUE16;
};
} ADI_RTC_ALM1_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_ALM1_t__ */
/*@}*/
/** @defgroup TRM RTC Trim (TRM) Register
* RTC Trim (TRM) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_TRM_Struct
*! \brief RTC Trim Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_TRM_t__
typedef struct _ADI_RTC_TRM_t {
union {
struct {
uint16_t VALUE : 3; /**< Trim value in prescaled RTC time units to be added or subtracted from the RTC count at the end of a periodic interval selected by RTC Trim Register */
uint16_t ADD : 1; /**< Trim Polarity */
uint16_t IVL : 2; /**< Trim interval in prescaled RTC time units */
uint16_t IVL2EXPMIN : 4; /**< Minimum power-of-two interval of prescaled RTC time units, which RTC Trim Register can select */
uint16_t reserved10 : 6;
};
uint16_t VALUE16;
};
} ADI_RTC_TRM_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_TRM_t__ */
/*@}*/
/** @defgroup GWY RTC Gateway (GWY) Register
* RTC Gateway (GWY) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_GWY_Struct
*! \brief RTC Gateway Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_GWY_t__
typedef struct _ADI_RTC_GWY_t {
union {
struct {
uint16_t SWKEY : 16; /**< Software-keyed command issued by the CPU */
};
uint16_t VALUE16;
};
} ADI_RTC_GWY_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_GWY_t__ */
/*@}*/
/** @defgroup CR1 RTC Control 1 (CR1) Register
* RTC Control 1 (CR1) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_CR1_Struct
*! \brief RTC Control 1 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR1_t__
typedef struct _ADI_RTC_CR1_t {
union {
struct {
uint16_t CNTINTEN : 1; /**< Enable for the RTC count interrupt source */
uint16_t PSINTEN : 1; /**< Enable for the prescaled, modulo-1 interrupt source */
uint16_t RTCTRMINTEN : 1; /**< Enable for the RTC Trim interrupt source */
uint16_t CNTROLLINTEN : 1; /**< Enable for the RTC count roll-over interrupt source in RTC Status 2 Register */
uint16_t CNTMOD60ROLLINTEN : 1; /**< Enable for the RTC modulo-60 count roll-over interrupt source in RTC Status 2 Register */
uint16_t PRESCALE2EXP : 4; /**< Prescale power of 2 division factor for the RTC base clock */
uint16_t reserved9 : 7;
};
uint16_t VALUE16;
};
} ADI_RTC_CR1_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR1_t__ */
/*@}*/
/** @defgroup SR2 RTC Status 2 (SR2) Register
* RTC Status 2 (SR2) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_SR2_Struct
*! \brief RTC Status 2 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR2_t__
typedef struct _ADI_RTC_SR2_t {
union {
struct {
uint16_t CNTINT : 1; /**< RTC count interrupt source */
uint16_t PSINT : 1; /**< RTC prescaled, modulo-1 boundary interrupt source */
uint16_t TRMINT : 1; /**< RTC Trim interrupt source */
uint16_t CNTROLLINT : 1; /**< RTC count roll-over interrupt source */
uint16_t CNTMOD60ROLLINT : 1; /**< RTC modulo-60 count roll-over interrupt source */
uint16_t CNTROLL : 1; /**< RTC count roll-over */
uint16_t CNTMOD60ROLL : 1; /**< RTC count modulo-60 roll-over */
uint16_t TRMBDYMIR : 1; /**< Mirror of the RTCTRMBDY field of RTC Modulo Register */
uint16_t reserved8 : 4;
uint16_t WPNDCR1MIR : 1; /**< Pending status of posted writes to RTC Control 1 Register */
uint16_t WPNDALM2MIR : 1; /**< Pending status of posted writes to RTC Alarm 2 Register */
uint16_t WSYNCCR1MIR : 1; /**< Synchronization status of posted writes to RTC Control 1 Register */
uint16_t WSYNCALM2MIR : 1; /**< Synchronization status of posted writes to RTC Alarm 2 Register */
};
uint16_t VALUE16;
};
} ADI_RTC_SR2_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR2_t__ */
/*@}*/
/** @defgroup SNAP0 RTC Snapshot 0 (SNAP0) Register
* RTC Snapshot 0 (SNAP0) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_SNAP0_Struct
*! \brief RTC Snapshot 0 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SNAP0_t__
typedef struct _ADI_RTC_SNAP0_t {
union {
struct {
uint16_t VALUE : 16; /**< Constituent part of the 47-bit RTC Input Capture Channel 0, containing a sticky snapshot of RTC Count 0 Register */
};
uint16_t VALUE16;
};
} ADI_RTC_SNAP0_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SNAP0_t__ */
/*@}*/
/** @defgroup SNAP1 RTC Snapshot 1 (SNAP1) Register
* RTC Snapshot 1 (SNAP1) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_SNAP1_Struct
*! \brief RTC Snapshot 1 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SNAP1_t__
typedef struct _ADI_RTC_SNAP1_t {
union {
struct {
uint16_t VALUE : 16; /**< Constituent part of the 47-bit RTC Input Capture Channel 0, containing a sticky snapshot of RTC Count 1 Register */
};
uint16_t VALUE16;
};
} ADI_RTC_SNAP1_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SNAP1_t__ */
/*@}*/
/** @defgroup SNAP2 RTC Snapshot 2 (SNAP2) Register
* RTC Snapshot 2 (SNAP2) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_SNAP2_Struct
*! \brief RTC Snapshot 2 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SNAP2_t__
typedef struct _ADI_RTC_SNAP2_t {
union {
struct {
uint16_t VALUE : 15; /**< Constituent part of the 47-bit RTC Input Capture Channel 0, containing a sticky snapshot of RTC Count 2 Register */
uint16_t reserved15 : 1;
};
uint16_t VALUE16;
};
} ADI_RTC_SNAP2_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SNAP2_t__ */
/*@}*/
/** @defgroup MOD RTC Modulo (MOD) Register
* RTC Modulo (MOD) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_MOD_Struct
*! \brief RTC Modulo Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_MOD_t__
typedef struct _ADI_RTC_MOD_t {
union {
struct {
uint16_t CNTMOD60 : 6; /**< Modulo-60 value of prescaled RTC Count 1 and RTC Count 0 Registers */
uint16_t INCR : 4; /**< Most recent increment value added to the RTC Count in RTC Count 1 and RTC Count 0 Registers */
uint16_t TRMBDY : 1; /**< Trim boundary indicator that the most recent RTC count increment has coincided with trimming of the count value */
uint16_t CNT0_4TOZERO : 5; /**< Mirror of RTC Count 0 Register [4:0] */
};
uint16_t VALUE16;
};
} ADI_RTC_MOD_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_MOD_t__ */
/*@}*/
/** @defgroup CNT2 RTC Count 2 (CNT2) Register
* RTC Count 2 (CNT2) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_CNT2_Struct
*! \brief RTC Count 2 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CNT2_t__
typedef struct _ADI_RTC_CNT2_t {
union {
struct {
uint16_t VALUE : 15; /**< Fractional bits of the RTC real-time count */
uint16_t reserved15 : 1;
};
uint16_t VALUE16;
};
} ADI_RTC_CNT2_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CNT2_t__ */
/*@}*/
/** @defgroup ALM2 RTC Alarm 2 (ALM2) Register
* RTC Alarm 2 (ALM2) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_ALM2_Struct
*! \brief RTC Alarm 2 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_ALM2_t__
typedef struct _ADI_RTC_ALM2_t {
union {
struct {
uint16_t VALUE : 15; /**< Fractional (non-prescaled) bits of the RTC alarm target time */
uint16_t reserved15 : 1;
};
uint16_t VALUE16;
};
} ADI_RTC_ALM2_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_ALM2_t__ */
/*@}*/
/** @defgroup SR3 RTC Status 3 (SR3) Register
* RTC Status 3 (SR3) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_SR3_Struct
*! \brief RTC Status 3 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR3_t__
typedef struct _ADI_RTC_SR3_t {
union {
struct {
uint16_t RTCIC0IRQ : 1; /**< Sticky Interrupt Source for the RTC Input Capture Channel 0 */
uint16_t reserved1 : 1;
uint16_t RTCIC2IRQ : 1; /**< Sticky Interrupt Source for the RTC Input Capture Channel 2 */
uint16_t RTCIC3IRQ : 1; /**< Sticky Interrupt Source for the RTC Input Capture Channel 3 */
uint16_t RTCIC4IRQ : 1; /**< Sticky Interrupt Source for the RTC Input Capture Channel 4 */
uint16_t reserved5 : 3;
uint16_t ALMINTMIR : 1; /**< Read-only mirror of the ALMINT interrupt source in RTC Status 0 Register, acting as RTCOC0IRQ */
uint16_t RTCOC1IRQ : 1; /**< Sticky Interrupt Source for Output Compare Channel 1 */
uint16_t reserved10 : 6;
};
uint16_t VALUE16;
};
} ADI_RTC_SR3_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR3_t__ */
/*@}*/
/** @defgroup CR2IC RTC Control 2 for Configuring Input Capture Channels (CR2IC) Register
* RTC Control 2 for Configuring Input Capture Channels (CR2IC) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_CR2IC_Struct
*! \brief RTC Control 2 for Configuring Input Capture Channels Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR2IC_t__
typedef struct _ADI_RTC_CR2IC_t {
union {
struct {
uint16_t RTCIC0EN : 1; /**< Enable for the RTC Input Capture Channel 0 */
uint16_t reserved1 : 1;
uint16_t RTCIC2EN : 1; /**< Enable for the RTC Input Capture Channel 2 */
uint16_t RTCIC3EN : 1; /**< Enable for the RTC Input Capture Channel 3 */
uint16_t RTCIC4EN : 1; /**< Enable for the RTC Input Capture Channel 4 */
uint16_t RTCIC0LH : 1; /**< Polarity of the active-going capture edge for the RTC Input Capture Channel 0 */
uint16_t reserved6 : 1;
uint16_t RTCIC2LH : 1; /**< Polarity of the active-going capture edge for the RTC Input Capture Channel 2 */
uint16_t RTCIC3LH : 1; /**< Polarity of the active-going capture edge for the RTC Input Capture Channel 3 */
uint16_t RTCIC4LH : 1; /**< Polarity of the active-going capture edge for the RTC Input Capture Channel 4 */
uint16_t RTCIC0IRQEN : 1; /**< Interrupt Enable for the RTC Input Capture Channel 0 */
uint16_t reserved11 : 1;
uint16_t RTCIC2IRQEN : 1; /**< Interrupt Enable for the RTC Input Capture Channel 2 */
uint16_t RTCIC3IRQEN : 1; /**< Interrupt Enable for the RTC Input Capture Channel 3 */
uint16_t RTCIC4IRQEN : 1; /**< Interrupt Enable for the RTC Input Capture Channel 4 */
uint16_t RTCICOWUSEN : 1; /**< Enable Overwrite of Unread Snapshots for all RTC Input Capture Channels */
};
uint16_t VALUE16;
};
} ADI_RTC_CR2IC_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR2IC_t__ */
/*@}*/
/** @defgroup CR3OC RTC Control 3 for Configuring Output Compare Channel (CR3OC) Register
* RTC Control 3 for Configuring Output Compare Channel (CR3OC) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_CR3OC_Struct
*! \brief RTC Control 3 for Configuring Output Compare Channel Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR3OC_t__
typedef struct _ADI_RTC_CR3OC_t {
union {
struct {
uint16_t reserved0 : 1;
uint16_t RTCOC1EN : 1; /**< Enable for Output Compare Channel 1 */
uint16_t reserved2 : 7;
uint16_t RTCOC1IRQEN : 1; /**< Interrupt Enable for Output Compare Channel 1 */
uint16_t reserved10 : 6;
};
uint16_t VALUE16;
};
} ADI_RTC_CR3OC_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR3OC_t__ */
/*@}*/
/** @defgroup CR4OC RTC Control 4 for Configuring Output Compare Channel (CR4OC) Register
* RTC Control 4 for Configuring Output Compare Channel (CR4OC) Register.
* @{
*/
/* =========================================================================
*! \enum ADI_RTC_CR4OC_RTCOC1MSKEN
*! \brief Enable for thermometer-code masking of the Output Compare 1 Channel (RTCOC1MSKEN) Enumerations
* ========================================================================= */
typedef enum
{
RTC_CR4OC_EN000 = 0, /**< Do not apply a mask to the 16-bit Output Compare channel OC1. */
RTC_CR4OC_EN001 = 1 /**< Apply a thermometer-decoded mask to the 16-bit Output Compare channel OC1 provided that channel is enabled via CR3OC:RTCOC1EN */
} ADI_RTC_CR4OC_RTCOC1MSKEN;
/* ==========================================================================
*! \struct ADI_RTC_CR4OC_Struct
*! \brief RTC Control 4 for Configuring Output Compare Channel Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR4OC_t__
typedef struct _ADI_RTC_CR4OC_t {
union {
struct {
uint16_t reserved0 : 1;
uint16_t RTCOC1MSKEN : 1; /**< Enable for thermometer-code masking of the Output Compare 1 Channel */
uint16_t reserved2 : 7;
uint16_t RTCOC1ARLEN : 1; /**< Enable for auto-reloading when output compare match occurs */
uint16_t reserved10 : 6;
};
uint16_t VALUE16;
};
} ADI_RTC_CR4OC_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR4OC_t__ */
/*@}*/
/** @defgroup OCMSK RTC Masks for Output Compare Channel (OCMSK) Register
* RTC Masks for Output Compare Channel (OCMSK) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_OCMSK_Struct
*! \brief RTC Masks for Output Compare Channel Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_OCMSK_t__
typedef struct _ADI_RTC_OCMSK_t {
union {
struct {
uint16_t RTCOCMSK : 16; /**< Concatenation of thermometer-encoded masks for the 16-bit output compare channels */
};
uint16_t VALUE16;
};
} ADI_RTC_OCMSK_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_OCMSK_t__ */
/*@}*/
/** @defgroup OC1ARL RTC Auto-Reload for Output Compare Channel 1 (OC1ARL) Register
* RTC Auto-Reload for Output Compare Channel 1 (OC1ARL) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_OC1ARL_Struct
*! \brief RTC Auto-Reload for Output Compare Channel 1 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_OC1ARL_t__
typedef struct _ADI_RTC_OC1ARL_t {
union {
struct {
uint16_t RTCOC1ARL : 16; /**< Auto-reload value when output compare match occurs */
};
uint16_t VALUE16;
};
} ADI_RTC_OC1ARL_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_OC1ARL_t__ */
/*@}*/
/** @defgroup IC2 RTC Input Capture Channel 2 (IC2) Register
* RTC Input Capture Channel 2 (IC2) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_IC2_Struct
*! \brief RTC Input Capture Channel 2 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_IC2_t__
typedef struct _ADI_RTC_IC2_t {
union {
struct {
uint16_t RTCIC2 : 16; /**< RTC Input Capture Channel 2 */
};
uint16_t VALUE16;
};
} ADI_RTC_IC2_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_IC2_t__ */
/*@}*/
/** @defgroup IC3 RTC Input Capture Channel 3 (IC3) Register
* RTC Input Capture Channel 3 (IC3) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_IC3_Struct
*! \brief RTC Input Capture Channel 3 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_IC3_t__
typedef struct _ADI_RTC_IC3_t {
union {
struct {
uint16_t RTCIC3 : 16; /**< RTC Input Capture Channel 3 */
};
uint16_t VALUE16;
};
} ADI_RTC_IC3_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_IC3_t__ */
/*@}*/
/** @defgroup IC4 RTC Input Capture Channel 4 (IC4) Register
* RTC Input Capture Channel 4 (IC4) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_IC4_Struct
*! \brief RTC Input Capture Channel 4 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_IC4_t__
typedef struct _ADI_RTC_IC4_t {
union {
struct {
uint16_t RTCIC4 : 16; /**< RTC Input Capture Channel 4 */
};
uint16_t VALUE16;
};
} ADI_RTC_IC4_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_IC4_t__ */
/*@}*/
/** @defgroup OC1 RTC Output Compare Channel 1 (OC1) Register
* RTC Output Compare Channel 1 (OC1) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_OC1_Struct
*! \brief RTC Output Compare Channel 1 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_OC1_t__
typedef struct _ADI_RTC_OC1_t {
union {
struct {
uint16_t RTCOC1 : 16; /**< RTC Output Compare 1 Channel. Scheduled alarm target time with optional auto-reload */
};
uint16_t VALUE16;
};
} ADI_RTC_OC1_t;
#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_OC1_t__ */
/*@}*/
/** @defgroup SR4 RTC Status 4 (SR4) Register
* RTC Status 4 (SR4) Register.
* @{
*/
/* ==========================================================================
*! \struct ADI_RTC_SR4_Struct
*! \brief RTC Status 4 Register bit field structure
* ========================================================================== */
#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR4_t__
typedef struct _ADI_RTC_SR4_t {
union {
struct {