VHDL 2008/93/87 simulator

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

VHDL synthesis (based on ghdl)

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino

Trying to verify Verilog/VHDL designs with formal methods and tools

cryptography ip-cores in vhdl / verilog

Library of reusable VHDL components

Examples and design pattern for VHDL verification

HDL part for Loa's FPGA(s).

Library for Clock Domain Crossing