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apollo3-clkgen

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                               apollo3-clkgen
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Copyright (C) 2013-2017, Fujitsu Electronics Europe GmbH or a               
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This software, including source code, documentation and related             
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one of its subsidiaries ("Fujitsu").
                                                                            
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History
** Date        Ver       Initials          Description
**   - 2019-08-21  V1.0  MSc  Automatic Created
**   - 2019-08-30  V1.1  MSc             Startup for IAR corrected

Supported toolchain versions


ARM        5.11
IAR        7.30
iSYSTEM    9.12.213
Segger     4.1
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Example how to clock-out one of the different clock-sources with or without divider.

This example generates 48MHz divided by 4 (=12MHz) at PAD7.

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EOF (not truncated) 
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