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cpu_testbench.cpp
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#include "cpu.cpp"
#include "systemc.h"
int sc_main(int argc, char* argv[]) {
sc_signal<bool> clock;
sc_signal<bool> cpu_out;
sc_signal<int> Program_Counter;
sc_signal<sc_bv<32>> instruction;
sc_signal<sc_bv<32*32>> instruction_memory;
sc_signal<sc_bv<32*32>> data_memory;
int i = 0;
int tid = 0; // Test ID
// Connect the DUT
cpu cpu_1("cpu");
cpu_1.clock(clock);
cpu_1.cpu_out(cpu_out);
cpu_1.Program_Counter(Program_Counter);
cpu_1.instruction(instruction);
cpu_1.instruction_memory(instruction_memory);
cpu_1.data_memory(data_memory);
sc_start(1, SC_NS);
// Open VCD file
sc_trace_file* wf = sc_create_vcd_trace_file("cpu");
// Dump the desired signals
sc_trace(wf, clock, "clock");
sc_trace(wf, cpu_out, "cpu_out");
sc_trace(wf, instruction, "instruction");
sc_trace(wf, instruction_memory, "instruction_memory");
sc_trace(wf, data_memory, "data_memory");
//instruction_memory = rand();
instruction_memory = "00000000000100011000001000110011" // ADD
"01000000100100010000011010110011" // SUB
"00000000000100011111001000110011" // AND
"00000000001000011100011100110011" // XOR
"00000000100000011001001000110011" // SLL
"00000000010000011110001000110011" // OR
"00000000111100011101001000110011" // SRL
"01000000000100011111001000110011" // SRA
"00000000000100011010001000000011" // LOAD (Word)
"00000000000100011001001110000011" // LOAD (Half)
"00000000000100011000011000000011" // LOAD (Byte)
"00000000000100011101011000000011" // LOAD (UByte)
"01000000000100011000001000010011" // ADD Immediate
"00100000000100011001001000010011" // SLL Immediate
"00010000000100011010001000010011" // SLT Immediate
"01000000000100011011001000010011" // STLU Immediate
"00010000000100011100001000010011" // XOR Immediate
"00000100000100011101001000010011" // SRL Immediate
"00100000000100011110001000010011" // OR Immediate
"10000000000100011111001000010011" // AND Immediate
"00000000000100011010001000100011" // Store (Word)
"00000000000100011001001000100011" // Store (Half)
"00000000000100011000001000100011" // Store (Byte)
"00000000111101110000000101100011" // BRANCH ==
"00000000111101110001000101100011" // BRANCH !=
"00000000111101110010000101100011" // Illegal
"00000000111101110100000101100011" // BRANCH <
"00000000111101110101000101100011" // BRANCH >=
"00000000000100011111001000000000" // Illegal
"00000000001000000000001001101111" // JUMP
"00000000000100011111001000000000" // Illegal
"00000000000100011111001000000000";// Illegal
//data_memory = rand();
data_memory = "00000000000100011000001000110011"
"01000000100100010000011010110011"
"00000000000100011111001000110011"
"00000000001000011100011100110011"
"11111111010101010000000010101010"
"00000000010000011110001000110011"
"00000000111100011101001000110011"
"00000000000000000000000000000000"
"00000000000100011010001000000011"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111"
"00000000000100011111001001101111";
for (tid = 0; tid < 1; tid++) {
Program_Counter = 0;
// Here we run the clock
for (i = 0;i < 29;i++) {
clock = 0;
sc_start(1, SC_NS);
clock = 1;
sc_start(1, SC_NS);
}
}
cout << "@" << sc_time_stamp() << " Terminating simulation\n" << endl;
sc_close_vcd_trace_file(wf);
return 0;// Terminate simulation
}