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farsync.c
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/*
* FarSync WAN driver for Linux (2.6.x kernel version)
*
* Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
*
* Copyright (C) 2001-2004 FarSite Communications Ltd.
* www.farsite.co.uk
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* Author: R.J.Dunlop <[email protected]>
* Maintainer: Kevin Curtis <[email protected]>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/version.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/if.h>
#include <linux/hdlc.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include "farsync.h"
/*
* Module info
*/
MODULE_AUTHOR("R.J.Dunlop <[email protected]>");
MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd.");
MODULE_LICENSE("GPL");
/* Driver configuration and global parameters
* ==========================================
*/
/* Number of ports (per card) and cards supported
*/
#define FST_MAX_PORTS 4
#define FST_MAX_CARDS 32
/* Default parameters for the link
*/
#define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is
* useful, the syncppp module forces
* this down assuming a slower line I
* guess.
*/
#define FST_TXQ_DEPTH 16 /* This one is for the buffering
* of frames on the way down to the card
* so that we can keep the card busy
* and maximise throughput
*/
#define FST_HIGH_WATER_MARK 12 /* Point at which we flow control
* network layer */
#define FST_LOW_WATER_MARK 8 /* Point at which we remove flow
* control from network layer */
#define FST_MAX_MTU 8000 /* Huge but possible */
#define FST_DEF_MTU 1500 /* Common sane value */
#define FST_TX_TIMEOUT (2*HZ)
#ifdef ARPHRD_RAWHDLC
#define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */
#else
#define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */
#endif
/*
* Modules parameters and associated varaibles
*/
static int fst_txq_low = FST_LOW_WATER_MARK;
static int fst_txq_high = FST_HIGH_WATER_MARK;
static int fst_max_reads = 7;
static int fst_excluded_cards = 0;
static int fst_excluded_list[FST_MAX_CARDS];
module_param(fst_txq_low, int, 0);
module_param(fst_txq_high, int, 0);
module_param(fst_max_reads, int, 0);
module_param(fst_excluded_cards, int, 0);
module_param_array(fst_excluded_list, int, NULL, 0);
/* Card shared memory layout
* =========================
*/
#pragma pack(1)
/* This information is derived in part from the FarSite FarSync Smc.h
* file. Unfortunately various name clashes and the non-portability of the
* bit field declarations in that file have meant that I have chosen to
* recreate the information here.
*
* The SMC (Shared Memory Configuration) has a version number that is
* incremented every time there is a significant change. This number can
* be used to check that we have not got out of step with the firmware
* contained in the .CDE files.
*/
#define SMC_VERSION 24
#define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */
#define SMC_BASE 0x00002000L /* Base offset of the shared memory window main
* configuration structure */
#define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA
* buffers */
#define LEN_TX_BUFFER 8192 /* Size of packet buffers */
#define LEN_RX_BUFFER 8192
#define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */
#define LEN_SMALL_RX_BUFFER 256
#define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */
#define NUM_RX_BUFFER 8
/* Interrupt retry time in milliseconds */
#define INT_RETRY_TIME 2
/* The Am186CH/CC processors support a SmartDMA mode using circular pools
* of buffer descriptors. The structure is almost identical to that used
* in the LANCE Ethernet controllers. Details available as PDF from the
* AMD web site: http://www.amd.com/products/epd/processors/\
* 2.16bitcont/3.am186cxfa/a21914/21914.pdf
*/
struct txdesc { /* Transmit descriptor */
volatile u16 ladr; /* Low order address of packet. This is a
* linear address in the Am186 memory space
*/
volatile u8 hadr; /* High order address. Low 4 bits only, high 4
* bits must be zero
*/
volatile u8 bits; /* Status and config */
volatile u16 bcnt; /* 2s complement of packet size in low 15 bits.
* Transmit terminal count interrupt enable in
* top bit.
*/
u16 unused; /* Not used in Tx */
};
struct rxdesc { /* Receive descriptor */
volatile u16 ladr; /* Low order address of packet */
volatile u8 hadr; /* High order address */
volatile u8 bits; /* Status and config */
volatile u16 bcnt; /* 2s complement of buffer size in low 15 bits.
* Receive terminal count interrupt enable in
* top bit.
*/
volatile u16 mcnt; /* Message byte count (15 bits) */
};
/* Convert a length into the 15 bit 2's complement */
/* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */
/* Since we need to set the high bit to enable the completion interrupt this
* can be made a lot simpler
*/
#define cnv_bcnt(len) (-(len))
/* Status and config bits for the above */
#define DMA_OWN 0x80 /* SmartDMA owns the descriptor */
#define TX_STP 0x02 /* Tx: start of packet */
#define TX_ENP 0x01 /* Tx: end of packet */
#define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */
#define RX_FRAM 0x20 /* Rx: framing error */
#define RX_OFLO 0x10 /* Rx: overflow error */
#define RX_CRC 0x08 /* Rx: CRC error */
#define RX_HBUF 0x04 /* Rx: buffer error */
#define RX_STP 0x02 /* Rx: start of packet */
#define RX_ENP 0x01 /* Rx: end of packet */
/* Interrupts from the card are caused by various events which are presented
* in a circular buffer as several events may be processed on one physical int
*/
#define MAX_CIRBUFF 32
struct cirbuff {
u8 rdindex; /* read, then increment and wrap */
u8 wrindex; /* write, then increment and wrap */
u8 evntbuff[MAX_CIRBUFF];
};
/* Interrupt event codes.
* Where appropriate the two low order bits indicate the port number
*/
#define CTLA_CHG 0x18 /* Control signal changed */
#define CTLB_CHG 0x19
#define CTLC_CHG 0x1A
#define CTLD_CHG 0x1B
#define INIT_CPLT 0x20 /* Initialisation complete */
#define INIT_FAIL 0x21 /* Initialisation failed */
#define ABTA_SENT 0x24 /* Abort sent */
#define ABTB_SENT 0x25
#define ABTC_SENT 0x26
#define ABTD_SENT 0x27
#define TXA_UNDF 0x28 /* Transmission underflow */
#define TXB_UNDF 0x29
#define TXC_UNDF 0x2A
#define TXD_UNDF 0x2B
#define F56_INT 0x2C
#define M32_INT 0x2D
#define TE1_ALMA 0x30
/* Port physical configuration. See farsync.h for field values */
struct port_cfg {
u16 lineInterface; /* Physical interface type */
u8 x25op; /* Unused at present */
u8 internalClock; /* 1 => internal clock, 0 => external */
u8 transparentMode; /* 1 => on, 0 => off */
u8 invertClock; /* 0 => normal, 1 => inverted */
u8 padBytes[6]; /* Padding */
u32 lineSpeed; /* Speed in bps */
};
/* TE1 port physical configuration */
struct su_config {
u32 dataRate;
u8 clocking;
u8 framing;
u8 structure;
u8 interface;
u8 coding;
u8 lineBuildOut;
u8 equalizer;
u8 transparentMode;
u8 loopMode;
u8 range;
u8 txBufferMode;
u8 rxBufferMode;
u8 startingSlot;
u8 losThreshold;
u8 enableIdleCode;
u8 idleCode;
u8 spare[44];
};
/* TE1 Status */
struct su_status {
u32 receiveBufferDelay;
u32 framingErrorCount;
u32 codeViolationCount;
u32 crcErrorCount;
u32 lineAttenuation;
u8 portStarted;
u8 lossOfSignal;
u8 receiveRemoteAlarm;
u8 alarmIndicationSignal;
u8 spare[40];
};
/* Finally sling all the above together into the shared memory structure.
* Sorry it's a hodge podge of arrays, structures and unused bits, it's been
* evolving under NT for some time so I guess we're stuck with it.
* The structure starts at offset SMC_BASE.
* See farsync.h for some field values.
*/
struct fst_shared {
/* DMA descriptor rings */
struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER];
struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER];
/* Obsolete small buffers */
u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER];
u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER];
u8 taskStatus; /* 0x00 => initialising, 0x01 => running,
* 0xFF => halted
*/
u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt,
* set to 0xEE by host to acknowledge interrupt
*/
u16 smcVersion; /* Must match SMC_VERSION */
u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major
* version, RR = revision and BB = build
*/
u16 txa_done; /* Obsolete completion flags */
u16 rxa_done;
u16 txb_done;
u16 rxb_done;
u16 txc_done;
u16 rxc_done;
u16 txd_done;
u16 rxd_done;
u16 mailbox[4]; /* Diagnostics mailbox. Not used */
struct cirbuff interruptEvent; /* interrupt causes */
u32 v24IpSts[FST_MAX_PORTS]; /* V.24 control input status */
u32 v24OpSts[FST_MAX_PORTS]; /* V.24 control output status */
struct port_cfg portConfig[FST_MAX_PORTS];
u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */
u16 cableStatus; /* lsb: 0=> present, 1=> absent */
u16 txDescrIndex[FST_MAX_PORTS]; /* transmit descriptor ring index */
u16 rxDescrIndex[FST_MAX_PORTS]; /* receive descriptor ring index */
u16 portMailbox[FST_MAX_PORTS][2]; /* command, modifier */
u16 cardMailbox[4]; /* Not used */
/* Number of times the card thinks the host has
* missed an interrupt by not acknowledging
* within 2mS (I guess NT has problems)
*/
u32 interruptRetryCount;
/* Driver private data used as an ID. We'll not
* use this as I'd rather keep such things
* in main memory rather than on the PCI bus
*/
u32 portHandle[FST_MAX_PORTS];
/* Count of Tx underflows for stats */
u32 transmitBufferUnderflow[FST_MAX_PORTS];
/* Debounced V.24 control input status */
u32 v24DebouncedSts[FST_MAX_PORTS];
/* Adapter debounce timers. Don't touch */
u32 ctsTimer[FST_MAX_PORTS];
u32 ctsTimerRun[FST_MAX_PORTS];
u32 dcdTimer[FST_MAX_PORTS];
u32 dcdTimerRun[FST_MAX_PORTS];
u32 numberOfPorts; /* Number of ports detected at startup */
u16 _reserved[64];
u16 cardMode; /* Bit-mask to enable features:
* Bit 0: 1 enables LED identify mode
*/
u16 portScheduleOffset;
struct su_config suConfig; /* TE1 Bits */
struct su_status suStatus;
u32 endOfSmcSignature; /* endOfSmcSignature MUST be the last member of
* the structure and marks the end of shared
* memory. Adapter code initializes it as
* END_SIG.
*/
};
/* endOfSmcSignature value */
#define END_SIG 0x12345678
/* Mailbox values. (portMailbox) */
#define NOP 0 /* No operation */
#define ACK 1 /* Positive acknowledgement to PC driver */
#define NAK 2 /* Negative acknowledgement to PC driver */
#define STARTPORT 3 /* Start an HDLC port */
#define STOPPORT 4 /* Stop an HDLC port */
#define ABORTTX 5 /* Abort the transmitter for a port */
#define SETV24O 6 /* Set V24 outputs */
/* PLX Chip Register Offsets */
#define CNTRL_9052 0x50 /* Control Register */
#define CNTRL_9054 0x6c /* Control Register */
#define INTCSR_9052 0x4c /* Interrupt control/status register */
#define INTCSR_9054 0x68 /* Interrupt control/status register */
/* 9054 DMA Registers */
/*
* Note that we will be using DMA Channel 0 for copying rx data
* and Channel 1 for copying tx data
*/
#define DMAMODE0 0x80
#define DMAPADR0 0x84
#define DMALADR0 0x88
#define DMASIZ0 0x8c
#define DMADPR0 0x90
#define DMAMODE1 0x94
#define DMAPADR1 0x98
#define DMALADR1 0x9c
#define DMASIZ1 0xa0
#define DMADPR1 0xa4
#define DMACSR0 0xa8
#define DMACSR1 0xa9
#define DMAARB 0xac
#define DMATHR 0xb0
#define DMADAC0 0xb4
#define DMADAC1 0xb8
#define DMAMARBR 0xac
#define FST_MIN_DMA_LEN 64
#define FST_RX_DMA_INT 0x01
#define FST_TX_DMA_INT 0x02
#define FST_CARD_INT 0x04
/* Larger buffers are positioned in memory at offset BFM_BASE */
struct buf_window {
u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER];
u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER];
};
/* Calculate offset of a buffer object within the shared memory window */
#define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X))
#pragma pack()
/* Device driver private information
* =================================
*/
/* Per port (line or channel) information
*/
struct fst_port_info {
struct net_device *dev; /* Device struct - must be first */
struct fst_card_info *card; /* Card we're associated with */
int index; /* Port index on the card */
int hwif; /* Line hardware (lineInterface copy) */
int run; /* Port is running */
int mode; /* Normal or FarSync raw */
int rxpos; /* Next Rx buffer to use */
int txpos; /* Next Tx buffer to use */
int txipos; /* Next Tx buffer to check for free */
int start; /* Indication of start/stop to network */
/*
* A sixteen entry transmit queue
*/
int txqs; /* index to get next buffer to tx */
int txqe; /* index to queue next packet */
struct sk_buff *txq[FST_TXQ_DEPTH]; /* The queue */
int rxqdepth;
};
/* Per card information
*/
struct fst_card_info {
char __iomem *mem; /* Card memory mapped to kernel space */
char __iomem *ctlmem; /* Control memory for PCI cards */
unsigned int phys_mem; /* Physical memory window address */
unsigned int phys_ctlmem; /* Physical control memory address */
unsigned int irq; /* Interrupt request line number */
unsigned int nports; /* Number of serial ports */
unsigned int type; /* Type index of card */
unsigned int state; /* State of card */
spinlock_t card_lock; /* Lock for SMP access */
unsigned short pci_conf; /* PCI card config in I/O space */
/* Per port info */
struct fst_port_info ports[FST_MAX_PORTS];
struct pci_dev *device; /* Information about the pci device */
int card_no; /* Inst of the card on the system */
int family; /* TxP or TxU */
int dmarx_in_progress;
int dmatx_in_progress;
unsigned long int_count;
unsigned long int_time_ave;
void *rx_dma_handle_host;
dma_addr_t rx_dma_handle_card;
void *tx_dma_handle_host;
dma_addr_t tx_dma_handle_card;
struct sk_buff *dma_skb_rx;
struct fst_port_info *dma_port_rx;
struct fst_port_info *dma_port_tx;
int dma_len_rx;
int dma_len_tx;
int dma_txpos;
int dma_rxpos;
};
/* Convert an HDLC device pointer into a port info pointer and similar */
#define dev_to_port(D) (dev_to_hdlc(D)->priv)
#define port_to_dev(P) ((P)->dev)
/*
* Shared memory window access macros
*
* We have a nice memory based structure above, which could be directly
* mapped on i386 but might not work on other architectures unless we use
* the readb,w,l and writeb,w,l macros. Unfortunately these macros take
* physical offsets so we have to convert. The only saving grace is that
* this should all collapse back to a simple indirection eventually.
*/
#define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X))
#define FST_RDB(C,E) readb ((C)->mem + WIN_OFFSET(E))
#define FST_RDW(C,E) readw ((C)->mem + WIN_OFFSET(E))
#define FST_RDL(C,E) readl ((C)->mem + WIN_OFFSET(E))
#define FST_WRB(C,E,B) writeb ((B), (C)->mem + WIN_OFFSET(E))
#define FST_WRW(C,E,W) writew ((W), (C)->mem + WIN_OFFSET(E))
#define FST_WRL(C,E,L) writel ((L), (C)->mem + WIN_OFFSET(E))
/*
* Debug support
*/
#if FST_DEBUG
static int fst_debug_mask = { FST_DEBUG };
/* Most common debug activity is to print something if the corresponding bit
* is set in the debug mask. Note: this uses a non-ANSI extension in GCC to
* support variable numbers of macro parameters. The inverted if prevents us
* eating someone else's else clause.
*/
#define dbg(F,fmt,A...) if ( ! ( fst_debug_mask & (F))) \
; \
else \
printk ( KERN_DEBUG FST_NAME ": " fmt, ## A )
#else
#define dbg(X...) /* NOP */
#endif
/* Printing short cuts
*/
#define printk_err(fmt,A...) printk ( KERN_ERR FST_NAME ": " fmt, ## A )
#define printk_warn(fmt,A...) printk ( KERN_WARNING FST_NAME ": " fmt, ## A )
#define printk_info(fmt,A...) printk ( KERN_INFO FST_NAME ": " fmt, ## A )
/*
* PCI ID lookup table
*/
static struct pci_device_id fst_pci_dev_id[] __devinitdata = {
{PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2P, PCI_ANY_ID,
PCI_ANY_ID, 0, 0, FST_TYPE_T2P},
{PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4P, PCI_ANY_ID,
PCI_ANY_ID, 0, 0, FST_TYPE_T4P},
{PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T1U, PCI_ANY_ID,
PCI_ANY_ID, 0, 0, FST_TYPE_T1U},
{PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2U, PCI_ANY_ID,
PCI_ANY_ID, 0, 0, FST_TYPE_T2U},
{PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4U, PCI_ANY_ID,
PCI_ANY_ID, 0, 0, FST_TYPE_T4U},
{PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1, PCI_ANY_ID,
PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
{PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1C, PCI_ANY_ID,
PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
{0,} /* End */
};
MODULE_DEVICE_TABLE(pci, fst_pci_dev_id);
/*
* Device Driver Work Queues
*
* So that we don't spend too much time processing events in the
* Interrupt Service routine, we will declare a work queue per Card
* and make the ISR schedule a task in the queue for later execution.
* In the 2.4 Kernel we used to use the immediate queue for BH's
* Now that they are gone, tasklets seem to be much better than work
* queues.
*/
static void do_bottom_half_tx(struct fst_card_info *card);
static void do_bottom_half_rx(struct fst_card_info *card);
static void fst_process_tx_work_q(unsigned long work_q);
static void fst_process_int_work_q(unsigned long work_q);
static DECLARE_TASKLET(fst_tx_task, fst_process_tx_work_q, 0);
static DECLARE_TASKLET(fst_int_task, fst_process_int_work_q, 0);
static struct fst_card_info *fst_card_array[FST_MAX_CARDS];
static spinlock_t fst_work_q_lock;
static u64 fst_work_txq;
static u64 fst_work_intq;
static void
fst_q_work_item(u64 * queue, int card_index)
{
unsigned long flags;
u64 mask;
/*
* Grab the queue exclusively
*/
spin_lock_irqsave(&fst_work_q_lock, flags);
/*
* Making an entry in the queue is simply a matter of setting
* a bit for the card indicating that there is work to do in the
* bottom half for the card. Note the limitation of 64 cards.
* That ought to be enough
*/
mask = 1 << card_index;
*queue |= mask;
spin_unlock_irqrestore(&fst_work_q_lock, flags);
}
static void
fst_process_tx_work_q(unsigned long /*void **/work_q)
{
unsigned long flags;
u64 work_txq;
int i;
/*
* Grab the queue exclusively
*/
dbg(DBG_TX, "fst_process_tx_work_q\n");
spin_lock_irqsave(&fst_work_q_lock, flags);
work_txq = fst_work_txq;
fst_work_txq = 0;
spin_unlock_irqrestore(&fst_work_q_lock, flags);
/*
* Call the bottom half for each card with work waiting
*/
for (i = 0; i < FST_MAX_CARDS; i++) {
if (work_txq & 0x01) {
if (fst_card_array[i] != NULL) {
dbg(DBG_TX, "Calling tx bh for card %d\n", i);
do_bottom_half_tx(fst_card_array[i]);
}
}
work_txq = work_txq >> 1;
}
}
static void
fst_process_int_work_q(unsigned long /*void **/work_q)
{
unsigned long flags;
u64 work_intq;
int i;
/*
* Grab the queue exclusively
*/
dbg(DBG_INTR, "fst_process_int_work_q\n");
spin_lock_irqsave(&fst_work_q_lock, flags);
work_intq = fst_work_intq;
fst_work_intq = 0;
spin_unlock_irqrestore(&fst_work_q_lock, flags);
/*
* Call the bottom half for each card with work waiting
*/
for (i = 0; i < FST_MAX_CARDS; i++) {
if (work_intq & 0x01) {
if (fst_card_array[i] != NULL) {
dbg(DBG_INTR,
"Calling rx & tx bh for card %d\n", i);
do_bottom_half_rx(fst_card_array[i]);
do_bottom_half_tx(fst_card_array[i]);
}
}
work_intq = work_intq >> 1;
}
}
/* Card control functions
* ======================
*/
/* Place the processor in reset state
*
* Used to be a simple write to card control space but a glitch in the latest
* AMD Am186CH processor means that we now have to do it by asserting and de-
* asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register
* at offset 9052_CNTRL. Note the updates for the TXU.
*/
static inline void
fst_cpureset(struct fst_card_info *card)
{
unsigned char interrupt_line_register;
unsigned long j = jiffies + 1;
unsigned int regval;
if (card->family == FST_FAMILY_TXU) {
if (pci_read_config_byte
(card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) {
dbg(DBG_ASS,
"Error in reading interrupt line register\n");
}
/*
* Assert PLX software reset and Am186 hardware reset
* and then deassert the PLX software reset but 186 still in reset
*/
outw(0x440f, card->pci_conf + CNTRL_9054 + 2);
outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
/*
* We are delaying here to allow the 9054 to reset itself
*/
j = jiffies + 1;
while (jiffies < j)
/* Do nothing */ ;
outw(0x240f, card->pci_conf + CNTRL_9054 + 2);
/*
* We are delaying here to allow the 9054 to reload its eeprom
*/
j = jiffies + 1;
while (jiffies < j)
/* Do nothing */ ;
outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
if (pci_write_config_byte
(card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) {
dbg(DBG_ASS,
"Error in writing interrupt line register\n");
}
} else {
regval = inl(card->pci_conf + CNTRL_9052);
outl(regval | 0x40000000, card->pci_conf + CNTRL_9052);
outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052);
}
}
/* Release the processor from reset
*/
static inline void
fst_cpurelease(struct fst_card_info *card)
{
if (card->family == FST_FAMILY_TXU) {
/*
* Force posted writes to complete
*/
(void) readb(card->mem);
/*
* Release LRESET DO = 1
* Then release Local Hold, DO = 1
*/
outw(0x040e, card->pci_conf + CNTRL_9054 + 2);
outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
} else {
(void) readb(card->ctlmem);
}
}
/* Clear the cards interrupt flag
*/
static inline void
fst_clear_intr(struct fst_card_info *card)
{
if (card->family == FST_FAMILY_TXU) {
(void) readb(card->ctlmem);
} else {
/* Poke the appropriate PLX chip register (same as enabling interrupts)
*/
outw(0x0543, card->pci_conf + INTCSR_9052);
}
}
/* Enable card interrupts
*/
static inline void
fst_enable_intr(struct fst_card_info *card)
{
if (card->family == FST_FAMILY_TXU) {
outl(0x0f0c0900, card->pci_conf + INTCSR_9054);
} else {
outw(0x0543, card->pci_conf + INTCSR_9052);
}
}
/* Disable card interrupts
*/
static inline void
fst_disable_intr(struct fst_card_info *card)
{
if (card->family == FST_FAMILY_TXU) {
outl(0x00000000, card->pci_conf + INTCSR_9054);
} else {
outw(0x0000, card->pci_conf + INTCSR_9052);
}
}
/* Process the result of trying to pass a received frame up the stack
*/
static void
fst_process_rx_status(int rx_status, char *name)
{
switch (rx_status) {
case NET_RX_SUCCESS:
{
/*
* Nothing to do here
*/
break;
}
case NET_RX_CN_LOW:
{
dbg(DBG_ASS, "%s: Receive Low Congestion\n", name);
break;
}
case NET_RX_CN_MOD:
{
dbg(DBG_ASS, "%s: Receive Moderate Congestion\n", name);
break;
}
case NET_RX_CN_HIGH:
{
dbg(DBG_ASS, "%s: Receive High Congestion\n", name);
break;
}
case NET_RX_DROP:
{
dbg(DBG_ASS, "%s: Received packet dropped\n", name);
break;
}
}
}
/* Initilaise DMA for PLX 9054
*/
static inline void
fst_init_dma(struct fst_card_info *card)
{
/*
* This is only required for the PLX 9054
*/
if (card->family == FST_FAMILY_TXU) {
pci_set_master(card->device);
outl(0x00020441, card->pci_conf + DMAMODE0);
outl(0x00020441, card->pci_conf + DMAMODE1);
outl(0x0, card->pci_conf + DMATHR);
}
}
/* Tx dma complete interrupt
*/
static void
fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
int len, int txpos)
{
struct net_device *dev = port_to_dev(port);
struct net_device_stats *stats = hdlc_stats(dev);
/*
* Everything is now set, just tell the card to go
*/
dbg(DBG_TX, "fst_tx_dma_complete\n");
FST_WRB(card, txDescrRing[port->index][txpos].bits,
DMA_OWN | TX_STP | TX_ENP);
stats->tx_packets++;
stats->tx_bytes += len;
dev->trans_start = jiffies;
}
/*
* Mark it for our own raw sockets interface
*/
static __be16 farsync_type_trans(struct sk_buff *skb, struct net_device *dev)
{
skb->dev = dev;
skb_reset_mac_header(skb);
skb->pkt_type = PACKET_HOST;
return htons(ETH_P_CUST);
}
/* Rx dma complete interrupt
*/
static void
fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
int len, struct sk_buff *skb, int rxp)
{
struct net_device *dev = port_to_dev(port);
struct net_device_stats *stats = hdlc_stats(dev);
int pi;
int rx_status;
dbg(DBG_TX, "fst_rx_dma_complete\n");
pi = port->index;
memcpy(skb_put(skb, len), card->rx_dma_handle_host, len);
/* Reset buffer descriptor */
FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
/* Update stats */
stats->rx_packets++;
stats->rx_bytes += len;
/* Push upstream */
dbg(DBG_RX, "Pushing the frame up the stack\n");
if (port->mode == FST_RAW)
skb->protocol = farsync_type_trans(skb, dev);
else
skb->protocol = hdlc_type_trans(skb, dev);
rx_status = netif_rx(skb);
fst_process_rx_status(rx_status, port_to_dev(port)->name);
if (rx_status == NET_RX_DROP)
stats->rx_dropped++;
dev->last_rx = jiffies;
}
/*
* Receive a frame through the DMA
*/
static inline void
fst_rx_dma(struct fst_card_info *card, unsigned char *skb,
unsigned char *mem, int len)
{
/*
* This routine will setup the DMA and start it
*/
dbg(DBG_RX, "In fst_rx_dma %p %p %d\n", skb, mem, len);
if (card->dmarx_in_progress) {
dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n");
}
outl((unsigned long) skb, card->pci_conf + DMAPADR0); /* Copy to here */
outl((unsigned long) mem, card->pci_conf + DMALADR0); /* from here */
outl(len, card->pci_conf + DMASIZ0); /* for this length */
outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */
/*
* We use the dmarx_in_progress flag to flag the channel as busy
*/
card->dmarx_in_progress = 1;
outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */
}
/*
* Send a frame through the DMA
*/
static inline void
fst_tx_dma(struct fst_card_info *card, unsigned char *skb,
unsigned char *mem, int len)
{
/*
* This routine will setup the DMA and start it.
*/
dbg(DBG_TX, "In fst_tx_dma %p %p %d\n", skb, mem, len);
if (card->dmatx_in_progress) {
dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n");
}
outl((unsigned long) skb, card->pci_conf + DMAPADR1); /* Copy from here */
outl((unsigned long) mem, card->pci_conf + DMALADR1); /* to here */
outl(len, card->pci_conf + DMASIZ1); /* for this length */
outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */
/*
* We use the dmatx_in_progress to flag the channel as busy
*/
card->dmatx_in_progress = 1;
outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */
}
/* Issue a Mailbox command for a port.
* Note we issue them on a fire and forget basis, not expecting to see an
* error and not waiting for completion.
*/
static void
fst_issue_cmd(struct fst_port_info *port, unsigned short cmd)
{
struct fst_card_info *card;
unsigned short mbval;
unsigned long flags;
int safety;
card = port->card;
spin_lock_irqsave(&card->card_lock, flags);
mbval = FST_RDW(card, portMailbox[port->index][0]);
safety = 0;
/* Wait for any previous command to complete */
while (mbval > NAK) {
spin_unlock_irqrestore(&card->card_lock, flags);
schedule_timeout_uninterruptible(1);
spin_lock_irqsave(&card->card_lock, flags);
if (++safety > 2000) {
printk_err("Mailbox safety timeout\n");
break;
}
mbval = FST_RDW(card, portMailbox[port->index][0]);
}
if (safety > 0) {
dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety);
}
if (mbval == NAK) {
dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n");
}
FST_WRW(card, portMailbox[port->index][0], cmd);