Skip to content
View solongjim's full-sized avatar

Block or report solongjim

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
5 results for source starred repositories written in Verilog
Clear filter

RISC-V CPU Core (RV32IM)

Verilog 1,369 249 Updated Sep 18, 2021

Open source retro ISA video card

Verilog 520 29 Updated Oct 24, 2024

基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现

Verilog 295 66 Updated May 2, 2023

Audio controller (I2S, SPDIF, DAC)

Verilog 82 19 Updated Sep 1, 2019

Minimal DVI / HDMI Framebuffer

Verilog 79 12 Updated Aug 9, 2020