FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Debug and parallel trace hardware for CORTEX-M (FPGA + support code)

CircuitVerse Primary Code Base

中文版 Parallel Programming for FPGAs

GPGPU microprocessor architecture

OpenXuantie - OpenC910 Core

Generates Makefiles to synthesize, place, and route verilog using Vivado

Package manager and build abstraction tool for FPGA/ASIC development

Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

32-bit Superscalar RISC-V CPU

Amaranth HDL framework for monitoring, hacking, and developing USB devices

Simple custom computer on a FPGA

Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

PCB for ULX3S FPGA R&D board

SystemVerilog to Verilog conversion

利用C++实现针对SystemVerilog的高性能在线编译系统，可将SystemVerilog源代码进行高鲁棒性的词法解析和常见语法分析和部分语义分析，生成可靠Abstract Syntax Tree，并提供Parser解析过程信息、报错信息和变量表，该在线编译系统通过webbenchh压力测试可以实现近万的QPS

Build your hardware, easily!

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication