From 0037d416591a4226f06711856d9a73a7edf2fd17 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Wolfgang=20R=C3=B6nninger?= <wroennin@student.ethz.ch>
Date: Mon, 13 Jan 2020 10:18:29 +0100
Subject: [PATCH] axi_isolate: Add comment for counter width

---
 src/axi_isolate.sv | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/axi_isolate.sv b/src/axi_isolate.sv
index 4c8c5d1e5..ca951fa58 100644
--- a/src/axi_isolate.sv
+++ b/src/axi_isolate.sv
@@ -32,7 +32,8 @@ module axi_isolate #(
   input  logic  isolate_i,  // isolate master port from slave port
   output logic  isolated_o  // master port is isolated from slave port
 );
-  localparam int unsigned CounterWidth = $clog2(NoPending + 32'd1) + 32'd1; // for atop injection
+  // plus 1 in clog for accouning no open transaction, plus one bit for atomic inhection
+  localparam int unsigned CounterWidth = $clog2(NoPending + 32'd1) + 32'd1;
   typedef logic [CounterWidth-1:0] cnt_t;
 
   enum logic [1:0] {