From 2af2d66f53ea2a7bcc351e55291326f02f86a9fe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Wolfgang=20R=C3=B6nninger?= Date: Thu, 20 Feb 2020 10:32:00 +0100 Subject: [PATCH] tb_axi_lite_to_apb: Update TB and synth bench to reflect changed `apb_req_o` port --- test/synth_bench.sv | 11 +++++------ test/tb_axi_lite_to_apb.sv | 20 ++++++++++---------- 2 files changed, 15 insertions(+), 16 deletions(-) diff --git a/test/synth_bench.sv b/test/synth_bench.sv index 1ae77cb3c..13eae3958 100644 --- a/test/synth_bench.sv +++ b/test/synth_bench.sv @@ -175,12 +175,11 @@ module synth_axi_lite_to_apb #( typedef logic [31:0] addr_t; typedef logic [DataWidth-1:0] data_t; typedef logic [DataWidth/8-1:0] strb_t; - typedef logic [NoApbSlaves-1:0] sel_t; typedef struct packed { addr_t paddr; // same as AXI4-Lite axi_pkg::prot_t pprot; // same as AXI4-Lite, specification is the same - sel_t psel; // onehot, one psel line per connected APB4 slave + logic psel; // one request line per connected APB4 slave logic penable; // enable signal shows second APB4 cycle logic pwrite; // write enable data_t pwdata; // write data, comes from W channel @@ -201,10 +200,10 @@ module synth_axi_lite_to_apb #( `AXI_LITE_TYPEDEF_REQ_T ( axi_req_t, aw_chan_t, w_chan_t, ar_chan_t ) `AXI_LITE_TYPEDEF_RESP_T ( axi_resp_t, b_chan_t, r_chan_t ) - axi_req_t axi_req; - axi_resp_t axi_resp; - apb_req_t apb_req; - apb_resp_t [NoApbSlaves-1:0] apb_resp; + axi_req_t axi_req; + axi_resp_t axi_resp; + apb_req_t [NoApbSlaves-1:0] apb_req; + apb_resp_t [NoApbSlaves-1:0] apb_resp; axi_pkg::xbar_rule_32_t [NoApbSlaves-1:0] addr_map; diff --git a/test/tb_axi_lite_to_apb.sv b/test/tb_axi_lite_to_apb.sv index c247e40d4..8ae0b4606 100644 --- a/test/tb_axi_lite_to_apb.sv +++ b/test/tb_axi_lite_to_apb.sv @@ -53,7 +53,7 @@ module tb_axi_lite_to_apb; typedef struct packed { addr_t paddr; axi_pkg::prot_t pprot; // same as AXI, this is allowed - sel_t psel; // onehot + logic psel; // onehot logic penable; logic pwrite; data_t pwdata; @@ -112,7 +112,7 @@ module tb_axi_lite_to_apb; axi_resp_t axi_resp; // slave structs - apb_req_t apb_req; + apb_req_t [NoApbSlaves-1:0] apb_req; apb_resp_t [NoApbSlaves-1:0] apb_resps; // ------------------------------- @@ -169,17 +169,17 @@ module tb_axi_lite_to_apb; for (genvar i = 0; i < NoApbSlaves; i++) begin : gen_apb_assertions // when psel is not asserted, the bus is in the idle state sequence APB_IDLE; - !apb_req.psel[i]; + !apb_req[i].psel; endsequence // when psel is set and penable is not, it is the setup state sequence APB_SETUP; - apb_req.psel[i] && !apb_req.penable; + apb_req[i].psel && !apb_req[i].penable; endsequence // when psel and penable are set it is the access state sequence APB_ACCESS; - apb_req.psel[i] && apb_req.penable; + apb_req[i].psel && apb_req[i].penable; endsequence // APB Transfer is APB state going from setup to access @@ -191,19 +191,19 @@ module tb_axi_lite_to_apb; (APB_SETUP |-> APB_TRANSFER)); apb_penable: assert property ( @(posedge clk) - (apb_req.penable && apb_req.psel[i] && apb_resps[i].pready |=> (!apb_req.penable))); + (apb_req[i].penable && apb_req[i].psel && apb_resps[i].pready |=> (!apb_req[i].penable))); control_stable: assert property ( @(posedge clk) - (APB_TRANSFER |-> $stable({apb_req.pwrite, apb_req.paddr}))); + (APB_TRANSFER |-> $stable({apb_req[i].pwrite, apb_req[i].paddr}))); apb_valid: assert property ( @(posedge clk) - (APB_TRANSFER |-> ((!{apb_req.pwrite, apb_req.pstrb, apb_req.paddr}) !== 1'bx))); + (APB_TRANSFER |-> ((!{apb_req[i].pwrite, apb_req[i].pstrb, apb_req[i].paddr}) !== 1'bx))); write_stable: assert property ( @(posedge clk) - ((apb_req.penable && apb_req.pwrite) |-> $stable(apb_req.pwdata))); + ((apb_req[i].penable && apb_req[i].pwrite) |-> $stable(apb_req[i].pwdata))); strb_stable: assert property ( @(posedge clk) - ((apb_req.penable && apb_req.pwrite) |-> $stable(apb_req.pstrb))); + ((apb_req[i].penable && apb_req[i].pwrite) |-> $stable(apb_req[i].pstrb))); end `endif // pragma translate_on