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mips_malta.c
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/*
* QEMU Malta board support
*
* Copyright (c) 2006 Aurelien Jarno
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/southbridge/piix.h"
#include "hw/isa/superio.h"
#include "hw/char/serial.h"
#include "net/net.h"
#include "hw/boards.h"
#include "hw/i2c/smbus_eeprom.h"
#include "hw/block/flash.h"
#include "hw/mips/mips.h"
#include "hw/mips/cpudevs.h"
#include "hw/pci/pci.h"
#include "sysemu/sysemu.h"
#include "sysemu/arch_init.h"
#include "qemu/log.h"
#include "hw/mips/bios.h"
#include "hw/ide.h"
#include "hw/irq.h"
#include "hw/loader.h"
#include "elf.h"
#include "exec/address-spaces.h"
#include "hw/sysbus.h" /* SysBusDevice */
#include "qemu/host-utils.h"
#include "sysemu/qtest.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "hw/empty_slot.h"
#include "sysemu/kvm.h"
#include "hw/semihosting/semihost.h"
#include "hw/mips/cps.h"
#define ENVP_ADDR 0x80002000l
#define ENVP_NB_ENTRIES 16
#define ENVP_ENTRY_SIZE 256
/* Hardware addresses */
#define FLASH_ADDRESS 0x1e000000ULL
#define FPGA_ADDRESS 0x1f000000ULL
#define RESET_ADDRESS 0x1fc00000ULL
#define FLASH_SIZE 0x400000
#define MAX_IDE_BUS 2
typedef struct {
MemoryRegion iomem;
MemoryRegion iomem_lo; /* 0 - 0x900 */
MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */
uint32_t leds;
uint32_t brk;
uint32_t gpout;
uint32_t i2cin;
uint32_t i2coe;
uint32_t i2cout;
uint32_t i2csel;
CharBackend display;
char display_text[9];
SerialState *uart;
bool display_inited;
} MaltaFPGAState;
#define TYPE_MIPS_MALTA "mips-malta"
#define MIPS_MALTA(obj) OBJECT_CHECK(MaltaState, (obj), TYPE_MIPS_MALTA)
typedef struct {
SysBusDevice parent_obj;
MIPSCPSState cps;
qemu_irq i8259[ISA_NUM_IRQS];
} MaltaState;
static struct _loaderparams {
int ram_size, ram_low_size;
const char *kernel_filename;
const char *kernel_cmdline;
const char *initrd_filename;
} loaderparams;
/* Malta FPGA */
static void malta_fpga_update_display(void *opaque)
{
char leds_text[9];
int i;
MaltaFPGAState *s = opaque;
for (i = 7 ; i >= 0 ; i--) {
if (s->leds & (1 << i)) {
leds_text[i] = '#';
} else {
leds_text[i] = ' ';
}
}
leds_text[8] = '\0';
qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n",
leds_text);
qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|",
s->display_text);
}
/*
* EEPROM 24C01 / 24C02 emulation.
*
* Emulation for serial EEPROMs:
* 24C01 - 1024 bit (128 x 8)
* 24C02 - 2048 bit (256 x 8)
*
* Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
*/
#if defined(DEBUG)
# define logout(fmt, ...) \
fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
#else
# define logout(fmt, ...) ((void)0)
#endif
struct _eeprom24c0x_t {
uint8_t tick;
uint8_t address;
uint8_t command;
uint8_t ack;
uint8_t scl;
uint8_t sda;
uint8_t data;
/* uint16_t size; */
uint8_t contents[256];
};
typedef struct _eeprom24c0x_t eeprom24c0x_t;
static eeprom24c0x_t spd_eeprom = {
.contents = {
/* 00000000: */
0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
/* 00000008: */
0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
/* 00000010: */
0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
/* 00000018: */
0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
/* 00000020: */
0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
/* 00000028: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000030: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000038: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
/* 00000040: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000048: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000050: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000058: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000060: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000068: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000070: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000078: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
},
};
static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size)
{
enum { SDR = 0x4, DDR2 = 0x8 } type;
uint8_t *spd = spd_eeprom.contents;
uint8_t nbanks = 0;
uint16_t density = 0;
int i;
/* work in terms of MB */
ram_size /= MiB;
while ((ram_size >= 4) && (nbanks <= 2)) {
int sz_log2 = MIN(31 - clz32(ram_size), 14);
nbanks++;
density |= 1 << (sz_log2 - 2);
ram_size -= 1 << sz_log2;
}
/* split to 2 banks if possible */
if ((nbanks == 1) && (density > 1)) {
nbanks++;
density >>= 1;
}
if (density & 0xff00) {
density = (density & 0xe0) | ((density >> 8) & 0x1f);
type = DDR2;
} else if (!(density & 0x1f)) {
type = DDR2;
} else {
type = SDR;
}
if (ram_size) {
warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB"
" of SDRAM", ram_size);
}
/* fill in SPD memory information */
spd[2] = type;
spd[5] = nbanks;
spd[31] = density;
/* checksum */
spd[63] = 0;
for (i = 0; i < 63; i++) {
spd[63] += spd[i];
}
/* copy for SMBUS */
memcpy(eeprom, spd, sizeof(spd_eeprom.contents));
}
static void generate_eeprom_serial(uint8_t *eeprom)
{
int i, pos = 0;
uint8_t mac[6] = { 0x00 };
uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
/* version */
eeprom[pos++] = 0x01;
/* count */
eeprom[pos++] = 0x02;
/* MAC address */
eeprom[pos++] = 0x01; /* MAC */
eeprom[pos++] = 0x06; /* length */
memcpy(&eeprom[pos], mac, sizeof(mac));
pos += sizeof(mac);
/* serial number */
eeprom[pos++] = 0x02; /* serial */
eeprom[pos++] = 0x05; /* length */
memcpy(&eeprom[pos], sn, sizeof(sn));
pos += sizeof(sn);
/* checksum */
eeprom[pos] = 0;
for (i = 0; i < pos; i++) {
eeprom[pos] += eeprom[i];
}
}
static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom)
{
logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data);
return eeprom->sda;
}
static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda)
{
if (eeprom->scl && scl && (eeprom->sda != sda)) {
logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
eeprom->tick, eeprom->scl, scl, eeprom->sda, sda,
sda ? "stop" : "start");
if (!sda) {
eeprom->tick = 1;
eeprom->command = 0;
}
} else if (eeprom->tick == 0 && !eeprom->ack) {
/* Waiting for start. */
logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
} else if (!eeprom->scl && scl) {
logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
if (eeprom->ack) {
logout("\ti2c ack bit = 0\n");
sda = 0;
eeprom->ack = 0;
} else if (eeprom->sda == sda) {
uint8_t bit = (sda != 0);
logout("\ti2c bit = %d\n", bit);
if (eeprom->tick < 9) {
eeprom->command <<= 1;
eeprom->command += bit;
eeprom->tick++;
if (eeprom->tick == 9) {
logout("\tcommand 0x%04x, %s\n", eeprom->command,
bit ? "read" : "write");
eeprom->ack = 1;
}
} else if (eeprom->tick < 17) {
if (eeprom->command & 1) {
sda = ((eeprom->data & 0x80) != 0);
}
eeprom->address <<= 1;
eeprom->address += bit;
eeprom->tick++;
eeprom->data <<= 1;
if (eeprom->tick == 17) {
eeprom->data = eeprom->contents[eeprom->address];
logout("\taddress 0x%04x, data 0x%02x\n",
eeprom->address, eeprom->data);
eeprom->ack = 1;
eeprom->tick = 0;
}
} else if (eeprom->tick >= 17) {
sda = 0;
}
} else {
logout("\tsda changed with raising scl\n");
}
} else {
logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl,
scl, eeprom->sda, sda);
}
eeprom->scl = scl;
eeprom->sda = sda;
}
static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
unsigned size)
{
MaltaFPGAState *s = opaque;
uint32_t val = 0;
uint32_t saddr;
saddr = (addr & 0xfffff);
switch (saddr) {
/* SWITCH Register */
case 0x00200:
val = 0x00000000;
break;
/* STATUS Register */
case 0x00208:
#ifdef TARGET_WORDS_BIGENDIAN
val = 0x00000012;
#else
val = 0x00000010;
#endif
break;
/* JMPRS Register */
case 0x00210:
val = 0x00;
break;
/* LEDBAR Register */
case 0x00408:
val = s->leds;
break;
/* BRKRES Register */
case 0x00508:
val = s->brk;
break;
/* UART Registers are handled directly by the serial device */
/* GPOUT Register */
case 0x00a00:
val = s->gpout;
break;
/* XXX: implement a real I2C controller */
/* GPINP Register */
case 0x00a08:
/* IN = OUT until a real I2C control is implemented */
if (s->i2csel) {
val = s->i2cout;
} else {
val = 0x00;
}
break;
/* I2CINP Register */
case 0x00b00:
val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom));
break;
/* I2COE Register */
case 0x00b08:
val = s->i2coe;
break;
/* I2COUT Register */
case 0x00b10:
val = s->i2cout;
break;
/* I2CSEL Register */
case 0x00b18:
val = s->i2csel;
break;
default:
#if 0
printf("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
addr);
#endif
break;
}
return val;
}
static void malta_fpga_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MaltaFPGAState *s = opaque;
uint32_t saddr;
saddr = (addr & 0xfffff);
switch (saddr) {
/* SWITCH Register */
case 0x00200:
break;
/* JMPRS Register */
case 0x00210:
break;
/* LEDBAR Register */
case 0x00408:
s->leds = val & 0xff;
malta_fpga_update_display(s);
break;
/* ASCIIWORD Register */
case 0x00410:
snprintf(s->display_text, 9, "%08X", (uint32_t)val);
malta_fpga_update_display(s);
break;
/* ASCIIPOS0 to ASCIIPOS7 Registers */
case 0x00418:
case 0x00420:
case 0x00428:
case 0x00430:
case 0x00438:
case 0x00440:
case 0x00448:
case 0x00450:
s->display_text[(saddr - 0x00418) >> 3] = (char) val;
malta_fpga_update_display(s);
break;
/* SOFTRES Register */
case 0x00500:
if (val == 0x42) {
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
break;
/* BRKRES Register */
case 0x00508:
s->brk = val & 0xff;
break;
/* UART Registers are handled directly by the serial device */
/* GPOUT Register */
case 0x00a00:
s->gpout = val & 0xff;
break;
/* I2COE Register */
case 0x00b08:
s->i2coe = val & 0x03;
break;
/* I2COUT Register */
case 0x00b10:
eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01);
s->i2cout = val;
break;
/* I2CSEL Register */
case 0x00b18:
s->i2csel = val & 0x01;
break;
default:
#if 0
printf("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
addr);
#endif
break;
}
}
static const MemoryRegionOps malta_fpga_ops = {
.read = malta_fpga_read,
.write = malta_fpga_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void malta_fpga_reset(void *opaque)
{
MaltaFPGAState *s = opaque;
s->leds = 0x00;
s->brk = 0x0a;
s->gpout = 0x00;
s->i2cin = 0x3;
s->i2coe = 0x0;
s->i2cout = 0x3;
s->i2csel = 0x1;
s->display_text[8] = '\0';
snprintf(s->display_text, 9, " ");
}
static void malta_fgpa_display_event(void *opaque, int event)
{
MaltaFPGAState *s = opaque;
if (event == CHR_EVENT_OPENED && !s->display_inited) {
qemu_chr_fe_printf(&s->display, "\e[HMalta LEDBAR\r\n");
qemu_chr_fe_printf(&s->display, "+--------+\r\n");
qemu_chr_fe_printf(&s->display, "+ +\r\n");
qemu_chr_fe_printf(&s->display, "+--------+\r\n");
qemu_chr_fe_printf(&s->display, "\n");
qemu_chr_fe_printf(&s->display, "Malta ASCII\r\n");
qemu_chr_fe_printf(&s->display, "+--------+\r\n");
qemu_chr_fe_printf(&s->display, "+ +\r\n");
qemu_chr_fe_printf(&s->display, "+--------+\r\n");
s->display_inited = true;
}
}
static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
hwaddr base, qemu_irq uart_irq, Chardev *uart_chr)
{
MaltaFPGAState *s;
Chardev *chr;
s = g_new0(MaltaFPGAState, 1);
memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s,
"malta-fpga", 0x100000);
memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga",
&s->iomem, 0, 0x900);
memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga",
&s->iomem, 0xa00, 0x10000 - 0xa00);
memory_region_add_subregion(address_space, base, &s->iomem_lo);
memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
chr = qemu_chr_new("fpga", "vc:320x200", NULL);
qemu_chr_fe_init(&s->display, chr, NULL);
qemu_chr_fe_set_handlers(&s->display, NULL, NULL,
malta_fgpa_display_event, NULL, s, NULL, true);
s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq,
230400, uart_chr, DEVICE_NATIVE_ENDIAN);
malta_fpga_reset(s);
qemu_register_reset(malta_fpga_reset, s);
return s;
}
/* Network support */
static void network_init(PCIBus *pci_bus)
{
int i;
for (i = 0; i < nb_nics; i++) {
NICInfo *nd = &nd_table[i];
const char *default_devaddr = NULL;
if (i == 0 && (!nd->model || strcmp(nd->model, "pcnet") == 0))
/* The malta board has a PCNet card using PCI SLOT 11 */
default_devaddr = "0b";
pci_nic_init_nofail(nd, pci_bus, "pcnet", default_devaddr);
}
}
static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr,
int64_t kernel_entry)
{
uint16_t *p;
/* Small bootloader */
p = (uint16_t *)base;
#define NM_HI1(VAL) (((VAL) >> 16) & 0x1f)
#define NM_HI2(VAL) \
(((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1))
#define NM_LO(VAL) ((VAL) & 0xfff)
stw_p(p++, 0x2800); stw_p(p++, 0x001c);
/* bc to_here */
stw_p(p++, 0x8000); stw_p(p++, 0xc000);
/* nop */
stw_p(p++, 0x8000); stw_p(p++, 0xc000);
/* nop */
stw_p(p++, 0x8000); stw_p(p++, 0xc000);
/* nop */
stw_p(p++, 0x8000); stw_p(p++, 0xc000);
/* nop */
stw_p(p++, 0x8000); stw_p(p++, 0xc000);
/* nop */
stw_p(p++, 0x8000); stw_p(p++, 0xc000);
/* nop */
stw_p(p++, 0x8000); stw_p(p++, 0xc000);
/* nop */
/* to_here: */
if (semihosting_get_argc()) {
/* Preserve a0 content as arguments have been passed */
stw_p(p++, 0x8000); stw_p(p++, 0xc000);
/* nop */
} else {
stw_p(p++, 0x0080); stw_p(p++, 0x0002);
/* li a0,2 */
}
stw_p(p++, 0xe3a0 | NM_HI1(ENVP_ADDR - 64));
stw_p(p++, NM_HI2(ENVP_ADDR - 64));
/* lui sp,%hi(ENVP_ADDR - 64) */
stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_ADDR - 64));
/* ori sp,sp,%lo(ENVP_ADDR - 64) */
stw_p(p++, 0xe0a0 | NM_HI1(ENVP_ADDR));
stw_p(p++, NM_HI2(ENVP_ADDR));
/* lui a1,%hi(ENVP_ADDR) */
stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_ADDR));
/* ori a1,a1,%lo(ENVP_ADDR) */
stw_p(p++, 0xe0c0 | NM_HI1(ENVP_ADDR + 8));
stw_p(p++, NM_HI2(ENVP_ADDR + 8));
/* lui a2,%hi(ENVP_ADDR + 8) */
stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_ADDR + 8));
/* ori a2,a2,%lo(ENVP_ADDR + 8) */
stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size));
stw_p(p++, NM_HI2(loaderparams.ram_low_size));
/* lui a3,%hi(loaderparams.ram_low_size) */
stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
/* ori a3,a3,%lo(loaderparams.ram_low_size) */
/*
* Load BAR registers as done by YAMON:
*
* - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
* - set up PCI0 MEM0 at 0x10000000, size 0x8000000
* - set up PCI0 MEM1 at 0x18200000, size 0xbe00000
*
*/
stw_p(p++, 0xe040); stw_p(p++, 0x0681);
/* lui t1, %hi(0xb4000000) */
#ifdef TARGET_WORDS_BIGENDIAN
stw_p(p++, 0xe020); stw_p(p++, 0x0be1);
/* lui t0, %hi(0xdf000000) */
/* 0x68 corresponds to GT_ISD (from hw/mips/gt64xxx_pci.c) */
stw_p(p++, 0x8422); stw_p(p++, 0x9068);
/* sw t0, 0x68(t1) */
stw_p(p++, 0xe040); stw_p(p++, 0x077d);
/* lui t1, %hi(0xbbe00000) */
stw_p(p++, 0xe020); stw_p(p++, 0x0801);
/* lui t0, %hi(0xc0000000) */
/* 0x48 corresponds to GT_PCI0IOLD */
stw_p(p++, 0x8422); stw_p(p++, 0x9048);
/* sw t0, 0x48(t1) */
stw_p(p++, 0xe020); stw_p(p++, 0x0800);
/* lui t0, %hi(0x40000000) */
/* 0x50 corresponds to GT_PCI0IOHD */
stw_p(p++, 0x8422); stw_p(p++, 0x9050);
/* sw t0, 0x50(t1) */
stw_p(p++, 0xe020); stw_p(p++, 0x0001);
/* lui t0, %hi(0x80000000) */
/* 0x58 corresponds to GT_PCI0M0LD */
stw_p(p++, 0x8422); stw_p(p++, 0x9058);
/* sw t0, 0x58(t1) */
stw_p(p++, 0xe020); stw_p(p++, 0x07e0);
/* lui t0, %hi(0x3f000000) */
/* 0x60 corresponds to GT_PCI0M0HD */
stw_p(p++, 0x8422); stw_p(p++, 0x9060);
/* sw t0, 0x60(t1) */
stw_p(p++, 0xe020); stw_p(p++, 0x0821);
/* lui t0, %hi(0xc1000000) */
/* 0x80 corresponds to GT_PCI0M1LD */
stw_p(p++, 0x8422); stw_p(p++, 0x9080);
/* sw t0, 0x80(t1) */
stw_p(p++, 0xe020); stw_p(p++, 0x0bc0);
/* lui t0, %hi(0x5e000000) */
#else
stw_p(p++, 0x0020); stw_p(p++, 0x00df);
/* addiu[32] t0, $0, 0xdf */
/* 0x68 corresponds to GT_ISD */
stw_p(p++, 0x8422); stw_p(p++, 0x9068);
/* sw t0, 0x68(t1) */
/* Use kseg2 remapped address 0x1be00000 */
stw_p(p++, 0xe040); stw_p(p++, 0x077d);
/* lui t1, %hi(0xbbe00000) */
stw_p(p++, 0x0020); stw_p(p++, 0x00c0);
/* addiu[32] t0, $0, 0xc0 */
/* 0x48 corresponds to GT_PCI0IOLD */
stw_p(p++, 0x8422); stw_p(p++, 0x9048);
/* sw t0, 0x48(t1) */
stw_p(p++, 0x0020); stw_p(p++, 0x0040);
/* addiu[32] t0, $0, 0x40 */
/* 0x50 corresponds to GT_PCI0IOHD */
stw_p(p++, 0x8422); stw_p(p++, 0x9050);
/* sw t0, 0x50(t1) */
stw_p(p++, 0x0020); stw_p(p++, 0x0080);
/* addiu[32] t0, $0, 0x80 */
/* 0x58 corresponds to GT_PCI0M0LD */
stw_p(p++, 0x8422); stw_p(p++, 0x9058);
/* sw t0, 0x58(t1) */
stw_p(p++, 0x0020); stw_p(p++, 0x003f);
/* addiu[32] t0, $0, 0x3f */
/* 0x60 corresponds to GT_PCI0M0HD */
stw_p(p++, 0x8422); stw_p(p++, 0x9060);
/* sw t0, 0x60(t1) */
stw_p(p++, 0x0020); stw_p(p++, 0x00c1);
/* addiu[32] t0, $0, 0xc1 */
/* 0x80 corresponds to GT_PCI0M1LD */
stw_p(p++, 0x8422); stw_p(p++, 0x9080);
/* sw t0, 0x80(t1) */
stw_p(p++, 0x0020); stw_p(p++, 0x005e);
/* addiu[32] t0, $0, 0x5e */
#endif
/* 0x88 corresponds to GT_PCI0M1HD */
stw_p(p++, 0x8422); stw_p(p++, 0x9088);
/* sw t0, 0x88(t1) */
stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
stw_p(p++, NM_HI2(kernel_entry));
/* lui t9,%hi(kernel_entry) */
stw_p(p++, 0x8339); stw_p(p++, NM_LO(kernel_entry));
/* ori t9,t9,%lo(kernel_entry) */
stw_p(p++, 0x4bf9); stw_p(p++, 0x0000);
/* jalrc t8 */
}
/*
* ROM and pseudo bootloader
*
* The following code implements a very very simple bootloader. It first
* loads the registers a0 to a3 to the values expected by the OS, and
* then jump at the kernel address.
*
* The bootloader should pass the locations of the kernel arguments and
* environment variables tables. Those tables contain the 32-bit address
* of NULL terminated strings. The environment variables table should be
* terminated by a NULL address.
*
* For a simpler implementation, the number of kernel arguments is fixed
* to two (the name of the kernel and the command line), and the two
* tables are actually the same one.
*
* The registers a0 to a3 should contain the following values:
* a0 - number of kernel arguments
* a1 - 32-bit address of the kernel arguments table
* a2 - 32-bit address of the environment variables table
* a3 - RAM size in bytes
*/
static void write_bootloader(uint8_t *base, int64_t run_addr,
int64_t kernel_entry)
{
uint32_t *p;
/* Small bootloader */
p = (uint32_t *)base;
stl_p(p++, 0x08000000 | /* j 0x1fc00580 */
((run_addr + 0x580) & 0x0fffffff) >> 2);
stl_p(p++, 0x00000000); /* nop */
/* YAMON service vector */
stl_p(base + 0x500, run_addr + 0x0580); /* start: */
stl_p(base + 0x504, run_addr + 0x083c); /* print_count: */
stl_p(base + 0x520, run_addr + 0x0580); /* start: */
stl_p(base + 0x52c, run_addr + 0x0800); /* flush_cache: */
stl_p(base + 0x534, run_addr + 0x0808); /* print: */
stl_p(base + 0x538, run_addr + 0x0800); /* reg_cpu_isr: */
stl_p(base + 0x53c, run_addr + 0x0800); /* unred_cpu_isr: */
stl_p(base + 0x540, run_addr + 0x0800); /* reg_ic_isr: */
stl_p(base + 0x544, run_addr + 0x0800); /* unred_ic_isr: */
stl_p(base + 0x548, run_addr + 0x0800); /* reg_esr: */
stl_p(base + 0x54c, run_addr + 0x0800); /* unreg_esr: */
stl_p(base + 0x550, run_addr + 0x0800); /* getchar: */
stl_p(base + 0x554, run_addr + 0x0800); /* syscon_read: */
/* Second part of the bootloader */
p = (uint32_t *) (base + 0x580);
if (semihosting_get_argc()) {
/* Preserve a0 content as arguments have been passed */
stl_p(p++, 0x00000000); /* nop */
} else {
stl_p(p++, 0x24040002); /* addiu a0, zero, 2 */
}
/* lui sp, high(ENVP_ADDR) */
stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff));
/* ori sp, sp, low(ENVP_ADDR) */
stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff));
/* lui a1, high(ENVP_ADDR) */
stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff));
/* ori a1, a1, low(ENVP_ADDR) */
stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff));
/* lui a2, high(ENVP_ADDR + 8) */
stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff));
/* ori a2, a2, low(ENVP_ADDR + 8) */
stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff));
/* lui a3, high(ram_low_size) */
stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16));
/* ori a3, a3, low(ram_low_size) */
stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff));
/* Load BAR registers as done by YAMON */
stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */
#ifdef TARGET_WORDS_BIGENDIAN
stl_p(p++, 0x3c08df00); /* lui t0, 0xdf00 */
#else
stl_p(p++, 0x340800df); /* ori t0, r0, 0x00df */
#endif
stl_p(p++, 0xad280068); /* sw t0, 0x0068(t1) */
stl_p(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
#ifdef TARGET_WORDS_BIGENDIAN
stl_p(p++, 0x3c08c000); /* lui t0, 0xc000 */
#else
stl_p(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */
#endif
stl_p(p++, 0xad280048); /* sw t0, 0x0048(t1) */
#ifdef TARGET_WORDS_BIGENDIAN
stl_p(p++, 0x3c084000); /* lui t0, 0x4000 */
#else
stl_p(p++, 0x34080040); /* ori t0, r0, 0x0040 */
#endif
stl_p(p++, 0xad280050); /* sw t0, 0x0050(t1) */
#ifdef TARGET_WORDS_BIGENDIAN
stl_p(p++, 0x3c088000); /* lui t0, 0x8000 */
#else
stl_p(p++, 0x34080080); /* ori t0, r0, 0x0080 */
#endif
stl_p(p++, 0xad280058); /* sw t0, 0x0058(t1) */
#ifdef TARGET_WORDS_BIGENDIAN
stl_p(p++, 0x3c083f00); /* lui t0, 0x3f00 */
#else
stl_p(p++, 0x3408003f); /* ori t0, r0, 0x003f */
#endif
stl_p(p++, 0xad280060); /* sw t0, 0x0060(t1) */
#ifdef TARGET_WORDS_BIGENDIAN
stl_p(p++, 0x3c08c100); /* lui t0, 0xc100 */
#else
stl_p(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */
#endif
stl_p(p++, 0xad280080); /* sw t0, 0x0080(t1) */
#ifdef TARGET_WORDS_BIGENDIAN
stl_p(p++, 0x3c085e00); /* lui t0, 0x5e00 */
#else
stl_p(p++, 0x3408005e); /* ori t0, r0, 0x005e */
#endif
stl_p(p++, 0xad280088); /* sw t0, 0x0088(t1) */
/* Jump to kernel code */
stl_p(p++, 0x3c1f0000 |
((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
stl_p(p++, 0x37ff0000 |
(kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */
stl_p(p++, 0x03e00009); /* jalr ra */
stl_p(p++, 0x00000000); /* nop */
/* YAMON subroutines */
p = (uint32_t *) (base + 0x800);
stl_p(p++, 0x03e00009); /* jalr ra */
stl_p(p++, 0x24020000); /* li v0,0 */
/* 808 YAMON print */
stl_p(p++, 0x03e06821); /* move t5,ra */
stl_p(p++, 0x00805821); /* move t3,a0 */
stl_p(p++, 0x00a05021); /* move t2,a1 */
stl_p(p++, 0x91440000); /* lbu a0,0(t2) */
stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */
stl_p(p++, 0x10800005); /* beqz a0,834 */
stl_p(p++, 0x00000000); /* nop */
stl_p(p++, 0x0ff0021c); /* jal 870 */
stl_p(p++, 0x00000000); /* nop */
stl_p(p++, 0x1000fff9); /* b 814 */
stl_p(p++, 0x00000000); /* nop */
stl_p(p++, 0x01a00009); /* jalr t5 */
stl_p(p++, 0x01602021); /* move a0,t3 */
/* 0x83c YAMON print_count */
stl_p(p++, 0x03e06821); /* move t5,ra */
stl_p(p++, 0x00805821); /* move t3,a0 */
stl_p(p++, 0x00a05021); /* move t2,a1 */
stl_p(p++, 0x00c06021); /* move t4,a2 */
stl_p(p++, 0x91440000); /* lbu a0,0(t2) */
stl_p(p++, 0x0ff0021c); /* jal 870 */
stl_p(p++, 0x00000000); /* nop */
stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */
stl_p(p++, 0x258cffff); /* addiu t4,t4,-1 */
stl_p(p++, 0x1580fffa); /* bnez t4,84c */
stl_p(p++, 0x00000000); /* nop */
stl_p(p++, 0x01a00009); /* jalr t5 */
stl_p(p++, 0x01602021); /* move a0,t3 */
/* 0x870 */
stl_p(p++, 0x3c08b800); /* lui t0,0xb400 */
stl_p(p++, 0x350803f8); /* ori t0,t0,0x3f8 */
stl_p(p++, 0x91090005); /* lbu t1,5(t0) */
stl_p(p++, 0x00000000); /* nop */
stl_p(p++, 0x31290040); /* andi t1,t1,0x40 */
stl_p(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
stl_p(p++, 0x00000000); /* nop */
stl_p(p++, 0x03e00009); /* jalr ra */
stl_p(p++, 0xa1040000); /* sb a0,0(t0) */
}
static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index,
const char *string, ...)
{