forked from aliguori/qemu
-
Notifications
You must be signed in to change notification settings - Fork 12
/
css.c
2591 lines (2290 loc) · 74.8 KB
/
css.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Channel subsystem base support.
*
* Copyright 2012 IBM Corp.
* Author(s): Cornelia Huck <[email protected]>
*
* This work is licensed under the terms of the GNU GPL, version 2 or (at
* your option) any later version. See the COPYING file in the top-level
* directory.
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
#include "qemu/bitops.h"
#include "qemu/error-report.h"
#include "exec/address-spaces.h"
#include "cpu.h"
#include "hw/s390x/ioinst.h"
#include "hw/qdev-properties.h"
#include "hw/s390x/css.h"
#include "trace.h"
#include "hw/s390x/s390_flic.h"
#include "hw/s390x/s390-virtio-ccw.h"
#include "hw/s390x/s390-ccw.h"
typedef struct CrwContainer {
CRW crw;
QTAILQ_ENTRY(CrwContainer) sibling;
} CrwContainer;
static const VMStateDescription vmstate_crw = {
.name = "s390_crw",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT16(flags, CRW),
VMSTATE_UINT16(rsid, CRW),
VMSTATE_END_OF_LIST()
},
};
static const VMStateDescription vmstate_crw_container = {
.name = "s390_crw_container",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_STRUCT(crw, CrwContainer, 0, vmstate_crw, CRW),
VMSTATE_END_OF_LIST()
},
};
typedef struct ChpInfo {
uint8_t in_use;
uint8_t type;
uint8_t is_virtual;
} ChpInfo;
static const VMStateDescription vmstate_chp_info = {
.name = "s390_chp_info",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT8(in_use, ChpInfo),
VMSTATE_UINT8(type, ChpInfo),
VMSTATE_UINT8(is_virtual, ChpInfo),
VMSTATE_END_OF_LIST()
}
};
typedef struct SubchSet {
SubchDev *sch[MAX_SCHID + 1];
unsigned long schids_used[BITS_TO_LONGS(MAX_SCHID + 1)];
unsigned long devnos_used[BITS_TO_LONGS(MAX_SCHID + 1)];
} SubchSet;
static const VMStateDescription vmstate_scsw = {
.name = "s390_scsw",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT16(flags, SCSW),
VMSTATE_UINT16(ctrl, SCSW),
VMSTATE_UINT32(cpa, SCSW),
VMSTATE_UINT8(dstat, SCSW),
VMSTATE_UINT8(cstat, SCSW),
VMSTATE_UINT16(count, SCSW),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_pmcw = {
.name = "s390_pmcw",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(intparm, PMCW),
VMSTATE_UINT16(flags, PMCW),
VMSTATE_UINT16(devno, PMCW),
VMSTATE_UINT8(lpm, PMCW),
VMSTATE_UINT8(pnom, PMCW),
VMSTATE_UINT8(lpum, PMCW),
VMSTATE_UINT8(pim, PMCW),
VMSTATE_UINT16(mbi, PMCW),
VMSTATE_UINT8(pom, PMCW),
VMSTATE_UINT8(pam, PMCW),
VMSTATE_UINT8_ARRAY(chpid, PMCW, 8),
VMSTATE_UINT32(chars, PMCW),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_schib = {
.name = "s390_schib",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_STRUCT(pmcw, SCHIB, 0, vmstate_pmcw, PMCW),
VMSTATE_STRUCT(scsw, SCHIB, 0, vmstate_scsw, SCSW),
VMSTATE_UINT64(mba, SCHIB),
VMSTATE_UINT8_ARRAY(mda, SCHIB, 4),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_ccw1 = {
.name = "s390_ccw1",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT8(cmd_code, CCW1),
VMSTATE_UINT8(flags, CCW1),
VMSTATE_UINT16(count, CCW1),
VMSTATE_UINT32(cda, CCW1),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_ciw = {
.name = "s390_ciw",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT8(type, CIW),
VMSTATE_UINT8(command, CIW),
VMSTATE_UINT16(count, CIW),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_sense_id = {
.name = "s390_sense_id",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT8(reserved, SenseId),
VMSTATE_UINT16(cu_type, SenseId),
VMSTATE_UINT8(cu_model, SenseId),
VMSTATE_UINT16(dev_type, SenseId),
VMSTATE_UINT8(dev_model, SenseId),
VMSTATE_UINT8(unused, SenseId),
VMSTATE_STRUCT_ARRAY(ciw, SenseId, MAX_CIWS, 0, vmstate_ciw, CIW),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_orb = {
.name = "s390_orb",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(intparm, ORB),
VMSTATE_UINT16(ctrl0, ORB),
VMSTATE_UINT8(lpm, ORB),
VMSTATE_UINT8(ctrl1, ORB),
VMSTATE_UINT32(cpa, ORB),
VMSTATE_END_OF_LIST()
}
};
static bool vmstate_schdev_orb_needed(void *opaque)
{
return css_migration_enabled();
}
static const VMStateDescription vmstate_schdev_orb = {
.name = "s390_subch_dev/orb",
.version_id = 1,
.minimum_version_id = 1,
.needed = vmstate_schdev_orb_needed,
.fields = (VMStateField[]) {
VMSTATE_STRUCT(orb, SubchDev, 1, vmstate_orb, ORB),
VMSTATE_END_OF_LIST()
}
};
static int subch_dev_post_load(void *opaque, int version_id);
static int subch_dev_pre_save(void *opaque);
const char err_hint_devno[] = "Devno mismatch, tried to load wrong section!"
" Likely reason: some sequences of plug and unplug can break"
" migration for machine versions prior to 2.7 (known design flaw).";
const VMStateDescription vmstate_subch_dev = {
.name = "s390_subch_dev",
.version_id = 1,
.minimum_version_id = 1,
.post_load = subch_dev_post_load,
.pre_save = subch_dev_pre_save,
.fields = (VMStateField[]) {
VMSTATE_UINT8_EQUAL(cssid, SubchDev, "Bug!"),
VMSTATE_UINT8_EQUAL(ssid, SubchDev, "Bug!"),
VMSTATE_UINT16(migrated_schid, SubchDev),
VMSTATE_UINT16_EQUAL(devno, SubchDev, err_hint_devno),
VMSTATE_BOOL(thinint_active, SubchDev),
VMSTATE_STRUCT(curr_status, SubchDev, 0, vmstate_schib, SCHIB),
VMSTATE_UINT8_ARRAY(sense_data, SubchDev, 32),
VMSTATE_UINT64(channel_prog, SubchDev),
VMSTATE_STRUCT(last_cmd, SubchDev, 0, vmstate_ccw1, CCW1),
VMSTATE_BOOL(last_cmd_valid, SubchDev),
VMSTATE_STRUCT(id, SubchDev, 0, vmstate_sense_id, SenseId),
VMSTATE_BOOL(ccw_fmt_1, SubchDev),
VMSTATE_UINT8(ccw_no_data_cnt, SubchDev),
VMSTATE_END_OF_LIST()
},
.subsections = (const VMStateDescription * []) {
&vmstate_schdev_orb,
NULL
}
};
typedef struct IndAddrPtrTmp {
IndAddr **parent;
uint64_t addr;
int32_t len;
} IndAddrPtrTmp;
static int post_load_ind_addr(void *opaque, int version_id)
{
IndAddrPtrTmp *ptmp = opaque;
IndAddr **ind_addr = ptmp->parent;
if (ptmp->len != 0) {
*ind_addr = get_indicator(ptmp->addr, ptmp->len);
} else {
*ind_addr = NULL;
}
return 0;
}
static int pre_save_ind_addr(void *opaque)
{
IndAddrPtrTmp *ptmp = opaque;
IndAddr *ind_addr = *(ptmp->parent);
if (ind_addr != NULL) {
ptmp->len = ind_addr->len;
ptmp->addr = ind_addr->addr;
} else {
ptmp->len = 0;
ptmp->addr = 0L;
}
return 0;
}
const VMStateDescription vmstate_ind_addr_tmp = {
.name = "s390_ind_addr_tmp",
.pre_save = pre_save_ind_addr,
.post_load = post_load_ind_addr,
.fields = (VMStateField[]) {
VMSTATE_INT32(len, IndAddrPtrTmp),
VMSTATE_UINT64(addr, IndAddrPtrTmp),
VMSTATE_END_OF_LIST()
}
};
const VMStateDescription vmstate_ind_addr = {
.name = "s390_ind_addr_tmp",
.fields = (VMStateField[]) {
VMSTATE_WITH_TMP(IndAddr*, IndAddrPtrTmp, vmstate_ind_addr_tmp),
VMSTATE_END_OF_LIST()
}
};
typedef struct CssImage {
SubchSet *sch_set[MAX_SSID + 1];
ChpInfo chpids[MAX_CHPID + 1];
} CssImage;
static const VMStateDescription vmstate_css_img = {
.name = "s390_css_img",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
/* Subchannel sets have no relevant state. */
VMSTATE_STRUCT_ARRAY(chpids, CssImage, MAX_CHPID + 1, 0,
vmstate_chp_info, ChpInfo),
VMSTATE_END_OF_LIST()
}
};
typedef struct IoAdapter {
uint32_t id;
uint8_t type;
uint8_t isc;
uint8_t flags;
} IoAdapter;
typedef struct ChannelSubSys {
QTAILQ_HEAD(, CrwContainer) pending_crws;
bool sei_pending;
bool do_crw_mchk;
bool crws_lost;
uint8_t max_cssid;
uint8_t max_ssid;
bool chnmon_active;
uint64_t chnmon_area;
CssImage *css[MAX_CSSID + 1];
uint8_t default_cssid;
/* don't migrate, see css_register_io_adapters */
IoAdapter *io_adapters[CSS_IO_ADAPTER_TYPE_NUMS][MAX_ISC + 1];
/* don't migrate, see get_indicator and IndAddrPtrTmp */
QTAILQ_HEAD(, IndAddr) indicator_addresses;
} ChannelSubSys;
static const VMStateDescription vmstate_css = {
.name = "s390_css",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_QTAILQ_V(pending_crws, ChannelSubSys, 1, vmstate_crw_container,
CrwContainer, sibling),
VMSTATE_BOOL(sei_pending, ChannelSubSys),
VMSTATE_BOOL(do_crw_mchk, ChannelSubSys),
VMSTATE_BOOL(crws_lost, ChannelSubSys),
/* These were kind of migrated by virtio */
VMSTATE_UINT8(max_cssid, ChannelSubSys),
VMSTATE_UINT8(max_ssid, ChannelSubSys),
VMSTATE_BOOL(chnmon_active, ChannelSubSys),
VMSTATE_UINT64(chnmon_area, ChannelSubSys),
VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(css, ChannelSubSys, MAX_CSSID + 1,
0, vmstate_css_img, CssImage),
VMSTATE_UINT8(default_cssid, ChannelSubSys),
VMSTATE_END_OF_LIST()
}
};
static ChannelSubSys channel_subsys = {
.pending_crws = QTAILQ_HEAD_INITIALIZER(channel_subsys.pending_crws),
.do_crw_mchk = true,
.sei_pending = false,
.do_crw_mchk = true,
.crws_lost = false,
.chnmon_active = false,
.indicator_addresses =
QTAILQ_HEAD_INITIALIZER(channel_subsys.indicator_addresses),
};
static int subch_dev_pre_save(void *opaque)
{
SubchDev *s = opaque;
/* Prepare remote_schid for save */
s->migrated_schid = s->schid;
return 0;
}
static int subch_dev_post_load(void *opaque, int version_id)
{
SubchDev *s = opaque;
/* Re-assign the subchannel to remote_schid if necessary */
if (s->migrated_schid != s->schid) {
if (css_find_subch(true, s->cssid, s->ssid, s->schid) == s) {
/*
* Cleanup the slot before moving to s->migrated_schid provided
* it still belongs to us, i.e. it was not changed by previous
* invocation of this function.
*/
css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, NULL);
}
/* It's OK to re-assign without a prior de-assign. */
s->schid = s->migrated_schid;
css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, s);
}
if (css_migration_enabled()) {
/* No compat voodoo to do ;) */
return 0;
}
/*
* Hack alert. If we don't migrate the channel subsystem status
* we still need to find out if the guest enabled mss/mcss-e.
* If the subchannel is enabled, it certainly was able to access it,
* so adjust the max_ssid/max_cssid values for relevant ssid/cssid
* values. This is not watertight, but better than nothing.
*/
if (s->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA) {
if (s->ssid) {
channel_subsys.max_ssid = MAX_SSID;
}
if (s->cssid != channel_subsys.default_cssid) {
channel_subsys.max_cssid = MAX_CSSID;
}
}
return 0;
}
void css_register_vmstate(void)
{
vmstate_register(NULL, 0, &vmstate_css, &channel_subsys);
}
IndAddr *get_indicator(hwaddr ind_addr, int len)
{
IndAddr *indicator;
QTAILQ_FOREACH(indicator, &channel_subsys.indicator_addresses, sibling) {
if (indicator->addr == ind_addr) {
indicator->refcnt++;
return indicator;
}
}
indicator = g_new0(IndAddr, 1);
indicator->addr = ind_addr;
indicator->len = len;
indicator->refcnt = 1;
QTAILQ_INSERT_TAIL(&channel_subsys.indicator_addresses,
indicator, sibling);
return indicator;
}
static int s390_io_adapter_map(AdapterInfo *adapter, uint64_t map_addr,
bool do_map)
{
S390FLICState *fs = s390_get_flic();
S390FLICStateClass *fsc = s390_get_flic_class(fs);
return fsc->io_adapter_map(fs, adapter->adapter_id, map_addr, do_map);
}
void release_indicator(AdapterInfo *adapter, IndAddr *indicator)
{
assert(indicator->refcnt > 0);
indicator->refcnt--;
if (indicator->refcnt > 0) {
return;
}
QTAILQ_REMOVE(&channel_subsys.indicator_addresses, indicator, sibling);
if (indicator->map) {
s390_io_adapter_map(adapter, indicator->map, false);
}
g_free(indicator);
}
int map_indicator(AdapterInfo *adapter, IndAddr *indicator)
{
int ret;
if (indicator->map) {
return 0; /* already mapped is not an error */
}
indicator->map = indicator->addr;
ret = s390_io_adapter_map(adapter, indicator->map, true);
if ((ret != 0) && (ret != -ENOSYS)) {
goto out_err;
}
return 0;
out_err:
indicator->map = 0;
return ret;
}
int css_create_css_image(uint8_t cssid, bool default_image)
{
trace_css_new_image(cssid, default_image ? "(default)" : "");
/* 255 is reserved */
if (cssid == 255) {
return -EINVAL;
}
if (channel_subsys.css[cssid]) {
return -EBUSY;
}
channel_subsys.css[cssid] = g_new0(CssImage, 1);
if (default_image) {
channel_subsys.default_cssid = cssid;
}
return 0;
}
uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc)
{
if (type >= CSS_IO_ADAPTER_TYPE_NUMS || isc > MAX_ISC ||
!channel_subsys.io_adapters[type][isc]) {
return -1;
}
return channel_subsys.io_adapters[type][isc]->id;
}
/**
* css_register_io_adapters: Register I/O adapters per ISC during init
*
* @swap: an indication if byte swap is needed.
* @maskable: an indication if the adapter is subject to the mask operation.
* @flags: further characteristics of the adapter.
* e.g. suppressible, an indication if the adapter is subject to AIS.
* @errp: location to store error information.
*/
void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable,
uint8_t flags, Error **errp)
{
uint32_t id;
int ret, isc;
IoAdapter *adapter;
S390FLICState *fs = s390_get_flic();
S390FLICStateClass *fsc = s390_get_flic_class(fs);
/*
* Disallow multiple registrations for the same device type.
* Report an error if registering for an already registered type.
*/
if (channel_subsys.io_adapters[type][0]) {
error_setg(errp, "Adapters for type %d already registered", type);
}
for (isc = 0; isc <= MAX_ISC; isc++) {
id = (type << 3) | isc;
ret = fsc->register_io_adapter(fs, id, isc, swap, maskable, flags);
if (ret == 0) {
adapter = g_new0(IoAdapter, 1);
adapter->id = id;
adapter->isc = isc;
adapter->type = type;
adapter->flags = flags;
channel_subsys.io_adapters[type][isc] = adapter;
} else {
error_setg_errno(errp, -ret, "Unexpected error %d when "
"registering adapter %d", ret, id);
break;
}
}
/*
* No need to free registered adapters in kvm: kvm will clean up
* when the machine goes away.
*/
if (ret) {
for (isc--; isc >= 0; isc--) {
g_free(channel_subsys.io_adapters[type][isc]);
channel_subsys.io_adapters[type][isc] = NULL;
}
}
}
static void css_clear_io_interrupt(uint16_t subchannel_id,
uint16_t subchannel_nr)
{
Error *err = NULL;
static bool no_clear_irq;
S390FLICState *fs = s390_get_flic();
S390FLICStateClass *fsc = s390_get_flic_class(fs);
int r;
if (unlikely(no_clear_irq)) {
return;
}
r = fsc->clear_io_irq(fs, subchannel_id, subchannel_nr);
switch (r) {
case 0:
break;
case -ENOSYS:
no_clear_irq = true;
/*
* Ignore unavailability, as the user can't do anything
* about it anyway.
*/
break;
default:
error_setg_errno(&err, -r, "unexpected error condition");
error_propagate(&error_abort, err);
}
}
static inline uint16_t css_do_build_subchannel_id(uint8_t cssid, uint8_t ssid)
{
if (channel_subsys.max_cssid > 0) {
return (cssid << 8) | (1 << 3) | (ssid << 1) | 1;
}
return (ssid << 1) | 1;
}
uint16_t css_build_subchannel_id(SubchDev *sch)
{
return css_do_build_subchannel_id(sch->cssid, sch->ssid);
}
void css_inject_io_interrupt(SubchDev *sch)
{
uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11;
trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid,
sch->curr_status.pmcw.intparm, isc, "");
s390_io_interrupt(css_build_subchannel_id(sch),
sch->schid,
sch->curr_status.pmcw.intparm,
isc << 27);
}
void css_conditional_io_interrupt(SubchDev *sch)
{
/*
* If the subchannel is not enabled, it is not made status pending
* (see PoP p. 16-17, "Status Control").
*/
if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA)) {
return;
}
/*
* If the subchannel is not currently status pending, make it pending
* with alert status.
*/
if (!(sch->curr_status.scsw.ctrl & SCSW_STCTL_STATUS_PEND)) {
uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11;
trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid,
sch->curr_status.pmcw.intparm, isc,
"(unsolicited)");
sch->curr_status.scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL;
sch->curr_status.scsw.ctrl |=
SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
/* Inject an I/O interrupt. */
s390_io_interrupt(css_build_subchannel_id(sch),
sch->schid,
sch->curr_status.pmcw.intparm,
isc << 27);
}
}
int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode)
{
S390FLICState *fs = s390_get_flic();
S390FLICStateClass *fsc = s390_get_flic_class(fs);
int r;
if (env->psw.mask & PSW_MASK_PSTATE) {
r = -PGM_PRIVILEGED;
goto out;
}
trace_css_do_sic(mode, isc);
switch (mode) {
case SIC_IRQ_MODE_ALL:
case SIC_IRQ_MODE_SINGLE:
break;
default:
r = -PGM_OPERAND;
goto out;
}
r = fsc->modify_ais_mode(fs, isc, mode) ? -PGM_OPERATION : 0;
out:
return r;
}
void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc)
{
S390FLICState *fs = s390_get_flic();
S390FLICStateClass *fsc = s390_get_flic_class(fs);
uint32_t io_int_word = (isc << 27) | IO_INT_WORD_AI;
IoAdapter *adapter = channel_subsys.io_adapters[type][isc];
if (!adapter) {
return;
}
trace_css_adapter_interrupt(isc);
if (fs->ais_supported) {
if (fsc->inject_airq(fs, type, isc, adapter->flags)) {
error_report("Failed to inject airq with AIS supported");
exit(1);
}
} else {
s390_io_interrupt(0, 0, 0, io_int_word);
}
}
static void sch_handle_clear_func(SubchDev *sch)
{
SCHIB *schib = &sch->curr_status;
int path;
/* Path management: In our simple css, we always choose the only path. */
path = 0x80;
/* Reset values prior to 'issuing the clear signal'. */
schib->pmcw.lpum = 0;
schib->pmcw.pom = 0xff;
schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO;
/* We always 'attempt to issue the clear signal', and we always succeed. */
sch->channel_prog = 0x0;
sch->last_cmd_valid = false;
schib->scsw.ctrl &= ~SCSW_ACTL_CLEAR_PEND;
schib->scsw.ctrl |= SCSW_STCTL_STATUS_PEND;
schib->scsw.dstat = 0;
schib->scsw.cstat = 0;
schib->pmcw.lpum = path;
}
static void sch_handle_halt_func(SubchDev *sch)
{
SCHIB *schib = &sch->curr_status;
hwaddr curr_ccw = sch->channel_prog;
int path;
/* Path management: In our simple css, we always choose the only path. */
path = 0x80;
/* We always 'attempt to issue the halt signal', and we always succeed. */
sch->channel_prog = 0x0;
sch->last_cmd_valid = false;
schib->scsw.ctrl &= ~SCSW_ACTL_HALT_PEND;
schib->scsw.ctrl |= SCSW_STCTL_STATUS_PEND;
if ((schib->scsw.ctrl & (SCSW_ACTL_SUBCH_ACTIVE |
SCSW_ACTL_DEVICE_ACTIVE)) ||
!((schib->scsw.ctrl & SCSW_ACTL_START_PEND) ||
(schib->scsw.ctrl & SCSW_ACTL_SUSP))) {
schib->scsw.dstat = SCSW_DSTAT_DEVICE_END;
}
if ((schib->scsw.ctrl & (SCSW_ACTL_SUBCH_ACTIVE |
SCSW_ACTL_DEVICE_ACTIVE)) ||
(schib->scsw.ctrl & SCSW_ACTL_SUSP)) {
schib->scsw.cpa = curr_ccw + 8;
}
schib->scsw.cstat = 0;
schib->pmcw.lpum = path;
}
/*
* As the SenseId struct cannot be packed (would cause unaligned accesses), we
* have to copy the individual fields to an unstructured area using the correct
* layout (see SA22-7204-01 "Common I/O-Device Commands").
*/
static void copy_sense_id_to_guest(uint8_t *dest, SenseId *src)
{
int i;
dest[0] = src->reserved;
stw_be_p(dest + 1, src->cu_type);
dest[3] = src->cu_model;
stw_be_p(dest + 4, src->dev_type);
dest[6] = src->dev_model;
dest[7] = src->unused;
for (i = 0; i < ARRAY_SIZE(src->ciw); i++) {
dest[8 + i * 4] = src->ciw[i].type;
dest[9 + i * 4] = src->ciw[i].command;
stw_be_p(dest + 10 + i * 4, src->ciw[i].count);
}
}
static CCW1 copy_ccw_from_guest(hwaddr addr, bool fmt1)
{
CCW0 tmp0;
CCW1 tmp1;
CCW1 ret;
if (fmt1) {
cpu_physical_memory_read(addr, &tmp1, sizeof(tmp1));
ret.cmd_code = tmp1.cmd_code;
ret.flags = tmp1.flags;
ret.count = be16_to_cpu(tmp1.count);
ret.cda = be32_to_cpu(tmp1.cda);
} else {
cpu_physical_memory_read(addr, &tmp0, sizeof(tmp0));
if ((tmp0.cmd_code & 0x0f) == CCW_CMD_TIC) {
ret.cmd_code = CCW_CMD_TIC;
ret.flags = 0;
ret.count = 0;
} else {
ret.cmd_code = tmp0.cmd_code;
ret.flags = tmp0.flags;
ret.count = be16_to_cpu(tmp0.count);
}
ret.cda = be16_to_cpu(tmp0.cda1) | (tmp0.cda0 << 16);
}
return ret;
}
/**
* If out of bounds marks the stream broken. If broken returns -EINVAL,
* otherwise the requested length (may be zero)
*/
static inline int cds_check_len(CcwDataStream *cds, int len)
{
if (cds->at_byte + len > cds->count) {
cds->flags |= CDS_F_STREAM_BROKEN;
}
return cds->flags & CDS_F_STREAM_BROKEN ? -EINVAL : len;
}
static inline bool cds_ccw_addrs_ok(hwaddr addr, int len, bool ccw_fmt1)
{
return (addr + len) < (ccw_fmt1 ? (1UL << 31) : (1UL << 24));
}
static int ccw_dstream_rw_noflags(CcwDataStream *cds, void *buff, int len,
CcwDataStreamOp op)
{
int ret;
ret = cds_check_len(cds, len);
if (ret <= 0) {
return ret;
}
if (!cds_ccw_addrs_ok(cds->cda, len, cds->flags & CDS_F_FMT)) {
return -EINVAL; /* channel program check */
}
if (op == CDS_OP_A) {
goto incr;
}
if (!cds->do_skip) {
ret = address_space_rw(&address_space_memory, cds->cda,
MEMTXATTRS_UNSPECIFIED, buff, len, op);
} else {
ret = MEMTX_OK;
}
if (ret != MEMTX_OK) {
cds->flags |= CDS_F_STREAM_BROKEN;
return -EINVAL;
}
incr:
cds->at_byte += len;
cds->cda += len;
return 0;
}
/* returns values between 1 and bsz, where bsz is a power of 2 */
static inline uint16_t ida_continuous_left(hwaddr cda, uint64_t bsz)
{
return bsz - (cda & (bsz - 1));
}
static inline uint64_t ccw_ida_block_size(uint8_t flags)
{
if ((flags & CDS_F_C64) && !(flags & CDS_F_I2K)) {
return 1ULL << 12;
}
return 1ULL << 11;
}
static inline int ida_read_next_idaw(CcwDataStream *cds)
{
union {uint64_t fmt2; uint32_t fmt1; } idaw;
int ret;
hwaddr idaw_addr;
bool idaw_fmt2 = cds->flags & CDS_F_C64;
bool ccw_fmt1 = cds->flags & CDS_F_FMT;
if (idaw_fmt2) {
idaw_addr = cds->cda_orig + sizeof(idaw.fmt2) * cds->at_idaw;
if (idaw_addr & 0x07 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) {
return -EINVAL; /* channel program check */
}
ret = address_space_read(&address_space_memory, idaw_addr,
MEMTXATTRS_UNSPECIFIED, &idaw.fmt2,
sizeof(idaw.fmt2));
cds->cda = be64_to_cpu(idaw.fmt2);
} else {
idaw_addr = cds->cda_orig + sizeof(idaw.fmt1) * cds->at_idaw;
if (idaw_addr & 0x03 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) {
return -EINVAL; /* channel program check */
}
ret = address_space_read(&address_space_memory, idaw_addr,
MEMTXATTRS_UNSPECIFIED, &idaw.fmt1,
sizeof(idaw.fmt1));
cds->cda = be64_to_cpu(idaw.fmt1);
if (cds->cda & 0x80000000) {
return -EINVAL; /* channel program check */
}
}
++(cds->at_idaw);
if (ret != MEMTX_OK) {
/* assume inaccessible address */
return -EINVAL; /* channel program check */
}
return 0;
}
static int ccw_dstream_rw_ida(CcwDataStream *cds, void *buff, int len,
CcwDataStreamOp op)
{
uint64_t bsz = ccw_ida_block_size(cds->flags);
int ret = 0;
uint16_t cont_left, iter_len;
ret = cds_check_len(cds, len);
if (ret <= 0) {
return ret;
}
if (!cds->at_idaw) {
/* read first idaw */
ret = ida_read_next_idaw(cds);
if (ret) {
goto err;
}
cont_left = ida_continuous_left(cds->cda, bsz);
} else {
cont_left = ida_continuous_left(cds->cda, bsz);
if (cont_left == bsz) {
ret = ida_read_next_idaw(cds);
if (ret) {
goto err;
}
if (cds->cda & (bsz - 1)) {
ret = -EINVAL; /* channel program check */
goto err;
}
}
}
do {
iter_len = MIN(len, cont_left);
if (op != CDS_OP_A) {
if (!cds->do_skip) {
ret = address_space_rw(&address_space_memory, cds->cda,
MEMTXATTRS_UNSPECIFIED, buff, iter_len,
op);
} else {
ret = MEMTX_OK;
}
if (ret != MEMTX_OK) {
/* assume inaccessible address */
ret = -EINVAL; /* channel program check */
goto err;
}
}
cds->at_byte += iter_len;
cds->cda += iter_len;
len -= iter_len;
if (!len) {
break;
}
ret = ida_read_next_idaw(cds);
if (ret) {
goto err;
}
cont_left = bsz;
} while (true);
return ret;
err:
cds->flags |= CDS_F_STREAM_BROKEN;
return ret;
}
void ccw_dstream_init(CcwDataStream *cds, CCW1 const *ccw, ORB const *orb)
{
/*
* We don't support MIDA (an optional facility) yet and we
* catch this earlier. Just for expressing the precondition.
*/
g_assert(!(orb->ctrl1 & ORB_CTRL1_MASK_MIDAW));
cds->flags = (orb->ctrl0 & ORB_CTRL0_MASK_I2K ? CDS_F_I2K : 0) |
(orb->ctrl0 & ORB_CTRL0_MASK_C64 ? CDS_F_C64 : 0) |
(orb->ctrl0 & ORB_CTRL0_MASK_FMT ? CDS_F_FMT : 0) |
(ccw->flags & CCW_FLAG_IDA ? CDS_F_IDA : 0);
cds->count = ccw->count;
cds->cda_orig = ccw->cda;
/* skip is only effective for read, read backwards, or sense commands */
cds->do_skip = (ccw->flags & CCW_FLAG_SKIP) &&
((ccw->cmd_code & 0x0f) == CCW_CMD_BASIC_SENSE ||
(ccw->cmd_code & 0x03) == 0x02 /* read */ ||
(ccw->cmd_code & 0x0f) == 0x0c /* read backwards */);
ccw_dstream_rewind(cds);
if (!(cds->flags & CDS_F_IDA)) {
cds->op_handler = ccw_dstream_rw_noflags;
} else {
cds->op_handler = ccw_dstream_rw_ida;
}
}
static int css_interpret_ccw(SubchDev *sch, hwaddr ccw_addr,
bool suspend_allowed)
{
int ret;
bool check_len;
int len;
CCW1 ccw;