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Commits on Mar 1, 2018

• nbd: BLOCK_STATUS constants

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  Vladimir Sementsov-Ogievskiy

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  ebblake

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  25c1467

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• nbd: change indenting in nbd.h

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  Vladimir Sementsov-Ogievskiy

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  ebblake

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• nbd: Honor server's advertised minimum block size

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  ebblake

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• Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20180301-v2' into staging

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  pm215

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• Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180301' into staging

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• Merge remote-tracking branch 'remotes/famz/tags/staging-pull-request' into staging

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• s390x/tcg: fix loading 31bit PSWs with the highest bit set

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  davidhildenbrand

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  cohuck

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• Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into staging

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• MAINTAINERS: Update my email address

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  alistair23

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  pm215

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• linux-user: Report AArch64 FP16 support via hwcap bits

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• target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU

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  pm215

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• arm/translate-a64: add all single op FP16 to handle_fp_1src_half

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  stsquad

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  pm215

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• arm/translate-a64: implement simd_scalar_three_reg_same_fp16

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  stsquad

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  pm215

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• arm/translate-a64: add all FP16 ops in simd_scalar_pairwise

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  stsquad

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  pm215

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• arm/translate-a64: add FP16 FMOV to simd_mod_imm

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  stsquad

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  pm215

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• arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16

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  stsquad

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• arm/helper.c: re-factor rsqrte and add rsqrte_f16

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  stsquad

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• arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16

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  stsquad

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• arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16

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  stsquad

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• arm/translate-a64: add FP16 FRECPE

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  stsquad

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• arm/helper.c: re-factor recpe and add recepe_f16

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  stsquad

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• arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16

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  stsquad

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• arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16

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  stsquad

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• arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16

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  stsquad

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• arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16

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  stsquad

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• arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16

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  stsquad

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• arm/translate-a64: initial decode for simd_two_reg_misc_fp16

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  stsquad

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  pm215

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• arm/translate-a64: add FP16 x2 ops for simd_indexed

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  stsquad

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• arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed

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  stsquad

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• arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16

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  stsquad

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• arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16

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  stsquad

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• arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16

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  stsquad

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• arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16

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  stsquad

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  pm215

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• arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16

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  stsquad

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  pm215

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• arm/translate-a64: initial decode for simd_three_reg_same_fp16

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  stsquad

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